TIME-BASED ARITHMETIC USING STEP FUNCTIONS Vishnu Ravinuthula and John G. Harris Computational NeuroEngineering Lab University of Florida Gainesville, FL 32611 vishnu,
[email protected]fl.edu ABSTRACT I2
I1
We describe a set of basic circuit building blocks for computation using an analog temporal step function representation for the inputs and outputs. Methods for computing weighted averages and thresholded differences are described. These techniques have advantages as CMOS process technologies scale since they minimize the analog circuitry required. We show an example of a time-based edge detector that directly interfaces to the output of a time-to-first spike imager.
t1
M1
M2 t2 t OUT
C
VTH
1. INTRODUCTION Fig. 1. Pulse Arithmetic - Basic Block The idea of performing computation using the timing of events is shared with the most powerful existing computer: the human brain. The brain is an analog computer but it does not transmit continuous analog voltages due to noise and cross talk susceptibility. Instead, information is represented using the timing of asynchronous digital-like pulses. Since our best man-made engineered solutions pale in comparison to human performance in common sensory processing tasks, it is worthwhile to study how biology achieves such amazing performance. Independent of any biological motivation, it is also making more and more sense to consider analog computation using the timing of asynchronous events from a purely engineering perspective. Through the electronics revolution over the past decades, CMOS process technology is shrinking the usable voltage swing, wreaking havoc on traditional analog circuit design. However, the faster “digital” transistors are better able to process timing signals leading us to consider analog computation more similar to that of the brain. This trend will likely continue with nanotechnology since even smaller voltage ranges and even faster devices are usually promised. Of course, CMOS technology is primarily scaling in favor of faster and faster digital devices, however power consumption is beginning to limit how far these digital circuits can scale. This material is based upon work supported by NASA under award no. NCC 2-1363 and SRC under Task ID: 1049 - Crosscut Research.
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Time-based signal representations have been in use for many years, including such techniques as pulse-width modulation and sigma-delta converters but temporal codes are becoming more and more common with the rising popularity of such techniques as class D amplifiers, spike-based sensors and even ultra-wideband (UWB) signal transmission. However, these temporal codes are typically used as temporary representations and computation is only performed after translation to a traditional analog or digital form. In this paper we describe a set of basic circuit building blocks for computation using an analog temporal step function representation for the inputs and outputs. Section 2 describes the precise computation performed by each block. Section 3 describes a simulation of a time-based edge detector that interfaces directly to a time-to-first-spike imager. Conclusions and future work are discussed in Section 4. 2. PULSE ARITHMETIC - BASIC CIRCUIT Fig. 1 illustrates the basic elements used to perform a weighted sum of temporal signals. The basic block can have an arbitrary number of input steps but only two are shown for simplicity. The inverters would not be necessary if nfets were used to sink current or if an inverted step function was used to represent input and output values. The rising edges
,
,6&$6
of the input steps correspond to the time values t1 and t2 representing the two input values. The PMOS transistors M1 and M2 act as switches. The two current sources I1 and I2 are connected to the source of PMOS transistors charge the capacitor C depending on the timing of the step inputs. A comparator senses the voltage across the capacitor and outputs a step when the voltage reaches the threshold voltage VT H . The current sources I1 and I2 charge the capacitor during different time periods as shown in Fig. 2.
VC Fig. 3. Cadence-Spectre simulation output showing the arithmetic mean of two input steps
VTH
The minimum value of tOU T in equation (3) occurs if
Vtemp
tOU T = t2
0
t1
t2
tOUT
(4)
Substituting equation (4) to (3), we get
t
(I2 t2 − I1 t1 ) = CVT H
(5)
Fig. 2. Idealized graph showing the basic block’s capacitor voltages at different time periods
Therefore for general values of tOU T above the minimum value in equation (4),
Initially, the voltage across the capacitor (VC ) is reset to 0V. For simplicity, let t1 < t2 < tOU T . The capacitor voltage VC stays at 0V until the first step arrives at time t1 . Transistor M1 turns on and the voltage VC linearly increases with the current source I1 charging capacitor C. This linear increase continues until time t2 when the second step arrives. For purposes of the following discussion, the capacitor voltage at that instant is labelled Vtemp . The value of Vtemp is computed during the period t1 to t2 as I1 (1) Vtemp = (t2 − t1 ) C Similarly, during the period t2 to tOU T (the time for the capacitor to charge to VT H )
|I2 t2 − I1 t1 | < CVT H
VT H − Vtemp =
I1 + I2 (tOU T − t2 ) C
(2)
Solving equations (1) and (2) gives: tOU T =
I1 t1 + I2 t2 CVT H + I1 + I2 I1 + I2
(3)
where tOU T is the time when the output step makes its transition from low to high voltage. Equation (3) is symmetric with I1 t1 and I2 t2 so the assumption that t1 < t2 can be relaxed. However, we still need to assume that tOU T occurs after t1 and t2 to ensure the validity of the equations.
(6)
Equation (6) provides the relation to be met for equation (3) to be valid. For the special case where I1 = I2 = I, tOU T = where when
CVT H 2I
t1 + t2 CVT H + 2 2I
(7)
is a constant. The above equation is valid,
CVT H (8) I In other words, if the current sources I1 and I2 are equal, then the output step is the mean of t1 and t2 plus a programmable constant. Fig. 3 shows the Cadence-Spectre simulation results where the basic block was used to compute the arithmetic mean of two input steps. The values of t1 , t2 , C, VT H and I used in the simulation were 200µs, 400µs, 20pF , 2.5V and 50nA. The output expected from this block (from equation 7) was 800µs and the output obtained from simulations was 799µs. Random variations in this delay and in the current sources are of concern and will lead to inaccuracies in the calculations. For different values of I1 and I2 ,
,
|t1 − t2 |
