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Universal Approach to Modeling Current Mode Controlled Converters in Distributed Power Systems for Large-Signal Subsystem Interactions Investigation Runxin Wang, Student Member, IEEE, Jinjun Liu, Member, IEEE, Hao Wang, Student Member, IEEE School of Electrical Engineering, Xi’an Jiaotong University, Xi’an, CHINA E-mail: [email protected] Abstract-This paper proposes a universal approach (model) to deal with current mode controlled power modules while investigating large-signal interactions among subsystems in a distributed dc power system. By establishing a family of power stage models that embody nonlinearity to an algebraic operation block and keeping all components along in the external feedback control loops staying in simulation, simulation speed can be dramatically accelerated as well as large-signal dynamic properties can be reflected correctly. Mathematic derivation of the models is presented and simulation tests show the validity of the proposed approach.1 Index Terms-power supply, simulation, DPS, interaction

I.

INTRODUCTION

Just from the moment that power supply modules appeared, it has been a common way to form a workable power supply system by inter-connecting different converter modules. A simple but typical case is the system composed of an ac-dc power factor correction (PFC) converter and a downstream dcdc converter that provides power to the load (Fig. 1)[1]. With the requirements of more complex electronic equipments, many other modules may need to join the system and all these modules, together with their input filters, make an enlarged multi-module power system as shown in Fig. 2. This is an embryo of today’s distributed power system (DPS)[2]. In both above cases, each module (subsystem) was designed with aim at its own stand-alone operation and it is obviously too simple to regard them as ideal power sources or passive loads after system integration. Actually, the interaction among subsystems may occur and therefore cause performance degradation or even instability of the whole power system if any key parameters of modules being connected were not properly chosen. Researches on such source-load interactions, which originally took the form of input filter considerations, had a long history and literatures on this subject can extend back to at least 1970s. Small-signal stability issue of inter-connected systems on a certain quiescent operating point has been investigated in depth

and Middlebrook’s impedance criterion, which treats impedance ratio Zo/Zi as a minor loop gain (system loop gain) and checks it by Nyquist criterion, was proven to be a valid tool[3]. But for large-signal stability investigation purpose, so far there exist no thoroughly effective analytical method, since in those systems where one power supply drives many others or even many power supplies feed many others, the nonlinear global dynamic analysis is theoretically too difficult and the situation is far more complex than that in the local stability criterion around a quiescent operating point. As a result, by now computer simulation still remains a powerful, if not the only, measure in engineering practices to predict the interaction problem in large-signal behaviors before final hardware tests. Proper models are important to computer simulations.

This work was supported by the National Nature Science Foundation of China (NSFC) under Grant Number 50677053. This work was also supported in part by ASTEC Custom Power (HK) Ltd. and in part by grants from the Power Electronics Science and Education Development Program of Delta Environmental & Educational Foundation.

1-4244-0714-1/07/$20.00 ©2007 IEEE.

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Figure 1 A cascaded front-end system[1].

Figure 2 A typical dc distributed power system[2].

current rather than the switching duty cycle as that in voltage mode control, the close-looped converter indirectly achieves its output voltage regulation. Although there being more accurate (also more detailed) models of the current loop, in most cases it is a reasonably good assumption that the controlled current is proportional to the input voltage of the inner current loop, and hence, the current loop can be regarded as an transconductance amplifier. Seeing that many theoretical analyses have provided arguments of this assumption before, this paper takes simulation results in Fig. 4 as extra evidence. By using ideal switch models in SIMPLIS environment, Fig. 4 shows frequency response curves of a dc-dc converter and a PFC converter respectively. (The PFC converter was “frozen” to a specified operating point when measuring frequency response.) In both cases, the following observations exist: First, the voltage to current transfer function has a wide bandwidth and this makes current loops fast. Second, in the wide bandwidth frequency range, gain of voltage to current transfer function keeps flat and the phase shit is small. Third and finally, compared to current loop, the voltage loop gain has a very narrow bandwidth and this makes it much slower. With these observations, one can get an intuitive and logical explanation to the transconductance assumption when a slowly-varying control voltage is imposed to a fast-responding current loop.

-

vout

vc

Vref

Figure 3 An ideal current mode controlled power system.

15 -10 10 -20 5 -30

G ain /

0 G ain /

From an engineer’s standpoint, with sufficiently accurate models, one can get operation details in sight as clear as possible. However, to investigate interactions among different modules, simulations based on detailed power semiconductor device models or even ideal switch models, as those of any stand-alone systems, are too time-consuming and sometimes even have convergence difficulties. This problem is especially challenging to the virtual prototyping process[4] where for each performance specification a significant number of time domain simulations need to be run to verify or test the design or help to select the optimum component parameters. So purely adopting switch models for every module is not a practically good choice. It was claimed that averaged switch modeling approach could be used to carry out large-signal simulation in some specific occasions[5]. But due to that the switch duty cycle d(t) is not directly controlled by compensation output in current mode control converters, the derivation process of large-signal averaged relationships often seems terrifying and this extremely limited the application of this approach to practical engineering. Efforts never stopped in avoiding brute-force simulation and finding proper systematic level model for power modules. Among research achievements published in the past, paper [1] proposed a large-signal model of downstream dc-dc converters with constant power load (Fig. 1) by emulating the static input characteristics and considering some of startup and faulthanding properties. Continuing but extending the same idea by considering dynamic properties, this paper will propose a more universal approach that is applicable for current mode controlled modules including both PFC and dc-dc converters, for both static and dynamic analysis and for both fixed loads and variant loads. The rest of this paper is organized as follows. The two approximations upon current loop accepted by this paper to model the current mode controlled power stage are briefly surveyed in Section 2. The two-port modeling based on power invariance to four basic dc-dc power stages is presented in Section 3. Section 4 illustrates the method of realizing simulation and section 5 shows comparative results from simulation using different models. Conclusion remarks are given in section 6.

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0 0 -0.5 -20 -1

II. CURRENT LOOP APPROXIMATIONS

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40 20 -200

0 P has e / d eg ree s

P has e / d eg ree s

Current mode control takes on various looks in different application fields in a power system, among which peakcurrent mode control and average-current mode control are well known. No matter what topologies and control strategies were employed, the common fact exists that a current mode controlled converter contains two control loops. As shown in Fig. 3, the inner current loop uses its input voltage to control a specific current. The external voltage loop generates a control voltage by compensating the error signal of the output voltage, and this control voltage is provided to the inner loop as its input voltage. Thus, by directly controlling the inner loop

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f req / Hertz freq / Hertz

Figure 4 Frequency responses comparison between two control loops, for PFC and dc-dc converters respectively.

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Another issue comes from whether it is needed to make a distinction between average current sensing and peak current sensing during the process of modeling current loop. Imagine that a control voltage is followed by an average-sensed current and a peak-sensed current simultaneously. Apparently one can find that the peak-sensed current is lower than the averagesensed current by half of the peak-to-peak ripple magnitude. However by calculating this magnitude value as a function of input voltage and other design parameters, literatures have verified that this difference is negligible and it is a good assumption not to distinguish peak-current sensing and average-current sensing[6]. All these controlled currents in current mode controlled converters can be referred as “average current” generally. This paper accepts above two assumptions and the following work closely depends on them.

io u t

iin

uout

uin

，

Figure 5 Power stage of a boost converter.

u1

III. CANONICAL LOSSLESS POWER STAGE MODEL Power stage (excluding the output capacitor) in current mode controlled converters can be regarded as a two-port, as the boost converter example shown in Fig. 5. As transconductance assumption revealed, the control voltage generated by the voltage compensator is sent to and then followed accurately by a current within this two-port. This current corresponding to the control voltage could be input current iin(t), output current iout(t) or a certain composition of them. By defining the moving-averaged value of x(t) over an internal of length Ts as

x (t )

Ts

〈〉

=

1 Ts

∫

t +Ts

t

x (τ )dτ

(1)

and denoting it as x for simplicity, all variables belonging to the two-port i.e. the line voltage uin, the input current iin, the output voltage uout and the output current iout are converted to iin uout and corresponding averaged value uin iout respectively. Provided that the power stage is lossless, the energy drawn from the source by the input port of the power stage equals to the energy consumed by the output port plus the energy stored in energy storage components (inductors and capacitors) inside the power stage switch network at any time during a zero-state response. In occasions where all circuit variables have been averaged, this is equivalent to say that average power consumed by the input port of the power stage equals to the average power flowing out from the output port plus the reactive power occupied by dynamic components inside the power stage switch network at any time. This relationship, which reflects invariance of power, generally holds in any lossless power stages. Define an algebraic operation block as shown in Fig. 6, where variables only have arithmetic meanings, to implement the following operation, u1 (⋅) × i1 (⋅) = u2 (⋅) × i2 (⋅) (2) Then, if effects of energy storage in any power stages could be separated and embedded into variables in Eq. (2), one can get a family of canonical models based on invariance of power.

〈 〉

〈 〉，〈 〉，〈 〉

i1

u2

u1i1=u2i2

i2

Figure 6 An algebraic operation block.

Assume the converters started from zero initial condition at time t=0. Derivation for four basic converters follows below. Attention should be paid to that definition of reference direction of some variables in buck-boost and Ćuk converters differ from convention for convenience of deriving the models, as denoted in Table 1. A. Boost Converter Energy relation:

∫

t

0

uin (τ ) iin (τ )dτ

1 = L iL 2

2

t

+ ∫ uout (τ ) iout (τ )dτ

(3)

0

Considering iL= iin in this converter, its derivative to time leads to: ⎛ d iin ⎞ (4) ⎜ uin − L ⎟ iin = uout iout dt ⎠ ⎝ B. Buck Converter Energy relation:

∫

t

0

=

uin (τ ) iin (τ )dτ 1 L iout 2

2

Power balance relation:

444

t

+ ∫ uout (τ ) iout (τ )dτ 0

(5)

⎛

d iout dt

uin iin = ⎜ uout + L ⎝

⎞ ⎟ ⎠

Considering KCL constraint, (6)

iout

Buck-boost Converter With symbol and variable definitions in Table 1, energy equations: C.

t

1 L iL 2

t

+ ∫ uout (τ ) iout (τ )dτ 0

iL = iin + iout

=

in

out

out

L

⎛ ⎜ ⎜ ⎝

uout + L2

(8)

Power balance relation:

(u i (u

(11)

(12)

⎞ d iout 1 t + ∫ ( iout − iin )dτ ⎟⎟ 0 dt C ⎠

Simulation circuits based on all above results and corresponding topologies are listed in Table 1.

Considering KCL constraint,

iin

= iout

(7) 2

1 t ( iin (τ ) − iout (τ ) )dτ C ∫0

Power balance relation: ⎞ ⎛ d i 1 t iin ⎜⎜ uin − L1 in + ∫ ( iout − iin )dτ ⎟⎟ dt C 0 ⎠ ⎝

uin (τ ) iin (τ )dτ

∫0

=

uC =

d iin d iout - L dt dt d iin d iout + L + L dt dt

)

)

(9)

D. Ćuk Converter With symbol and variable definitions in Table 1, energy equations: t 1 1 2 2 ∫0 uin (τ ) iin (τ ) dτ = L1 iin + L2 iout 2 2 (10) t 1 2 + C uC + ∫ uout (τ ) iout (τ ) dτ 0 2

IV. REALIZING THE SIMULATION Algebraic operation defined in Fig. 6 can be implemented by multipliers and dividers available in most simulation environments. Hence, by correctly connecting these power stage models and other parts of the converter circuit, one can realize the simulation, as shown in Fig. 7. But before connecting voltage loop output to the power stage model, one must thoroughly know the relation between this command signal and the controlled current, which may differ from one topology to another, depending on the systems under study.

Table 1 Canonical power stage models of basic converters. Topologies iin

Power Stage Models iout

L

iin

+

uin

Buck

iin

iout

uin

Boost

di1 (t ) dt

_

+

iout

+

uout

u1i1=u2i2

i2

di2 ( t ) dt

L

_

di1 (t ) dt

+

u1i1 =u2i 2

i1

uout

uin

L

i2

_ i1

L

uout

di1 ( t ) dt

+

uout

uin

iin

Buck-boost

L

iin

iout

_

u1i1=u2i2

i1

uout

uin

di2 (t ) dt

L

_

di2 ( t ) dt

_

+

i2

iout

di1 (t ) dt

L1 i in

Ćuk

+

i1

uout

uin iout

445

_

1 t 1 t i2 (τ )dτ i1 (τ )dτ C ∫0 C ∫0

+

_ _

+

L2

u1i1 =u2i2

di2 (t ) 1 t i2 (τ )dτ dt C ∫0

+

_

+

1 t i1 (τ )dτ C ∫0

_ _

+

i2

Denoting the current command signal to the power stage as ictrl, then ictrl = KvC (13) In the cases of buck converter, ictrl controls the output current iout independently, and the input current iin is constrained by Eq. 6; In both the cases of boost converter and Ćuk converter, ictrl controls the input current iin independently, and the output current iout is constrained respectively by Eq. 4 or Eq. 12. Fig. 7 showed the connection relations of boost (or Ćuk) converter example. Situation in buck-boost converters becomes a little complicated since ictrl controls the sum of iin or iout , ictrl = iin + iout (14)

〈 〉

〈 〉 〈 〉

〈 〉

〈〉 〈 〉

〈〉 〈 〉

rather than iin or iout alone. Slight changes to the power stage model are needed to make a room for putting the input signal ictrl. From Eq. (8), Eq.(9) and Eq. (14), a new equation with canonical form can be derived: ⎛

ictrol ⎜ uin − L ⎝

dictrl ⎞ = iout dt ⎟⎠

(u

+ uout

in

)

(15)

Using Eq. (15), a modified power stage model could be drawn as shown in Fig. 8, where ictrl becomes an apparent input. So far, by properly connecting variables to the two-port power stage model, and keeping other components, especially those along in the external voltage loop, to stay as they were in the switch model as closely as possible, one can get the large-signal model, as the example indicated in Fig. 7.

v in Vref

vc

＋

ictrl

uin

uout

iin

iout

－

vo

iout

Figure 7 Proposed modeling approach.

iin uin

L

+

dictrl dt

−

+

u2

ictrl

i2

ictrl

u1 i1

÷ × ×

i2

uin

iout

−

uout

V. VALIDITY VERIFICATION Two examples are provided as follow to preliminarily show the validity of the proposed approach: 1) A PFC circuit based on Unitrode Application Note U-134 (for UC3854) but with modified component values and simulation parameters to emulate its operation under various conditions was modeled by using the proposed approach. Fig. 9 shows the original simulation circuit in SIMPLIS environment[7]. Fig. 10 shows its model established by adopting the proposed approach. Fig. 11 shows simulation waveforms, which were obtained from Fig. 10 and remains reasonable simulation accuracy. Comparing simulation speed between switch model and the newly-established model, CPU time occupied by simulation was reduced dramatically from 6 min 52.92 sec (switch model) to 9.32 sec (new model); 2) Simulation prediction to large-signal interaction between a forward dc-dc converter and its input filter. Fig. 12 shows switch model of a forward dc-dc converter, which is connected to a poorly-designed input filter. A long CPU time is needed to spend only for discovering an oscillation with divergent amplitude, as shown in Fig. 13. Using proposed model shown in Fig. 14 makes things easier. A much longer operation process simulation (1 second versus 100 ms) needs less CPU time and one can conclude the system being unstable immediately by checking the amplitude envelopes. VI. CONCLUSION This paper proposes a universal approach (model) to deal with current mode controlled power modules while investigating large-signal interactions among subsystems in a distributed dc power system by computer simulation. The contributions mainly appeared in two aspects: First, establishing a family of power stage models that concentrate nonlinearity to an algebraic operation block by considering the invariance of power; Second, keeping all components along in external feedback control loops staying in simulation so to correctly reflect dynamic properties. Compared to other potential models, the proposed model has a remarkable merit that it is very easy to be derived from an existing switch model by just replacing the power stage. It is worth of mentioning that the proposed approach is targeted to model well-designed power supply modules and attentions were given to the interactions among different modules. If being put into the engineering background of virtual prototyping[4,8,9,10], the proposed model is suitable to cover the level of subsystem interaction test or system interaction test. Tests that consider more circuit details need other models with different levels. ACKNOWLEDGMENT

i2

The authors thank Transim Technology Corporation for software supports.

Figure 8 Modified power stage model of buck-boost converter.

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D1 IN_P by t12p

1m

D5

L2

mur860

VOUT 511k R7

D3 VIN

IRF450

V1

by t12p

I_IN

C1 1U

D4

C2 450u

10

byD2 t12p

250m

by t12p

R3

FB

600 R2

10k R8

Q1

R1

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C11

220k

620p IC=6.35

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24k R17

C10

10k R16

ENA VSNS IAC VRMS

C8 47n IC=-2 180k R14

SS ISNS

FB

CT RSET GND

C4 1u

91k

15k R4

20k R12

C5 100n IC=10.5

20 V2

PK_LMT GT_DRV CA_OUT MULT VA_OUT

62p IC=6.35

R11

U1 UC3854

VCC VREF

C3 820p IC=0

C6 470n IC=1.9

C9 470p

Figure 9 A PFC circuit based on Unitrode Application Note U-134 in SIMPLIS environment, where UC3854 is used as the controller[7]. 5

1000

V10

V9

Dif f Probe

D1

VIN

by t12p S11K R12

1

V7 V1

R10 1u C8

10k R1

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1.5Meg

1

D3 by t12p

1K R13

1K R15

100k R14

E3

by t12p

X4 15 V11

NLB_MULT2_DIV1 N1 HLIM N2 D1 REF

I_in 1 IPROBE3

IPROBE1 IOUT

G1

NLB_MULT2_DIV1 N1 HLIM N2 D1 REF

R19 600 S2 600 R9

450u IC=1 C1

100k R11

G2

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1

V3

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D2 by t12p

47n

15 V4

C2 180k R3

910k R4

VA_OUT Ref erence 91k

X3

R5 100n IC=10 C7 C5 C6

20k R6

1 R2

15 V5

470n IC=2 C3

Ideal_Diode1

I deal_Diode

I1

1

7.5 V2

7.5 V6 E1

C4 1u IC=0

Figure 10 Simulation model established by adopting the proposed approach and with modified simulation parameters. 6

I_in / A

5 4 3 2 1

IOUT / A

0 3.5 3 2.5 2 1.5 1 0.5 0 -0.5 5 VA_OUT / V

4 3 2 1 0 -1

VOUT / V

-2 450 400 350 300 250 200 150 100 50 300 250 VIN / V

200 150 100 50 0 -50 0

0.2

0.4

time/Secs

Load = 600

0.6

Ω

0.8

1

Load = 1200

1.2

Ω

1.4

1.6

Load = 600

1.8

Ω

Figure 11 Simulation waveforms obtained from the model shown in Fig. 10.

447

200mSecs/div

REFERENCES IPROBE1 I_Source

1m

D1

10u

Vout_Filter

L1

10mq060n D2 10mq060n

560 R9 48 V3

[1]

VOUT

TX1

R8

L3

10u

1m C5

10 R1

C1 470u 10m C6

D3 mur120

V2

R4 3.8k 100n

1k R6 R5 1K

U1

UCC1800_CKT COMP REF DEVICE='UCC1800' FB VCC

3k R7

C3

CS

IRF540

CS

OUT

RC

GND

Q1

CS R2 100m

20k R3 C2 180p

Figure 12 A PFC circuit based on Unitrode Application Note U-134 in SIMPLIS environment, where UC3854 is used as the controller[7]. 2.5 2

I_Source / A

1.5 1 0.5 0 -0 .5 -1 -1 .5 49 .5 49

Vout_Filter / V

48 .5 48 47 .5 47 46 .5 46 14 12

VOUT / V

10 8

Jinjun Liu, T.G. Wilson, Qun Zhao, Wei Dong and F.C. Lee, “Largesignal model of a downstream DC/DC converter for analysis and design of front-end PFC rectifier using computer simulation,” IEEE APEC 2003, pp. 1002-1007, 2003. [2] A. Altowati, T. Suntiot, and K. Zenger, “Input filter interactions in multimodule parallel switching-mode power supplies,” IEEE ICIT 2005, pp. 851-856, 2005. [3] R. D. Middlebrook, “Input filter considerations in design and applications of switching-mode regulators,” IEEE IAS 1976, pp. 22-26, 1976. [4] Q.M. Li, F.C. Lee and T.G. Wilson, “Design verification and testing of power supply system by using virtual prototype,” IEEE Trans. Power Electron., vol. 18, pp. 733-739, May 2003. [5] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics 2nd Edition, Kluwer Academic Publishers, MA, 2001. [6] Venable Industries, New Techniques for Measuring Feedback Loop Transfer Functions in Current Mode Converters, available on the Venable Industries web site. at: http://www.venable.biz/ [7] Transim Technology Corporation, SIMPLIS Reference Manual, UK: Cantena Software Ltd, 2003. [8] L. McGarry, K.Y. Qu, W. Lee and T.G. Wilson, “A virtual prototyping process for power supplies using an electronic design verification testing (eDVT) system,” IPEMC 2004, vol. 3, pp. 1689-1694, August 2004. [9] L. McGarry, K.Y. Qu, W. Lee and T.G. Wilson, “Quality assurance verification using a virtual prototyping system,” IEEE APEC 2005, vol. 2, pp. 1325-1331, March 2005. [10] Runxin Wang, Jinjun Liu, Pu Zhang, Junfeng Hou, “Study and Engineering Practice of Modeling IC Controllers for Switch Mode Power Supplies in SIMPLIS Environment,” IEEE APEC 2006, pp. 1216-1220.

6 4 2 0

20

40

60

80

tim e/mS e cs

2 0m Se c s/d iv

Figure 13 Simulation model established by adopting the proposed approach and with modified simulation parameters. 1000 V14 VOUT G3 NLB_MULT2_DIV1

150m

N1 N2 D1

I PROBE4 IOUT

HLIM REF

1

E1 1

R4 3.8k 1k

100 n

3k

R6

C3

R7

R5 1K

COMP

UCC1800_CKT COMP REF 'UCC1800' VCC

U1

470u IC=1 C13

10 R1

G1

FB

CS

OUT

RC

GND

IPROBE1 I_Source

V2

1m

IPROBE2 DC2DC_I in

Vout_F ilt er

L1 560 R2 48 V1

1m C1

10m C2

DC2DC_Iin / mA

COMP / V

Figure 14 Simulation waveforms obtained from the model shown in Fig. 10. 3.5 3 2.5 2 1.5 1 0.5 0 500 400 300 200 100

I_Source / A

0 10 6 2 -2 -6 -10

IOUT / A

10 8 6 4 2

Vout_Filter / V

58 54 50 46 42 38

VOUT / V

12 10 8 6 4 2 0 time/Sec s

0.2

0.4

0.6

0.8 200mSecs /div

Figure 15 Oscillations due to interaction with input filter. (Based on proposed model, a long process simulated, but less CPU time spent)

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