sequential/algorithmic/behavioral approach that, they learn in computer programming courses, and the par- allel/hardware/structural devices they learn about in.
Behavior t o Structure: Using Verilog and In-Circuit Emulation t o Teach How an Algorithm Becomes Hardware T.A. Bailey J.R. Cowles J.J. Cupal F.N. Engineer Computer Science Department Electrical Engineering Department University of Wyoming Laramie, Wyoming 82071
M.G. Arnold
root , [x' I 3 ] , of an unsigned binary integer provided on an external iinput bus, z. The most critical part of any problem is to choose an algorithm. Of course, many possible algorithms exist to solve this problem, but for simplicity, we will avoid any techniques that require multiplication, such as Newton's method. Instead, we will combine three simple techniques: a) the linear search algorithm that students learn in their introductory programming course; b) the polynomial table generation technique first realized in hardware (with cams and gears) by Babbage; and c) a push button user interface that allows the machine to communicate with the outside world. We begin our solution of this problem in the world of algorithms and software, without worrying about hardware, timing or interface details. We will state our initial solution as a single process in Verilog that takes no $time, yet one that uses many algorithmic steps before it arrives a t its solution. As such, this solution is not directly realizable in hardware. Our initial solution uses the simple assignment without time control (=) that works just like the assignment statements of C and Pascal. First of all, consider the simple linear search. If you have a monotone increasing function, f ( R I ) , you can find the least integer greater than or equal to its inverse, f-' (x), by searching for the smallest value of f ( R I ) that is greater than or equal to x:
Abstract W e present three stages of Verilog simulation (pure behavioral, mixed behavioral/structural, and pure structural), and a final stage of In-Circuit Emulation for translating an algorithm into hardware. Each successive stage i n the translation can be derived by minor editing of the previous stage. T h e pure behavioral stage uses a single Verilog process t o model an algorithmic state machine (ASM) using statements such as while and non-blocking assignment. T h e mixed stage keeps the algorithm i n a readable f o r m using statements such as while, but replaces the non-blocking assignment with a structural "architecture" that manipulates data. T h e third stage replaces statements such as while with a simulation of a conventional structural controller that generates the next state. T h e f i nal stage involves synthesizing actual hardware for the controller, and interfacing it t o the Verilog simulation of the architecture using an MS-DOS device driver that works in cooperation with a special module i n VeriWe11/PC.
Introduction We teach Verilog in a class containing both computer science and electrical engineering majors, who have very different technical backgrounds. We believe Verilog is an excellent vehicle to show both groups the intellectual journey from algorithms to hardware. In this class, we use three levels of abstraction in Verilog simulation (pure behavioral, mixed behavioral/structural, and pure structural), and then use a novel In-Circuit Emulation technique [3] that allows the students to interface their simulation to actual synthesized hardware, using a P C based implementation of Verilog, known as VeriWell/PC. Our purpose is to form a bridge in their minds between the sequential/algorithmic/behavioral approach that, they learn in computer programming courses, and the parallel/hardware/structural devices they learn about in a digital design course.
initial begin x = 125; R I = 0; R3 = 0; w h i l e (R3 < x) begin R I = R I + I; R3 = f(R1);
end $display("cube root=%d",Rl) ; end At first glance this appears to require multiplication, since f (RI) = R I 3 . The multiplication can be eliminated because we are not trying to compute an isolated value of f (RI) , but instead we want to compute a table of f ( R 1 ) a t equally spaced points ( R I = 0, 1, 2,3...) until we find the desired value of f ( R 1 ) . The
Example Problem To illustrate how our technique allows students to translate an algorithm into hardware, let's consider a small special purpose computer that solves a simple mathematical problem: computing the integer cube
19 0-8186-7082-7/95 $04.00 0 1995 IEEE
dependency because of the kind of assignment statement (=) used. Sequential programmers (including the students entering this class) rely on such dependencies, and in fact view them as synonymous with the passage of time. Verilog makes it clear that an algorithmic dependency does not necessarily advance $time. The eventual hardware realization will use a synchronous Algorithmic State Machine (ASM), and so the atomic operation in hardware corresponds to some state. To “weave” the algorithmic dependencies into states (that exist in physical $time), we use the following Verilog time control statement at appropriate places:
nth difference of equally spaced points of an nth degree polynomial is constant. In this case, the third difference is 6, and so the second difference is 6*R1: RI 0 R3=f(R1) 0 R2 6*R1 0
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Combining the linear search with Babbage’s approach, we have: RI = 0; R 2 = I; R3 = 0; while (R3 < x) begin R 4 = RI
