Upon burning this program onto FPGA board, the team plan to test out all combinations described in the simulation schema
VE270 Intro to Logic Design Lab Report
BY
3
Qi Chengyan 5120309454 & Xing Hua 5127169006
Lab Date: June 1, 2015 Report Date: June 1, 2015
Design of a SSD Driver
Objectives To design a Seven-Segment Display (SSD) control module that takes in a 3-bit Binary-Coded Decimal (BCD) and controls SSD display of 0-9. The design will be carried out in Xilinx ISE Design Suite and implemented on a FPGA board.
Problem Definition In all, this lab utilizes 8 switches as input and 4 Seven-Segment Display (SSD) as output. Output
• Use 4 SSD to display a decimal number output (0-9). Each SSD could be powered up individually. But all powered-on SSD will show the same decimal output. Input
• Use 4 switches (SW7 - SW4) to output a 4-bit BCD, corresponding to 0-9 in decimal. Decimal 10-15 are regarded as don’t care inputs.
• Use 4 switches (SW3 - SW0) to individually control the on/off of the 4 SSD we have. Functional Specification
• Cathodes of the 7 segments of all SSDs are wired into 7 wires, each wire controlling 4 segments on the same position. The control module developed will take in the 4-bit BCD input and output 7-bit signals to power up SSD segments. A total of 10 distinct signal combinations will show decimal number 0 to 9 on the SSD.
• All 7 Anodes of each SSD are wired together and controlled by a dedicated switch. A high voltage on the anode will power up all segments of the corresponding SSD.
System Partitioning Due to a complete independence of the decimal number displayed (0-9) and the on/off of each SSD, the system is partitioned into two parts. 1. Cathode part: the cathode part uses combinational logic to translate 4-bit BCD input into decimal numbers 0-9, and output the corresponding value to the 7 display segments. 2. Anode part: the anode part uses 4 switches to control the on/off of 4 SSD, independently. A flip of a switch turns on or off the one corresponding SSD. Page 2! of !12
Design Entry Entry #1. Truth Table of Cathode Part Based on SSD pin and a commonly accepted display method of number 0-9, as shown in Figure 1 and 2, we are designing the Cathode display in the truth table shown in Table 1.
Figure 2. SSD Display of Decimal Numbers (0-9) [Image source: bucknell.edu]
Figure 1. Naming convention of SSD segments [Image source: blogspot.com]
Table 1. Truth Table for the Cathode Part Input B0
B1
B2
B3
0
0
0
0
0
0
0
0
0
0
Decimal Num
Cathode Output A
B
C
D
E
F
G
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
1
0
2
0
0
1
0
0
1
0
0
1
1
3
0
0
0
0
1
1
0
0
1
0
0
4
1
0
0
1
1
0
0
0
1
0
1
5
0
1
0
0
1
0
0
0
1
1
0
6
0
1
0
0
0
0
0
0
1
1
1
7
0
0
0
1
1
1
1
1
0
0
0
8
0
0
0
0
0
0
0
1
0
0
1
9
0
0
0
0
1
0
0
1
0
1
0
10
x
x
x
x
x
x
x
1
0
1
1
11
x
x
x
x
x
x
x
1
1
0
0
12
x
x
x
x
x
x
x
1
1
0
1
13
x
x
x
x
x
x
x
1
1
1
0
14
x
x
x
x
x
x
x
1
1
1
1
15
x
x
x
x
x
x
x
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2
B0
B1
B2
B3
1
3
4
CA_inside
CB_inside
CC_inside
CD_inside
Page 4! of !12 CE_inside
CF_inside
CG_inside
B0_CG_inside
B1_CG_inside
CG_macro
B2_CG_inside
B3_CG_inside
B0_CF_inside
B1_CF_inside
CF_macro
B2_CF_inside
B3_CF_inside
B0_CE_inside
B1_CE_inside
CE_macro
B2_CE_inside
B3_CE_inside
B0_CD_inside
B1_CD_inside
CD_macro
B2_CD_inside
B3_CD_inside
B0_CC_inside
B1_CC_inside
CC_macro
B2_CC_inside
B3_CC_inside
B0_CB_inside
B1_CB_inside
CB_macro
B2_CB_inside
B3_CB_inside
B0_CA_inside
B1_CA_inside
CA_macro
B2_CA_inside
B3_CA_inside
5
CG_outside
CF_outside
CE_outside
CD_outside
CC_outside
CB_outside
CA_outside
SW0
SW1
SW2
SW3
6
AND2
AND2
AND2
AND2
7
AN3
AN2
AN1
AN0
Entry #2. Design Schematics for the entire circuit (please rotate the page to view)
Figure 3. Circuit Schematics (full view)
8
2
3
4
5
6
7
Entry #3. Design Schematics for the macro As we can see from entry #2, a part of circuit design is encapsulated into macros (e.g. CA_macro, CB_macro, …, CG_macro). Creating macros helps us focus on the current level of circuit design, and drastically reduces bug rate. Figure 4 shows the internal design of CA_macro. The other 6 macros are designed similarly with only difference in truth table entries.
D4_16E B3_CA_inside
A0
D0
B2_CA_inside
A1
D1
B1_CA_inside
A2
D2
B0_CA_inside
A3
D3 D4 D5 D6 D7
CA_inside
D8
OR2
D9 D10 D11 D12 VCC
D13 D14 E
D15
Figure 4. Circuit Schematics (macro view)
Test Plan For the cathode part, we plan to exhaust every possible combination on the truth table and compare simulation results with existing truth table results. For the anode part, we plan to open switches one at a time. Since their design are highly similar in nature and completely independent, we do not need to test each combination of the four switches that control the anodes. A tabular demonstration of the test plan is included in Figure 5 (See first 8 rows). 2
3
4
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5
6
7
Simulation Results Simulation result for the entire circuit is shown in Figure 5.
Figure 5. Simulation Result (b0-b3-sw3 are inputs; an0-an3-cg_outside are outputs)
Hardware Implementation and Testing Logic Synthesis Upon burning this program onto FPGA board, the team plan to test out all combinations described in the simulation schematics (Figure 5) and observe results. Then compare FPGA board reading with simulation results for discrepancy. • For the anode part, the team plan to switch up and down SW3, SW2, SW1 and SW0. The Page 6! of !12
corresponding SSD should turn on when switch is down, and off when switch is up. • For the cathode part, the team plan to exhaust all possible combinations of 4-bit BCD on SW7, SW6, SW5 and SW4 (ordering from most significant bit to least significant bit). Correspondingly, SSDs (the ones that are turned on) should display the decimal number (ranging from 0 to 9) based on the BCD input. All BCD inputs exceeding 9 (i.e. 10-15) should generate of SSD display of 8 (with all segments on).
FPGA Implementation The schematics described above are implemented on a XC3S1200E FPGA Board. The PIN assignment is shown in Figure 6.
Figure 6. I/O PIN Assignment for Implementation on XC3S1200E FPGA More specifically, 4 BCD input are controlled by SW7 to SW4, from the most significant to the Page 7! of !12
least significant bit. The 4 anodes are controlled by SW3 to SW0, corresponding to the 4 SSD’s in that order.
Board Testing (Describe how your design is tested on the hardware implementation.) First we test anode switches to see if they control the on/off of corresponding SSDs. Figure 7 shows an example where SSD_1 and SSD_3 are turned on, while SSD_0 and SSD_2 are turned off. Figure 8 demonstrates an exact opposite situation.
s
Figure 7. Anode control testing. SSD_1 and SSD_3 turned on; SSD_0 and SSD_2 turned off.
Figure 8. Anode control testing. SSD_0 and SSD_2 turned on; SSD_1 and SSD_3 turned off.
Then we exhaust all possible combinations on the SSD input through SW7 to SW4. Figure 9 to Figure 19 show the results. Note when BCD input exceeds 1001 (9 in decimal), output will be 8.
Figure 9. Cathode control testing. SSD outputs decimal 0, corresponding to BCD input 0000.
Figure 10. Cathode control testing. SSD outputs decimal 1, corresponding to BCD input 0001.
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Figure 11. Cathode control testing. SSD outputs decimal 2, corresponding to BCD input 0010.
Figure 12. Cathode control testing. SSD outputs decimal 3, corresponding to BCD input 0011.
Figure 13. Cathode control testing. SSD outputs decimal 4, corresponding to BCD input 0100.
Figure 14. Cathode control testing. SSD outputs decimal 5, corresponding to BCD input 0101.
Figure 15. Cathode control testing. SSD outputs decimal 6, corresponding to BCD input 0110.
Figure 16. Cathode control testing. SSD outputs decimal 7, corresponding to BCD input 0111.
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Figure 17. Cathode control testing. SSD outputs decimal 8, corresponding to BCD input 1000.
Figure 18. Cathode control testing. SSD outputs decimal 9, corresponding to BCD input 1001.
Figure 19. Cathode control testing. SSD outputs 8 (all segments on) when BCD input exceeds 1001.
Conclusions Through testing, we see a FPGA experimental output identical to simulation results. Thus we can confirm to have a correct schematics design, an accurate simulation and a smooth implementation. Through this lab, we have designed and implemented a SSD driver on a FPGA board. Utilizing combinational circuit design guidelines, we are able to convert a BCD to a decimal ranging from 0 to 9 and display the decimal on SSD. At the same time, we are capable of controlling the on/off of each SSD.
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Problems, if any, exists in design. The original schematics did not utilize macro to simplify each design step. Rather, we built a circuit straight out of AND, OR and NOT gates. But simulation gave us results not up to expectations. After a thorough and time-consuming debugging process, we found out a wrongly connected wire. Details of that wire and relevant schematics are shown in Appendix (Figure 20).
Form the exhausting debugging process we see the benefit of designing with macros. Encapsulation of detailed circuits allows for better focus on a correct design on that level of abstraction, and allows for easier debugging process once something went wrong. Such macro encapsulation ideas could be related to C++ object-oriented programming, where encapsulation allows for better focus and easier debugging. Just saying.
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Appendix The schematics in the circuit implemented are already shown in Figure 3 and Figure 4. The schematics attached here is the erroneously connected schematics, as discussed in the conclusion section.
Figure 20. The erroneous schematics. The wire marked in red is supposed to pass a value of B2B1’. In the erroneous connection shown here, the wire is connected to B2B1B0’. This example highlights the convenience and accuracy of designing with macros.
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