VHDL-AMS and Matlab/Simulink Modeling and Simulations

2011 Eighth International Conference on Information Technology: New Generations

A Novel Flash Fast-Locking Digital PLL: VHDL-AMS and Matlab/Simulink Modeling and Simulations By

Dr. Mahmoud Fawzy Wagdy Professor of Electrical Engineering, California State University, Long Beach (CSULB), 1250 Bellflower Blvd., Long Beach, CA 90840, USA &

Anurag Nannaka, MSEE, CSULB, M4 Wind Services, 5800 Skylab Rd., Huntington Beach, CA 92647, USA &

Rajeev K. N. Channegowda, MSEE, CSULB, 1250 Bellflower Blvd., Long Beach, CA 90840, USA Fast locking is therefore a necessity for clock/ data recovery circuits, frequency-hopping spreadspectrum communications, information technology, etc. However the literature on fast-locking PLLs is relatively very limited due to their more recent demand. Example research papers include: [2-5]. Examples US patents include: [6-8]. A number of industrial corporations produce fast-locking PLLs, e.g. Analog Devices Inc. [9], True Circuits Inc. [10], and National Semiconductor Inc. [11]. Frequency tracking is an effective frequency comparison technique which has a huge potential to decrease the lock time. Although some techniques have been employed to achieve effective frequency comparison, most of these techniques rely on counting the outputs of the phase frequency detector (PFD) to determine which frequency is higher. This process still depends on the phase of the signal resulting in high comparison time. In this paper, a standard frequency comparison technique is used which does not depend on the phase of the input signals.

ABSTRACT - A novel flash fast-locking digital phase-locked loop (DPLL) is presented and behaviorally modeled. The DPLL operation includes two stages: (1) a novel coarse-tuning stage for frequency tracking which employs a flash algorithm similar to the one employed in flash A/D converters (ADCs) and (2) a fine-tuning stage similar to conventional (classical) DPLLs. The coarse-tuning stage includes an array of frequency comparators, a priority encoder, a digital-to-analog converter (DAC), and control logic. Design considerations and implementations are presented in this paper. VHDLAMS (Simplorer) and Matlab/Simulink are used to design and perform simulations. The fast-locking DPLL reduces the lock time by a factor of about 1.80 compared to its conventional DPLL counterpart. Key Words: PLL, DPLL, fast-locking, coarse tuning, frequency tracking, flash algorithm, fine tuning, phase tracking, lock time, behavioral modeling, VHDL-AMS, MATLAB, SIMULINK.

II. THEORY OF OPERATION I. INTRODUCTION The block diagram of the novel flash DPLL employing DAC is shown in Fig. 1, which is similar to [12, Fig. 1] except that the DAC output is applied here to the LPF rather than directly to the VCO. It comprises two modes of operation, namely coarse tuning followed by fine tuning. Coarse tuning involves Frequency Comparator Array (FCA), Priority Encoder (PE), and a DAC. Fine tuning consists of Phase Frequency Detector (PFD), Charge Pump (CP), Lowpass Filter (LPF) and Voltage-Controlled Oscillator (VCO).

Phase-locked loops (PLLs) are most common in applications like wireless transceivers, cellular phones, etc. One of the important characteristic of a PLL is its lock time, which is amount of time a PLL takes to adapt and settle down to the changes in the input frequency. Conventional DPLL’s employ the technique of phase tracking which makes them misfits for contemporary high-speed high-throughput technology. The literature on conventional (classical) PLLs contains several thousands of designs and research papers, e.g. [1]. 978-0-7695-4367-3/11 $26.00 © 2011 IEEE DOI 10.1109/ITNG.2011.136

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Fig. 1. Block Diagram of the Novel Flash Fast-Locking DPLL (Employing DAC) The LPF input is selected using a monostable multivibrator. It produces a pulse when the encoder output changes which controls switching between the two modes. During the ON state, coarse tuning starts and the DAC output voltage is applied to the LPF to perform frequency tracking. At the OFF state, the conventional DPLL is active to perform phase tracking. When the input frequency changes, the FCA compares it with seven different reference frequencies and generates a new thermometer code. This code is fed to PE which generates a 3-bit code used to select the appropriate voltage via a DAC; it also triggers a monostable multivibrator during coarse tuning. The DAC output voltage is applied across LPF to change the VCO output. When the monostable multivibrator is off, coarse tuning is suspended and fine tuning starts. Hence the VCO output gets closer to the input signal and locks.

signals. Ultimately, when the DPLL is locked both the UP and DOWN signals remain low. B. Charge Pump (CP) and Lowpass Filter (LPF) The outputs of the PFD (UP and DOWN pulses) are combined into single output for driving the LPF using a CP. The block diagram for the CP and LPF is given in [13]. The CP sources current into the LPF during the UP pulse to increase the output frequency and sinks current during the DOWN pulse to decrease the output frequency. The LPF consists of C1 in parallel with the series combination R2, C2. The voltage across C2 increases/ decreases due to the PFD UP/DOWN pulses. C. Voltage-Controlled Oscillator (VCO) The VCO produces a digital pulse train whose frequency is proportional to the voltage across capacitor C1 of the LPF. The VCO block diagram is given in [13]. D. Frequency Comparator (FC) The FC is the most essential component of the Flash DPLL and its block diagram is given [14]. The FC has three inputs (F_input, F_vco, Reset). “F_input” is the input frequency and “F_vco” is the VCO output frequency. The advantage of this type of FCs, which uses ring counters, is that it always gives correct comparison results regardless of the phase shift between the F_input and F_vco signals. The counters are started and refreshed by using the “Reset” signal which receives a pulse every 20ns (in

III. FLASH DPLL DESIGN The individual blocks of Fig. 1 are explained in this section. The classical DPLL design equations are given in the Appendix. A. Phase Frequency Detector (PFD) The PFD block diagram is given in [13]. The inputs for the PFD are the input clock and the VCO output. The output UP/DOWN signals depend on the lead/lag relationship between the two input

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this design) thus starting a new frequency comparison cycle. The frequency comparator used in this work has three outputs (High, Low, and Timeout). Output High =’1’ when F_input > F_vco, thus the voltage to the VCO must be increased so that F_vco catches up with F_input. Similarly, output Low=’1’ when F_input < F_vco, thus the voltage to the VCO must be decreased so that F_vco catches up with F_input. The FC schematic is given in Fig. 2.

Fig. 3. Frequency Comparator Array F. Priority Encoder (PE) The purpose of the encoder is to take the input from the frequency comparator array and convert it to a 3-bit binary code. A priority encoder prioritizes the more significant bits in the data stream, and once it finds a high signal, it will ignore all other bits. The ENCODER used in this design is a 7-to-3 priority encoder, the truth table of which is given in Table 1.

Fig. 2. Frequency Comparator Using Ring Counters In cases when F_input and F_vco are close to each other the FC cannot decide during the allotted time (20ns in this case). To account for these cases, a Time-Out signal is added to the output of the FC. The idea is that ‘Time-Out = 1’ means that both F_input and F_vco are too close to each other, accordingly coarse tuning can be stopped and fine tuning can be started.

G. Digital-to-Analog Converter (DAC) The DAC transfer function used in this design is given in Table 2. Table 1. Priority Encoder Truth Table INPUT BITS (From FCA) OUTPUT BITS

E. Frequency Comparator Array (FCA) Frequency Comparators are arranged in the form of an array, as shown in Fig. 3, to accomplish fast locking employing the Flash algorithm. Each FC is provided with a reference frequency input. In this design, the FCA is composed of seven FCs, with 7 different reference frequencies which are equi-spaced over a frequency range of 2GHz. When F_in changes, the FCA start a comparison cycle at the end of which the FCA output is called “Thermometer Code”. The thermometer codes “0000000” through “1111111” correspond to the following F_in eight frequency ranges respectively: F_in