Xilinx Vivado Design Suite User Guide: High-Level Synthesis (UG902)
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Xilinx Vivado Design Suite User Guide: High-Level Synthesis (UG902)
Jun 19, 2013 - any errors contained in the Materials or to notify you of updates to the Materials or to product specific
Vivado Design Suite User Guide High-Level Synthesis
UG902 (v2013.2) June 19, 2013
Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of variable=a #pragma HLS resource core=AXI4LiteS meta variable=b // Define the pcore interfaces and group into AXI4 slave “slv1” #pragma HLS resource core=AXI4LiteS meta variable=return #pragma HLS resource core=AXI4LiteS meta variable=c #pragma HLS resource core=AXI4LiteS meta variable=d *a += *b; return (*c + *d); }
In the example above, ports “a” and “b” are grouped into a common AXI4-Lite Slave interface as shown in Figure 1-53. Block-level I/O protocol is explicitly set by applying interface mode ap_ctrl_hs to the function return. (This is the default but shown explicitly in this example). Grouping the
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Interface Management return port with ports “c” and “d”, means all the block level I/O protocol signals (ap_start, ap_done) are assigned to the AXI4-Lite Slave interface slv1. If the RESOURCE directive is applied using the GUI, the bus bundle string used to create the groupings (for example "-bus_bundle slv1") should be entered into the meta variable=return #pragma HLS RESOURCE core=RAM_1P meta variable=c
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Interface Management
... }
When a memory port is added to an AXI4 Lite Slave Interface following additional C functions are provided. In this case, since the function is called fir, file xfir.c would contain the following functions to manage the memory interface from the CPU: u32 u32 u32 u32 u32
SystemC AXI4 Lite Slave Interface An AXI4 Lite Slave interface can be added to any SystemC ports that are of the sc_in or sc_out type. To apply an AXI4 Lite interface to a SystemC design, the same process of assigning the ports to a named AXI4 Lite resource is used. However, when dealing with SystemC designs, and as explained in the section SystemC Bus Interfaces above, there are some differences in how the directives are applied to the design (and when using the GUI). The pragma directives for ports can only be applied inside design functions called by the SC_MODULE. An example best explains this. The following shows the top-level of a typical SystemC design. In this case, as is typical, the SC_MODULE and ports are defined in a header file: SC_MODULE(sc_sequ_cthread){ //Ports sc_in clk; sc_in reset; sc_in start; sc_in a; sc_in en; sc_out sum; sc_out vld; //Variables sc_uint acc; //Process Declaration void accum(); //Constructor SC_CTOR(sc_sequ_cthread){ //Process Registration SC_CTHREAD(accum,clk.pos()); reset_signal_is(reset,true); } };
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Interface Management The RESOURCE directives can be added directly to the source file. The directives can be applied to any member function of the SC_MODULE, however it is a good design practice to add them to the function where the variables are used. For this example, ports start, a, en, sum and valid are grouped into a single AXI4 Lite interface (using the same name “slv0” for each directive ensures all are grouped into the same interface). #include "sc_sequ_cthread.h"
//Initialization acc=0; sum.write(0); vld.write(false); wait(); // Process the port_map={{ port_map={{data_o_data TDATA} {data_o_strb TSTRB}} int i; DATA buf[N]; for (i = 0; i < N; i++) { buf[i] = data_i[i]; } for (i = 0; i < N; i++) { data_o[i] = buf[N-1-i]; } }
If the port mappings are applied using the GUI, each port map should be enclosed by braces {RTL_PORT AXI4_INTERFACE_SIGNAL} and all maps enclosed by an outer set of braces. The entire string must be entered into the port_map option box. For example: {{data_o_data TDATA} {data_o_strb TSTRB}}
Figure 1-55 shows the interface created from the example shown above, with RTL inputs and outputs grouped into separate interfaces.
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Interface Management
X-Ref Target - Figure 1-55
Figure 1-55:
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Pcore: AXI4 Stream Interfaces
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Interface Management This example used a unique struct. The header file ap_axi_sdata.h, located in the include directory in the Vivado HLS installation area, defines signed and unsigned structs for all possible signals in the AXI4 interface standard. These can be used in place of creating your own structs. •
ap_axi_s is a signed interpretation of the AXI4-Stream
•
ap_axi_u is an unsigned interpretation of the AXI4-Stream template struct ap_axis{ ap_int data; ap_uint keep; ap_uint strb; ap_uint user; ap_uint last; ap_uint id; ap_uint
Connecting an AXI4-Stream in EDK If a Vivado HLS block with an AXI4-Stream interface is to be connected inside the EDK GUI, the stream protocols have to be updated to match the stream protocols of the block(s) to which the AXI4-Streams connect. By default, Pcore blocks created by Vivado HLS have the following stream protocols (These can be accessed in the core configuration settings inside EDK): •
C_INPUT_STREAM_PROTOCOL = GENERIC
•
C_OUTPUT_STREAM_PROTOCOL = GENERIC
An AXI DMA block for example, will have the following stream protocols: •
To be able to connect two AXI4-Stream interfaces in the EDK GUI, each interface must have the same stream protocol.
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Interface Management 1. First, examination the core configuration settings for the block you wish to connect to and note the stream protocol for the port you wish to connect to. 2. Edit the core configurations for the Vivado HLS block and change the stream configuration setting for the port you wish to connect to match. In summary, to connect a Vivado HLS core to the AXI DMA example above, edit the core configuration setting in the Vivado HLS core and change the output stream port from GENERIC to C_INPUT_STREAM_PROTOCOL (to match the destination protocol) and change the input port from GENERIC to C_OUTPUT_STREAM_PROTOCOL (to match the source protocol). These changes enable the connection in the EDK GUI between a Vivado HLS block and the AXI DMA.
SystemC AXI4-Stream Interface An AXI4-Stream interface can be added to any SystemC ports that are of the sc_fifo_in or sc_fifo_out type. The same process of assigning the ports to an AXI4-Stream resource is used. As explained in the section SystemC Bus Interfaces above, there are some differences in how the directives are applied to the design (and when using the GUI). The pragma directives for ports can only be applied inside design functions called by the SC_MODULE. An example best explains this. The following shows the top-level of a typical SystemC design. In this case, as is typical, the SC_MODULE and ports are defined in a header file: SC_MODULE(sc_FIFO_port) { //Ports sc_in clock; sc_in reset; sc_in start; sc_out done; sc_fifo_out dout; sc_fifo_in din; //Variables int share_mem[100]; bool write_done; //Process Declaration void Prc1(); void Prc2(); //Constructor SC_CTOR(sc_FIFO_port) { //Process Registration SC_CTHREAD(Prc1,clock.pos()); reset_signal_is(reset,true);
High-Level Synthesis UG902 (v2013.2) June 19, 2013
The RESOURCE directives can be added directly to the source file. The directives can be applied to any member function of the SC_MODULE, however it is a good design practice to add them to the function where the variables are used. For this example, the directives are shown in the source code and ports din and dout are specified to have an AXI4Stream resource. #include "sc_FIFO_port.h" void sc_FIFO_port::Prc1() { //Initialization write_done = false; wait(); while(true) { while (!start.read()) wait(); write_done = false; for(int i=0;iburst_read(addr,2,tmp); // Port write bus_if->write(addr, tmp); // Port burst write bus_if->burst_write(addr,2,tmp); dout.write(tmp[0].to_int()); addr+=2; wait(); } }
When the port class AXI4M_bus_port is used in a design, it must have a matching HLS bus interface channel hls_bus_chn in the test bench, as shown in the following example: #include #include "tlm.h" using namespace tlm; #include "hls_bus_if.h" #include "AE_clock.h" #include "driver.h" #ifdef __RTL_SIMULATION__ #include "dut_rtl_wrapper.h" #define dut dut_rtl_wrapper #else #include "dut.h" #endif int sc_main (int argc , char *argv[]) { sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", SC_DO_NOTHING); sc_report_handler::set_actions( SC_ID_LOGIC_X_TO_BOOL_, SC_LOG); sc_report_handler::set_actions( SC_ID_VECTOR_CONTAINS_LOGIC_VALUE_, SC_LOG); sc_report_handler::set_actions( SC_ID_OBJECT_EXISTS_, SC_LOG); // hls_bus_chan // bus_variable(“name”, start_addr, end_addr) //
High-Level Synthesis UG902 (v2013.2) June 19, 2013
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