ORIGINALARBEITEN
Elektrotechnik & Informationstechnik (2012) 129/2: 88–101. DOI 10.1007/s00502-012-0083-3
Dynamic random-access memories without sense amplifiers S. M. Sharroush, Y. S. Abdalla, A. A. Dessouki, E.-S. A. El-Badawy
During the reading process of one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM) cells, the need arises to amplify a small voltage difference (in the order of 30 to 100 mV) by a suitable sense amplifier. The net result is that the higher voltage will rise to VDD while the lower one will decrease to 0 V. Simulation results for the 0.13 mm CMOS technology with VDD = 1.2 V reveal that approximately 40% of the read access time is associated with the sense amplifier operation in addition to the area required by each sense amplifier for each column in the memory array. In this paper, a novel readout technique for use with DRAM cells will be presented. This method depends on using an initially charged capacitance, then deciding whether to keep it charged or discharge it according to the stored data. Simulation results show that approximately 20% of the read access time is saved for the case of “1” storage which represents the worst case. The average power of the conventional scheme in case of stored “1” or “0” is 18.5 mW. The corresponding values for the proposed scheme are 9.8 mW and 2.25 mW. The significant reduction of the power consumption can be attributed to the reduction of the voltage swing of the bitline parasitic capacitance and taking the output data at a much smaller capacitance. The powerdelay products (PDPs) for the conventional and proposed readout schemes assuming the worst case (stored “1”) are 388.5 fJ and 166.6 fJ, respectively. Keywords: dynamic random-access memory; read access time; read cycle time; sense amplifier
Dynamische RAM-Speicher ohne Leseversta¨rker. Wa¨hrend des Leseprozesses von dynamischen Ein-Transistor-/Ein-Kondensator-DRAM-Speicherzellen (1T-1C DRAM) ist es notwendig, eine kleine Spannungsdifferenz (im Bereich von 30 mV bis 100 mV) mit einem entsprechenden Leseversta¨rker zu versta¨rken. Daraus resultierend wa¨chst die ho¨here Spannung zu VDD an, wa¨hrend die niedrigere Spannung auf 0 V sinkt. Die Simulationsergebnisse fu¨r die 0,13 mm CMOS-Technologie mit VDD = 1,2 V zeigen, dass ungefa¨hr 40 % der Lesezugriffszeit dem Leseversta¨rker zugeordnet werden kann – zusa¨tzlich zur beno¨tigten Siliziumfla¨che der Leseversta¨rker fu¨r jede Spalte im Speicherbereich. In der vorliegenden Arbeit wird eine neuartige Auslesetechnik fu¨r die Verwendung von DRAM-Zellen pra¨sentiert. Diese Methode basiert auf einer anfa¨nglich geladenen Kapazita¨t und der dann folgenden Entscheidung, ob sie entsprechend der gespeicherten Daten geladen bleiben oder wieder entladen werden soll. Die Simulationsergebnisse zeigen, dass ungefa¨hr 20 % der Lesezugriffszeit im Fall einer „1“-Speicherung, die den schlechtesten Fall darstellt, eingespart werden ko¨nnen. Die durchschnittliche Leistung der konventionellen Regelung im Fall einer „1“- oder „0“-Speicherung betra¨gt 18,5 mW. Die entsprechenden Werte fu¨r die vorgeschlagene Regelung lauten 9,8 mW und 2,25 mW. Die signifikante Verringerung des Stromverbrauchs kann der Reduzierung des Spannungshubs an der BitlineKapazita¨t und der Tatsache, dass die Ausgabedaten an einer wesentlich geringeren Kapazita¨t abgegriffen werden, zugeschrieben werden. Das Leistungsverzo¨gerungsprodukt (PDP) betra¨gt – ausgehend vom schlechtest mo¨glichen Fall (Speicherung „1“) – fu¨r das konventionelle bzw. vorgeschlagene Ausleseverfahren 388,5 fJ bzw. 166,6 fJ. Schlu¨sselwo¨rter: dynamischer RAM-Speicher; Lesezugriffszeit; Lesezykluszeit; Leseversta¨rker
Received September 26, 2011, accepted November 20, 2011 Springer-Verlag 2012
1. Introduction Dynamic random-access memories (DRAMs) are widely used in computer systems as the primary storage due to the relatively fast access especially if compared to hard disks. In this paper, the reading process of DRAMs will be addressed and a method will be proposed to speed-up the reading process of it without a sense amplifier. In fact, the reading process according to the proposed method depends on initially charging a parasitic capacitance to VDD, then deciding whether to discharge it or keep it charged depending on the stored data. The remainder of this paper is organized as follows: Section 2 discusses the reading process of 1T-1C DRAM cells according to the conventional method. The proposed scheme will be presented in Section 3 and will be investigated quantitatively in Section 4 in which the impact of the size of the cell capacitor, Cs, on the reading operation will be investigated and a mathematical relationship be-
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tween the cell capacitance, Cs, and the steady-state values of the bitline voltage in case of stored “0” and stored “1” will be derived. Also, the relationship between Cs and the read access times according to the conventional and proposed readout schemes is plotted on the same graph. The impact of technology scaling on the proposed readout scheme will be discussed in Section 5. The proposed scheme will be simulated for the 0.13 mm CMOS technology with VDD = 1.2 V with the simulation results presented in Section 6. The paper will be
Sharroush, Sherif M., Suez Canal University, Faculty of Engineering, Department of Electrical Engineering, Port Said, Egypt; Abdalla, Yasser S., Suez Canal University, Faculty of Industrial Education, Department of Electricity, Suez, Egypt; Dessouki, Ahmed A., Suez Canal University, Faculty of Engineering, Department of Electrical Engineering, Port Said, Egypt; El-Badawy, El-Sayed A., Alexandria University, Faculty of Engineering, Alexandria Higher Institute of Engineering and Technology, Alexandria, Egypt (E-mail:
[email protected])
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concluded in Section 7. Finally, Appendix A presents the derivation between the read access times and Cs. 2. Problem statement Although a variety of DRAM storage cells have been proposed over the years (Wood, Wood, 1965; ISSCC, Regitz, Karp, 1970; IEDM, Dennard, 1968), a particular cell, shown in Fig. 1, has become the industry standard. The cell consists of a single access transistor, M, and a storage capacitor, Cs, and thus is known as the 1T-1C DRAM cell. The cell stores one bit of information in the form of charge on Cs.
Bitline Wordline
M C BL
Cs
Fig. 1. The one-transistor one-capacitor dynamic RAM cell (Sedra, Smith, 1998) The write operation proceeds as follows: The wordline, WL, is first activated to a boosted voltage of VDD+Vthn. Depending on whether the data to be written is logic “1” or logic “0”, the bitline, BL, will be activated to VDD or 0 V, thus causing the storage capacitor, Cs, to be charged to VDD or discharge it to 0 V, respectively. Now, the conventional reading operation of the DRAM memory cells will be discussed. Refer to Fig. 2 for illustration (Jaeger, Blalock, 2004). First, the two bitlines, BL and BL, connected to the sense
BL
amplifier terminals will be precharged to VDD/2 and equalized to that voltage in order to block the effect of any noise on these lines where the complementary bitline is connected to a dummy cell. This is due to the fact that the differential voltage generated between the two bitlines, BL and BL, is small (typically 30 mV) for modern CMOS technologies. The wordline, WL, is then activated to a boosted voltage, VDD þ Vthn. This turns on Qc and charge sharing occurs between the cell capacitor, Cs, and the bitline parasitic capacitance, CBL. If the cell to be read stores “1”, then the cell capacitor, Cs, is initially charged to VDD and thus the bitline voltage, VBL, rises from VDD/2 to VDD/2 þ DV. The small differential voltage, DV, between the two bitlines, BL and BL, will be amplified by virtue of the sense amplifier until the BL rises to VDD and BL decreases to 0 V. The final bitline voltage, VDD, is used to writeback the stored data to the memory cell as the access transistor, Qc, is still activated. Had we assumed that the cell stores “0”, the cell capacitor, Cs, is initially discharged to 0 V and thus upon charge sharing between CBL and Cs, the bitline voltage, VBL, will decrease from VDD/2 to VDD/2–DV. By virtue of the positive feedback effect of the sense amplifier, the bitline voltage finally decreases to 0 V which will also be used to writeback the stored data on the memory cell. The steady-state voltages of the bitline can be found from the principle of charge conservation, that is; the charge lost by one capacitance equals that acquired by the other. In case of “1” storage, the cell capacitor, Cs, discharges from VDD to VBL1 while CBL charges from VDD/2 to VBL1. So, the amount of the charge lost by Cs is equal to that acquired by CBL, i.e. VDD ð1Þ Cs ½VDD VBL1 ¼ CBL VBL1 2 VBL1 ¼
Cs VDD þ CBL VDD 2 : Cs þ CBL
VBL0 ¼
WL Memory cell QC CS
ð2Þ
On the other hand, in case of “0” storage the capacitor, Cs, charges from 0 to VBL0 while CBL discharges from VDD/2 to VBL0. So, VDD VBL0 Cs ½VBL0 0 ¼ CBL ð3Þ 2
BL
CBL
ORIGINALARBEITEN
CBL V2DD : Cs þ CBL
ð4Þ
The main disadvantage of this reading scheme is the following: The output data will be available at the bitline after a relatively long time (21 ns according to our simulation for the 0.13 mm CMOS technology). This is due to the need to rise or decrease the voltage of the bitline parasitic capacitance, CBL, which is relatively large (typically 256 fF for the 0.13 mm CMOS technology) due to its connection to the access transistors in all the memory cells in the columns (typically there are 128 cells in each column).
C BL
Sense amplifier
Precharge
Fig. 2. The conventional reading scheme of the 1T-1C DRAM cell (Jaeger, Blalock, 2004)
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3. The proposed scheme Refer to Fig. 3 for illustration. Before discussing the proposed scheme, it must be noted that the output data will be available at the output of the inverter, inv2, that is at the Dout node. The proposed reading scheme will be discussed for the two cases of stored data “0” and “1”. Unlike the conventional reading scheme, the bitline parasitic capacitance, CBL, is precharged by the PMOS transistor, MP1, by virtue of the PRE signal to a voltage of Vthn not to VDD/2, where Vthn is the threshold voltage of the NMOS transistors. However, a point must be mentioned here about the conduction of MP1. It will be assumed here that Vthn = |Vthp|. So, if the threshold voltage of the PMOS transistor, MP1, is |Vthp|, then VSGMP1 = Vthn0 = Vthn = |Vthp|, thus it will not conduct. So, the threshold voltage of the precharge transistor, MP1, must be adjusted by body biasing for
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WL
Vthn PRE
MP1
QC CS
V DD PRE
M P2
inv1
C BL
M
Q inv2
C1
Dout Fig. 3. The 1T-1C DRAM cell along with the reading circuitry according to the proposed scheme
example (by the biasing voltage source, VB) (Sedra, Smith, 1998) so that VSGMP1 will be larger than |Vthp| and MP1 conducts. During the time interval at which the PRE signal is at logic “0”, the wordline signal is at logic “0” keeping the access transistor, Qc, deactivated, thus there will be no charge sharing between Cs and CBL. By virtue of the same precharge signal, PRE, the PMOS transistor, MP2, will be activated and charges the parasitic capacitance, C1, to VDD. So, the initial value of the Dout signal is zero. However, it will not be available for the data registers at this time as the final value of the output data is no longer available. Also, during this time interval, the transistor, M, will be deactivated and the inverter, inv1, output will not affect the bitline. Then, the PRE signal will be at logic “1” and the wordline signal, WL, will be activated to a boosted voltage of VDD+Vthn such that the access transistor, Qc, will be activated. Charge sharing will then occur between Cs and CBL. If the cell stores “0”, then Cs is initially discharged to 0 V. So, CBL will lose some of its charge through Cs. The bitline voltage, VBL, will thus be smaller than the threshold voltage of the NMOS transistor, Q. So, Q will be deactivated in this case and the capacitance, C1, will retain its charge. The inverter, inv1, output will thus be at logic “0”, and this “0” will be transferred to the bitline. In other words, both capacitors, CBL and Cs, will discharge through M and the NMOS transistor of the inverter, inv1. This acts to writeback the stored data on the cell capacitor. The main advantage gained from this technique is that the stored data will be available on the Dout line after a very short time interval. This is in contrast to the conventional method in which the data will be available on the bitline after a relatively longer period of time due to the sluggish charging and discharging of the bitline parasitic capacitance, CBL. The read access time can be defined as the time between the instant at which the address of the data is available on the address bus and the instant at which the data is available at the data bus. However, the read cycle time is defined as the minimum time between two successive read operations (Tocci, Widmer, 1998). So, the read access time of the proposed scheme is smaller than that of the conventional one while the read cycle time of the proposed
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scheme is approximately equal to or slightly less than that of the conventional one. Had we assumed that the cell stores “1”, then the cell capacitor, Cs, is initially precharged to VDD. Upon activation of the wordline, the bitline parasitic capacitance will gain some charge from Cs and thus its voltage will rise slightly to a voltage that is higher than Vthn. So, the NMOS transistor, Q, will conduct and the capacitance, C1, will discharge to 0 V through Q. The inverter, inv1, output will thus be at logic “1” and both the bitline parasitic capacitance, CBL, and Cs will be charged to VDD and the data will be written back. An important note here about the synchronization of the PRE signal must be mentioned. The activation signal of the writeback transistor, M, must be synchronized with the discharging process of C1 and the time delay of the inverter, inv1. If this signal is activated early, the output of the inverter, inv1, will still be at logic “0”, so the data will be erroneously written back. This point is of no concern with reading logic “0” as in this case the capacitance, C1, will remain charged at VDD and thus the output of the inverter, inv1, will remain at 0 V. An important role performed by M in addition to the writeback process is increasing the reading speed. This is done by the positive-feedback effect caused by connecting the transistor, M, this way. This positivefeedback effect will be illustrated in conjunction with the simulation results in Section 6. The Dout signal will be at logic “1” in this case as it must be but will be available earlier than that of the conventional method as discharging C1 is much faster than charging CBL. Note that the output data here is not taken at the bitline, rather it is taken at the output of the inverter, inv2. Note also that there is no need according to this scheme to use either a dummy cell or a sense amplifier, thus saving the silicon area. 4. Quantitative analysis In this section, the proposed reading scheme will be investigated quantitatively. Specifically, the impact of the size of the cell storage capacitor, Cs, on the reading operation will be addressed. To find the steady-state voltage on the bitline upon charge sharing, VBL, the principle of charge conservation will be used as explained in Section 2; that is the charge lost by one capacitor equals the charge gained by the other one. If the cell stores “0”, then the cell capacitor, Cs, will be initially discharged to 0 V. So, Cs ½VBL0 0 ¼ CBL ½Vthn VBL0 ) VBL0
CBL Vthn Vthn : ¼ ¼ ðCBL þ Cs Þ 1 þ Cs
ð5Þ ð6Þ
CBL
Since Cs is much smaller than CBL (typically 30 times smaller), then Cs/CBL 1/30. So, VBL0 ¼
Vthn ¼ 0:967Vthn : 1 1þ 30
ð7Þ
For the 0.13 mm CMOS technology, Vthn = 400 mV, so VBL0 ¼ 0:967ð400 mV Þ ¼ 387 mV: This means that the voltage on the bitline in case of stored “0” is only 13 mV lower than Vthn. This keeps Q in the cutoff mode but brings two problems. The first one is the subthreshold leakage current through Q. This current cannot be neglected in modern CMOS technologies, especially if the gate voltage is slightly smaller than Vthn which is the case, thus inducing a nonnegligible channel. This current puts a lower limit on the charging rate of C1. The second problem is the sensitivity to process variations. If, for some reason or another, the threshold
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voltage, Vthn, decreases by more than 13 mV due to variations in channel length, gate-oxide thickness, or dopant-atom concentration, the transistor, Q, will conduct irrespective of the stored data and the reading scheme will thus malfunction. One solution to this problem is to decrease CBL by educing the number of memory cells connected to each bitline. As evident from Eq. 6, if CBL is decreased, then VBL0 will decrease, thus enhancing the noise margin in case of stored “0”. Now, in case of stored “1”, the bitline voltage, VBL1, can be found from Cs ½VBL1 Vthn ¼ CBL ½VDD VBL1 : ) VBL1 ¼
C V Cs VDD þ CBL Vthn VDD þ CBL thn s ¼ : C ðCs þ CBL Þ BL 1þ
ð8Þ ð9Þ
Cs
Substituting VDD = 1.2 V, Vthn = 0.4 V, and CBL/Cs = 30 into Eq. 9 results in VBL1 ¼ 426 mV: This value exceeds Vthn = 400 mV by only 26 mV which is considered a weak excess gate voltage resulting in a relatively small current through Q. Fortunately, however, the parasitic capacitance to be discharged, C1 is much less than CBL. Also, increasing Cs can speedup the discharging process. This seems to be a tradeoff between the area and the speed. Finally, note that the sense margin of the stored “0” and “1” are not equal according to the proposed scheme. This is in contrast to the conventional readout scheme in which the bitline is initially precharged to VDD/2. The access times of the conventional and proposed readout schemes, tc and tp, are plotted in Fig. 4 versus the size of the storage capacitor, Cs. The derivation of the relationship between Cs and tc and tp will be presented in Appendix A.
ORIGINALARBEITEN
depends on the small differential voltage appearing between its two input terminals. The second comment is that the two access times, tc and tp, are shown to be equal at the critical value of Cs = 4.7 fF. The proposed scheme then does a benefit when Cs is larger than this value. The reason behind the fact that the access time of the proposed scheme is less than that of the conventional scheme for certain range of Cs is that there are two contradicting factors; the first one is that the parasitic capacitance to be discharged in the proposed scheme, C1, is much less than that in the conventional scheme, CBL. However, the effective gate voltage of the discharging transistor in the proposed scheme is very weak compared to that in the conventional scheme. When Cs is less than Cscritical, the second factor is the dominant one resulting in tc being less than tp. However, when Cs is larger than Cscritical, the first factor is the dominant one resulting in tp being less than tc. An important note is in order here concerning the relationship between the proper size of the cell storage capacitor, Cs, and the sense amplifier sensitivity, SAs. The sense amplifier sensitivity can be defined as the minimum voltage difference between the two input terminals of the sense amplifier such that it can amplify this difference and outputs the data properly. In the conventional readout scheme, the bitline voltage, VBL, is compared with a precharge level of VDD/2. Assuming that the cell stores “1”, then the sense margin in this case will be SM1 ¼ VBL1
Cs VDD VDD 2 ¼ ; 2 Cs þ CBL
ð10Þ
as derived in Eq. 9. In order to derive a compact form for the minimum value of Cs, SM1 will be put equal to the sense amplifier sensitivity, SAs. So, SAs ¼
Cs min VDD 2 Cs min þ CBL
CBL SAs : Cs min ¼ VDD SA 2
ð11Þ ð12Þ
s
So, it can be concluded that the sense amplifier sensitivity dictates a certain minimum limit on the size of Cs. If CBL = 250 fF, VDD = 1.2 V, and SAs = 20 mV, then Cs min ¼ 8:6 f F; which is larger than the critical value found in Fig. 4. So, we can safely say that the proposed scheme does not force the designer to use a cell capacitor larger than the minimum-sized one. 5. Impact of technology scaling Fig. 4. The access times of the conventional and proposed schemes, tc and tp, in ns versus the size of the cell storage capacitor, Cs, in fF Two comments on Fig. 4 are in order. The first one is that the access time of the proposed scheme, tp, is more sensitive to the size of the storage capacitor, Cs, than the access time of the conventional scheme, tc. This is an expected result since increasing Cs in the proposed scheme has a direct effect on increasing the gate voltage of the discharging transistor, Q. The discharging current of Q in turn is assumed to be proportional to the square of the effective gate voltage (VGS – Vthn). In the conventional scheme, however, increasing Cs has the direct effect also of increasing the voltage difference appearing on the bitline. However, its effect on the access time is less than that in the proposed scheme since the time delay of the sense amplifier slightly
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5.1 Velocity saturation and mobility degradation In this section, the impact of technology scaling on the proposed readout scheme is investigated. More importantly, due to the velocity saturation and mobility degradation effects, the discharging current of Q will be less sensitive to the increase of its gate voltage. Consequently, the access time of the proposed readout scheme, tp, is expected to be less sensitive to the size of the storage capacitor, Cs. 5.2 Reduction of the VDD/Vthn ratio Due to the need to reduce the dynamic power consumption and enhance the reliability of short-channel devices, the power-supply voltage, VDD, reduces at a rate that is faster than that of Vthn from one technology generation to the next as discussed in detail in Chapter 2. So, the ratio VDD/Vthn decreases. Since CBL is precharged
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to Vthn instead of VDD/2, the percentage of the precharging time interval relative to the total access time is expected to increase. However, it remains below the precharging time interval of the conventional scheme in which CBL is initially precharged to VDD/2 as soon as Vthn remains below VDD/2. The precharging time interval, however, of the conventional scheme remains the same as VDD and the precharge level decreases by the same ratio from one technology generation to the next. If the VDD/Vthn ratio reaches 2, then VDD/2 will be equal to Vthn and the precharging time delays of the conventional and proposed readout schemes will be the same. Also, the need arises in this case to adjust the threshold voltage of the precharging PMOS transistor in the conventional scheme. To investigate the impact of the reduction of the VDD/Vthn ratio on the ratio between the two sense margins in case of “0” and “1” readings, SM0 and SM1, respectively, refer to Eqs. 9 and 6 for VBL1 and VBL0. They will be repeated here for convenience. VBL1 ¼
Cs VDD þ CBL Vthn Cs þ CBL
ð13Þ
CBL Vthn : ðCBL þ Cs Þ
ð14Þ
VBL0 ¼
So, the sense margins in case of “1” and “0” readings will be SM1 ¼ DVBL1 ¼ VBL1 Vthn ¼
Cs ðVDD Vthn Þ Cs þ CBL
ð15Þ
and SM0 ¼ DVBL0 ¼ Vthn VBL0
Cs Vthn ¼ ; Cs þ CBL
ð16Þ
respectively. The ratio between SM1 and SM0 is thus SM1 Cs ðVDD Vthn Þ VDD ¼ ¼ 1: Cs Vthn SM0 Vthn
ð17Þ
So, with technology scaling, the ratio between SM1 and SM0 decreases until we arrive at the case VDD = 2Vthn at which the two sense margins are equal. In fact, this case corresponds to precharging the bitline to VDD/2 as in the conventional scheme. Refer to Fig. 5 for illustrating the impact of technology scaling on SM1 and SM0. 6. Simulation results In this section, the proposed readout scheme will be simulated and compared to the conventional readout scheme. Before presenting
Wordline activated
Wordline activated
Fig. 5. The effect of the reduction of the VDD/Vthn ratio on the sense margins of “1” and “0” readings, SM1 and SM0, in the proposed method. Note the equalization of the sense margins, SM1 and SM0, with technology scaling the simulation results, an important note concerning the interconnections is in order. The interconnection of the bitline or the wordline of the memory array can be modeled either by lumpedcapacitance model, distributed RC model, or transmission-line model (Ayers, 2005). The appropriate model depends on the interconnection length, l, the propagation delay of the driver source, tpdriver, and the resistance and capacitance per unit length, r and c, respectively. Specifically, the lumped-capacitance model applies if (Ayers, 2005) sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi tpdriver ð18Þ lG rc lnð2Þ=2 which holds for the 130 nm technology and the aluminum interconnect. Assuming that each cell connected to the bitline adds 2 fF to the bitline parasitic capacitance, then for 128 cells at each column, CBL is typically 256 fF. The threshold voltage of MP1 is Vthp = –0.2 V, Cs = 10 fF, and CBL = 256 fF. All the transistors are minimum-sized except for three transistors; the first one is the precharging transistor of CBL for both the conventional and proposed schemes which has an aspect ratio of 3 in order to shorten the precharging time intervals. The second one is the discharging transistor, Q, that discharges C1 as it is a critical-path transistor and has an aspect ratio of 2. If the size of this transistor is chosen below a certain minimum value, the capacitance, C1, will not discharge below the threshold voltage of the inverters, inv1 or inv2, thus resulting in erroneous output data and erroneous writeback process. Also, the aspect ratio of the writeback transistor of the proposed scheme is put equal to 3 because its size affects the read cycle time. Refer to Figs. 6 and 7 for the simulation results for stored 1 and 0 for the conventional readout scheme and to Figs. 8 and 9 for
Transient analysis
Fig. 6. The simulation results of the conventional readout scheme for stored “1” showing the bitline and complementary bitline voltages. The output data will be available after approximately 21 ns
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Transient analysis
Fig. 7. The simulation results of the conventional readout scheme for stored “0” showing the bitline and complementary bitline voltages
Transient analysis
Fig. 8. The simulation results of the proposed readout scheme for stored “1” showing the output data, Dout the voltage at the gate of the transistor, Q, and the voltage across the parasitic capacitance, C1
Transient analysis
Fig. 9. The simulation results of the proposed readout scheme for stored “0” showing the output data, the voltage at the gate of the transistor, Q, and the voltage across the parasitic capacitance, C1 the proposed readout scheme. The read access time according to the proposed scheme is approximately 17 ns for stored “1” which represents the worst case (longer access time) compared to 21 ns according to the conventional scheme, thus saving approximately 20% of the
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read access time. The read cycle times of both the conventional and proposed readout schemes are approximately the same (21 ns). The average power of the conventional scheme in case of stored “1” or “0” is 18.5 mW. The corresponding values for the proposed scheme
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Transient analysis
Fig. 10. The simulation results of the proposed readout scheme for stored “1” showing the voltage across the cell storage capacitor, Cs, during the precharging, charge sharing, and writeback processes
Transient analysis
Fig. 11. The simulation results of the proposed readout scheme for stored “0” showing the voltage across the cell storage capacitor, Cs, during the precharging, charge sharing, and writeback processes
Output data
Monte carlo analysis
Time (s) Fig. 12. The Monte Carlo simulation results for the case of stored “1” with CBL = 256 fF are 9.8 mW and 2.25 mW. The significant reduction of the power consumption can be attributed to the reduction of the voltage swing of the bitline parasitic capacitance and taking the output data at a much smaller capacitance. The power-delay products (PDPs) for the
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conventional and proposed readout schemes assuming the worst case (stored “1”) are 388.5 fJ and 166.6 fJ, respectively. Note that the discharging of C1 begins at the same time instant at which VGQ exceeds Vthn of the NMOS transistor, Q, as shown in
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Output data
Monte carlo analysis
Time (s) Fig. 13. The Monte Carlo simulation results for the case of stored “1” with CBL = 128 fF
Output data
Monte carlo analysis
Time (s) Fig. 14. The Monte Carlo simulation results for the case of stored “0” with CBL = 256 fF
Output data
Monte carlo analysis
Time (s) Fig. 15. The Monte Carlo simulation results for the case of stored “0” with CBL = 128 fF
Fig. 8. Since the increase in VGQ = VBL in case of stored “1” is small, the discharging is slow as expected. The process continues until VC1 reduces to the threshold voltage of the inverter, inv1. At this time, the inverter output rises, i.e. the PMOS transistor of the inverter, inv1, charges CBL, thus increasing the current of Q and speeding-up
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the discharging process of C1 as shown in Fig. 8. The operation continues in a positive-feedback process until C1 completely discharges to 0 V and the read data is written back. This positivefeedback effect was alluded to in Section 3. Finally, refer to Figs. 10 and 11 for the voltage across the cell storage capacitor, Cs, during
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the precharging, charge sharing, and writeback processes for stored “1” and stored “0”, respectively. Finally, concerning the problem of the sensitivity to thresholdvoltage variations, a Monte Carlo simulation is performed assuming that the distribution of the threshold voltage of the NMOS transistor, Q, is chosen to be Gaussian and the percentage change is 13%. The Monte Carlo simulation runs are 100 for stored “1” with 46 of them resulting in erroneous output data. When the analysis is repeated with CBL equal to half its value, 128 fF, the erroneous data occur in only 3 runs which can be corrected by error-correction codes (ECC) (Tocci, Widmer, 1998). When the simulation is repeated with stored “0”, the erroneous data occur in only 2 runs for CBL ¼ 256 fF and when CBL ¼ 128 fF, there are no wrong read data. These simulation results are shown in Figs. 12 to 15. Obviously, the case of the largest threshold voltage Vthnominal (1 þ 0.13%) corresponds to the smallest discharging current for C1 and thus the largest access time while the smallest threshold voltage Vthnominal (1–0.13%) corresponds to the largest discharging current for C1 and accordingly the smallest access time. 7. Conclusions There is no doubt that dynamic RAMs play a significant role in all computing and control devices. The conventional reading process of one-transistor one-capacitor dynamic random-access memories requires the use of a sense amplifier that compares between the bitline voltage and the dummy bitline voltage, then amplifying the voltage difference between them. However, this takes a
Appendix A We will now seek to derive compact forms for the access time in terms of the size of the cell storage capacitor, Cs, according to the conventional readout scheme, tc, using a sense amplifier and according to the proposed readout scheme, tp, where c stands for conventional and p stands for proposed. 1. The access time of the conventional scheme, tc Since in the logic “0” reading the capacitance, C1, remains charged, the access time in this case will certainly be smaller than that in case of logic “1” reading. So, the logic “1” reading represents the worst case, i.e. the critical path and thus the access time will be estimated assuming logic “1” storage. Now, in case of “1” storage, Cs is initially charged to VDD. According to the definition of the access time, tc, in Section 3, tc includes the precharging time delay required to charge CBL to VDD/2, tc1, the time interval required to share the charges between Cs and CBL upon activating the wordline, tc2, and the time required to amplify the small differential voltage between the two bitlines, BL and BL, upon activating the sense amplifier, tc3. Refer to Fig. 16 for illustration.
relatively long time. In this paper, a novel readout scheme for the 1T-1C DRAMs was presented and compared to the conventional one. The read access time according to the proposed scheme is 20% of the conventional scheme while the read cycle time of the proposed scheme is approximately equal to that of the conventional one. The power-delay products (PDPs) for the conventional and proposed readout schemes assuming the worst case (stored “1”), i.e the longest access time, are 388.5 fJ and 166.6 fJ, respectively. References Wood, J., Wood, R. G. (1965): The Use of Insulated-Gate Field-Effect Transistors in Digital Storage Systems. ISSCC Digest of Technical Papers, pp. 82–83, February 1965. Digest of Technical Papers of the IEEE International Solid-State Circuits Conference (ISSCC), February of each year. Regitz, W. M., Karp, J. A. (1970): A Three-Transistor Cell, 1024-bit, 500 ns MOS RAM. ISSCC Digest of Technical Papers, pp. 36–39, February 1970. Digest of the IEEE International Electron Devices Meeting (IEDM), December of each year. Dennard, R. H. (1968): Patent 3387286 assigned to the IBM Corporation. Sedra, A. S., Smith, K. C. (1998): Microelectronic Circuits. 4th ed. New York: Oxford. Jaeger, R. C., Blalock, T. N. (2004): Microelectronic Circuit Design. 2nd ed. New York: McGraw-Hill. Tocci, R. J., Widmer, N. S. (1998): Digital Systems: Principles and Applications. 7th ed. Upper Saddle River: Prentice Hall. Ayers, J. E. (2005): Digital Integrated Circuits: Analysis and Design. Boca Raton: CRC Press. Uyemura, J. P. (2006): Chip Design for Submicron VLSI: CMOS Layout and Simulation. New York: Thomson.
The precharging time interval begins with the activation of the PRE signal to 0 V. According to the conventional readout scheme, CBL is precharged to VDD/2 through the PMOS transistor, Mp. Refer to Fig. 17 for the corresponding circuit schematic.
VDD 2
M
P
+ CBL VBL
-
VBL Fig. 17. Circuit schematic representing the precharging of CBL to VDD/2
V(1) = VDD VBL1
VDD 2
V BL0
V(0) = 0 V tc1
tc2
Precharging Wordline activated time delay
tc3
The precharging time delay, tc1, can be estimated from (Sedra, Smith, 1998)
t
Sense amplifier activated
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CBL DVBL iavg
ð19Þ
where iavg is the average charging current of CBL and is equal to
Fig. 16. Waveforms of VBL before and after activating the sense amplifier of the conventional scheme. Complementary signal waveforms develop on the BL line. This plot is not to scale
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tc1 ¼
© Springer-Verlag
iavg ¼
iðVBL ¼0Þ þ iðVBL ¼VDD =2Þ 2
ð20Þ
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where i(VBL ¼ 0) and i(VBL ¼ VDD/2) are the transistor currents at the beginning and at the end of the precharging time interval and DVBL is the range within which the bitline voltage changes. At the beginning of the precharging process, MP, operates in the saturation region as its VSD = VDD/2HVSG|Vthp| ¼ VDD/2|Vthp|, so 2
1 W VSG Vthp 1 þ lp VSD iðVBL ¼0Þ ¼ kp0 2 L MP 2 1 W VDD VDD Vthp ; ð21Þ 1 þ lp ¼ kp0 2 L MP 2 2 where lp is the channel-length modulation effect parameter of the PMOS transistors. At the end of the precharging process, MP, operates in the triode region with VSD = 0 V, so iðVBL ¼VDD =2Þ ¼ 0:
Substituting
dVCS dt
L MP
2
kn0
CBL þ Cs s¼0 Cs CBL þ Cs ¼0 ) s RCBL s þ Cs
VDD VDD ; a þ 0 W
2 kn L Qc ðVDD Vthn ÞVDD 12 VDD L Qc ðVDD Vthn Þ
W
ð35Þ
The general solution to Eq. 32 is thus
VBLðtÞ ¼ Aes1 t þ Bes2 t ¼ A þ Be
CBL þCs RCBL Cs
t
ð36Þ
ð25Þ
where A and B are two arbitrary constants to be determined from the following initial conditions: VBL(0+) and dVdtBL ð0þ Þ where 0+ refers to the instant of time immediately after activating the wordline. Since the bitline is initially precharged to VDD/2 before activating the wordline, WL, then VBL(0+) = VDD/2. To find dVdtBL ð0þ Þ, since VCSð0þ Þ VBLð0þ Þ VDD VDD =2 VDD ¼ ¼ R R 2R
ð37Þ
dVBL þ VDD dVBL þ VDD )) ð0 Þ ¼ ð0 Þ ¼ : dt 2R dt 2RCBL
ð38Þ
ið0þ Þ ¼ ) ið0þ Þ ¼ CBL
Substituting these two initial conditions into Eq. 36 results in
+
+ i CBL
Cs
VBLð0Þ ¼ A þ B ¼
VBL
)
ð26Þ
dVBL dVCS ¼ Cs dt dt
dVCS CBL dVBL ¼ dt CCS dt
) VCS þ RCBL
dVBL þ VBL ¼ 0: dt
dVBL ðCBL þ Cs Þ VDD ð0Þ ¼ B ¼ RCBL Cs dt 2RCBL
ð41Þ
Cs VDD : 2ðCBL þ Cs Þ
ð42Þ
A¼
VDD ð2Cs þ CBL Þ : 2ðCs þ CBL Þ
ð43Þ
Substituting A and B into Eq. 36 results in ð27Þ
) VBLðt Þ ð29Þ
ðC þCs Þ VDD ð2Cs þ CBL Þ Cs VDD BL t e RCBL Cs 2ðCs þ CBL Þ 2ðCs þ CBL Þ ðC þCs Þ VDD BL t ¼ ð2Cs þ CBL Þ Cs e RCBL Cs : 2ðCs þ CBL Þ
VBLðt Þ ¼
ð28Þ
To put Eq. 29 in terms of VBL only, the whole equation must be differentiated with respect to time. So,
M€arz 2012 | 129. Jahrgang
ð40Þ
From Eqs. 39 and 40, we obtain
where VCS is the voltage across the cell storage capacitor, Cs, VBL is the voltage across the bitline parasitic capacitance, CBL, and i is the transient current through the loop. Now, since i ¼ CBL
ð39Þ
dVBL ðCBL þ Cs Þ ðCRCBL þCCss Þt ¼ B e BL RCBL Cs dt
B¼
By Kirchhoof’s voltage law, we obtain VCS þ Ri þ VBL ¼ 0
VDD 2
and
–
Fig. 18. The circuit schematic of the memory cell upon activating the word-line, WL
)
ð34Þ
2
R
–
ð33Þ
CBL þ Cs s1 ¼ 0; s2 ¼ : RCBL Cs
where a is a parameter accounting for the short-channel effects. So, the cell can be represented as shown in Fig. 18.
VCs
ð32Þ
RCBL s2 þ
ð23Þ
Now, upon activating the wordline, WL, the cell capacitor, Cs, loses some of its charge to the bitline parasitic capacitance, CBL, through the access transistor, Qc. Let the access transistor be represented by a resistor, R, for simplicity where (Uyemura, 2006). R¼
ð31Þ
So,
Substituting iavg from Eq. 23 into Eq. 19 results in the following formula for the precharging time delay, tc1, 4CBL V2DD ð24Þ tc1 ¼
2
: VDD Vthp 1 þ lp VDD k0 W p
from Eq. 28 into Eq. 30 results in
The characteristic equation corresponding to the previous secondorder ordinary differential equation is
The average charging current is thus iavg
ð30Þ
CBL dVBL d 2 VBL dVBL þ RCBL ¼0 þ Cs dt dt 2 dt d 2 VBL dVBL CBL þ Cs þ ) RCBL ¼ 0: dt 2 dt Cs
ð22Þ
2 1 W VDD VDD Vthp : ¼ kp0 1 þ lp 4 L MP 2 2
dVCS d 2 VBL dVBL þ RCBL ¼ 0: þ dt dt 2 dt
ð44Þ ð45Þ
The second component of the access time, tc2, can be defined as the time interval from the instant of time at which the wordline is activated to the instant of time at which VBL(t) reaches 99.99% of
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the final bitline voltage, VBL1. The final value of VBL(t) according to Eq. 45 is (when t ¼ ¥)
Cs VDD þ CBL V2DD : ð46Þ VBL1 ¼ ðCBL þ Cs Þ If the conventional definition of the rise time is adopted here (with the percentage of 90% considered), tc1 will be negative which does not have a physical meaning. This is due to the fact that the range within which VBL changes is very small to the extent that the initial value of VBL is less than 90% of its final value. Substituting these values into Eq. 45 results in
ðC þCs Þ Cs VDD þ CBL V2DD VDD BL t ¼ 0:9999 ð2Cs þ CBL Þ Cs e RCBL Cs c2 : ðCBL þ Cs Þ 2ðCBL þ Cs Þ ð47Þ After simple mathematical manipulations, we get tc2 ¼
RCBL Cs 104 Cs ln ðCBL þ Cs Þ ð2Cs þ CBL Þ
ð48Þ
where R¼
kn0
W L
VDD VDD : ð49Þ a þ 0 W
1 2 ð Þ ð V V k V V DD DD thn thn ÞVDD 2 VDD n L Qc Qc
For the 130 nm CMOS technology, we have VDD ¼1.2 V, kp0 ¼511 A/V2, kp0 ¼120 mA/V2, Vthn ¼0.4 V, a¼1.3 (in short-channel devices), and CBL ¼250 fF, then R ¼ 12923:38W:
3:23Cs 104 Cs ln ; ¼ ð250 þ Cs Þ ð250 þ 2Cs Þ
ð50Þ
where Cs is in fF and tc2 is in ns. In order to derive a compact form for the relationship between the third component of the access time, tc3, and the size of the cell storage capacitor, Cs, in the conventional readout scheme, the relationship between Cs and DVBL must be first derived. Then, the relationship between DVBL and tc3 will be found. In case of “1” storage, the voltage developed on the bitline, VBL1, is VBL1 ¼ ) DVBL1
W VDD Vthn ¼ 1:022 104 A=V 2 ; L 2 W V DD Vthp ¼ 2:56 105 A=V 2 ¼ kp0 L 2
gmn ¼ kn0
ð57Þ
gmp
ð58Þ
for minimum-sized transistors. So, 250 þ Cs : tc3 ¼ 1:956 ln Cs
ð59Þ
The access time as defined before is the sum of the three components, tc1, tc2, tc3, so 4CBL V2DD tc ¼
2
kp0 WL MP V2DD Vthp 1 þ lp V2DD 3:23Cs 104 Cs 250 þ Cs ln þ 1:956 ln þ : ð60Þ ð250 þ Cs Þ ð250 þ 2Cs Þ Cs Substituting kp0 ¼128 mA/V2, WL MP ¼ 3, VDD ¼ 1.2 V, Vthp ¼ –0.4 V, CBL ¼ 250 fF, and lp ¼ 0.02 into Eq. 60 results in tc ¼ 38:59 þ
3:23Cs 104 Cs 250 þ Cs ln þ 1:956 ln : ð61Þ ð250 þ Cs Þ ð250 þ 2Cs Þ Cs
where Cs is in fF and tc is in ns.
So, tc2
The two transconductances will be evaluated at a gate-to-source voltage, VGS, equal to VDD/2 which is the initial voltage to which the bitlines is precharged (Sedra, Smith, 1998). Adopting the parameters of the 130 nm CMOS technology results in
Cs VDD þ CBL V2DD Cs þ CBL
ð51Þ
Cs V2DD VDD Cs VDD þ CBL V2DD VDD ¼ ¼ ¼ VBL1 : ð52Þ 2 Cs þ CBL 2 Cs þ CBL
Now, tc3 is related to the positive difference signal, DVBL1, through the following approximate relationship (Sedra, Smith, 1998) Gm t VDD C þ DVBL1 e BL ; VBL < VDD ; ð53Þ VBL1ðt Þ ¼ 2
2. The access time of the proposed scheme, tp The access time of the proposed scheme, tp, includes four components; the first one is the time required to precharge CBL to Vthn, tp1, the second one is the time required to share the charges between Cs and CBL, tp2, the third component is that required to discharge C1 to 0 V if the cell stores “1”, tp3, and the fourth and last component is the low-to-high propagation delay of the inverter, inv2, tp4. According to the proposed readout scheme, CBL is precharged to Vthn through the PMOS transistor, Mp. Refer to Fig. 19 for the corresponding circuit schematic. The precharging time delay, tp1, can be estimated from (Sedra, Smith, 1998) tp1 ¼
CBL DVBL iavg
ð62Þ
Vthn
where Gm ¼ gmn þ gmp ;
ð54Þ
where gmn and gmp are the transconductances of the NMOS and PMOS transistors, respectively of the inverters employed in the sense amplifier. tc3 is the time required for VBL1(t) to reach VDD. So, Gm tc3 VDD C þ DVBL1 e BL : ð55Þ VDD ¼ 2 Substituting for DVBL1 from Eq. 52 into Eq. 55 results in CBL C þ Cs
ln BL : tc3 ¼ Cs gmn þ gmp
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P1
+ CBL V BL -
ð56Þ Fig. 19. Circuit schematic representing the precharging of CBL to Vthn
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ORIGINALARBEITEN
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where iavg is the average charging current of CBL and is equal to iðVBL ¼0Þ þ iðVBL ¼Vthn =2Þ 2
iavg ¼
ð63Þ
where i(VBL ¼ 0) and i(VBL ¼ Vthn) are the transistor currents at the beginning and at the end of the precharging time interval, tp1, and DVBL is the range within which the bitline voltage changes. At the beginning of the precharging process, MP operates in the saturation region as its VSD ¼ Vthn and its VSG – |Vthp| ¼ Vthn – |Vthp|. Putting |Vthp| ¼ Vthn/2 for the precharging transistor, MP1, then VSD > VSG – |Vthp|, so iðVBL ¼0Þ
1 W Vthn 2 ¼ kp0 Vthn 1 þ lp Vthn 2 L MP 2
1 W Vthn 2 1 þ lp Vthn : ¼ kp0 2 L MP 2
VBLðt Þ ¼
ðCBL Vthn þ Cs VDD Þ Cs ðVDD Vthn Þ ðCRCBL þCCss Þt e BL : ðCBL þ Cs Þ ðCBL þ Cs Þ
ð74Þ
The time delay, tp2, will be defined here as in the previous analysis to be the time interval from the instant of time at which the wordline is activated to the instant of time at which VBL is equal to 0.9999 of the final value, VBL1. VBL1 was found in Eq. 9 to be VBL1 ¼
Cs VDD þ CBL Vthn : ðCBL þ Cs Þ
ð75Þ
Since t ¼ tp2 when VBL(t) ¼ 0.9999 VBL1, we obtain ð64Þ
At the end of the precharging process, Mp operates in the triode region with VSD ¼ 0 V, so iðVBL ¼Vthn Þ ¼ 0:
So,
0:9999
Cs VDD þCBL Vthn ðCBL Vthn þCs VDD Þ Cs ðVDD Vthn Þ ðCRCBL þCCss Þtp2 ¼ e BL : ðCBL þCs Þ ðCBL þCs Þ ðCBL þCs Þ
After simple mathematical manipulations, we obtain the following compact from for tp2
ð65Þ
tp2 ¼
RCBL Cs 104 Cs ðVDD Vthn Þ ln : ðCBL þ Cs Þ ðCs VDD þ CBL Vthn Þ
ð76Þ
The average charging current is thus iavg
1 W Vthn 2 ¼ kp0 1 þ lp Vthn : 4 L MP 2
ð66Þ
tp2 ¼
Substituting iavg from Eq. 66 into Eq. 62 results in the following formula for the precharging time delay, tp1, tp1 ¼
4CBL Vthn W Vthn 2 0 kp L MP 2 1þ
) tp1 ¼
kp0
W
ð67Þ
16CBL
: 1 þ lp Vthn
ð68Þ
lp Vthn
L MP Vthn
Substituting for CBL ¼ 250 fF, kp0 ¼128 mA/V2, (W/L)MP ¼ 3, and lp ¼ 0.02 results in tp1 ¼ 25:835 ns: The second component of the access time of the proposed method, tp2, is that required to share the charges between Cs and CBL. To estimate this time, we will proceed as before through the transienttime analysis with the same equivalent circuit of Fig. 18 until we arrive at the following equation for VBL(t)
VBLðt Þ ¼ C þ De
ðCBL þCs Þ RC Cs t BL
;
To determine ið0þ Þ ¼
dVBL dt
The previous procedure will now be applied assuming stored “1” as this case represents the worst case as discussed previously. The relationship between Cs and VGQ was determined in Eq. 9, so VGQ ¼ VBL1 ¼
ð72Þ
M€arz 2012 | 129. Jahrgang
ð73Þ
ð79Þ
where ln is the channel-length modulation effect parameter of the NMOS transistors. The time delay, tp3, can be found from C1 DVC1 ; Iavg
ð80Þ
where Iavg is the average discharging current of C1 and DVC1 is the range within which the voltage, VC1, changes. So, IðVC1 ¼VDD Þ þ IðVC1 ¼VDD =2Þ ð81Þ 2 " # 2 1 12 kn0 WL Q ½VBL1 Vthn ð1 þ ln VDD Þ W
Iavg ¼ 1 0 2 þ 2 kn L Q ½VBL1 Vthn 2 1 þ ln V2DD 1 W VDD ¼ kn0 ½VBL1 Vthn 2 ð1 þ ln VDD Þ þ 1 þ ln 4 L Q 2 Iavg ¼
Substituting these two conditions into Eq. 69 results in two equations in terms of C and D that can be solved to yield CBL Vthn þ Cs VDD Cs ðVDD Vthn Þ ;D ¼ : ðCBL þ Cs Þ ðCBL þ Cs Þ
ð78Þ
1 W ½VGQ Vthn 2 ð1 þ ln VC1 Þ; Idis ¼ kn0 2 L Q
tp3 ¼
dVBL þ VDD Vthn ð0 Þ ¼ : dt RCBL
)
Cs VDD þ CBL Vthn : ðCBL þ Cs Þ
The discharging transistor, Q, will operate in the saturation region during the whole time interval during which C1 discharges to VDD/2 as its VDS will always be larger than VGSVthn. So,
ð0þ Þ, the initial current i(0+) is ð71Þ
ð77Þ
1. Determine the relationship between Cs and the gate voltage of the discharging transistor, VGQ, to which the bitline is connected; 2. Determine the relationship between VGQ and the discharging current, Idis; and finally 3. Determine the relationship between the discharging current, Idis, and the time required to discharge C1 to VDD/2, tp3.
ð70Þ
VCSð0þ Þ VBLð0þ Þ VDD Vthn dVBL þ ¼ ¼ CBL ð0 Þ R R dt
C¼
3:23Cs 8Cs ln : ð250 þ Cs Þ ð1:2Cs þ 100Þ
A compact form for the third component of the access time, tp3, is to be determined now. Toward that end, we will proceed as follows:
ð69Þ
where C and D are two arbitrary constants to be determined from the initial conditions as before. Taking into account that CBL is precharged to Vthn according to the proposed scheme, so VBLð0þ Þ ¼ Vthn :
Substituting the values of the 130 nm technology as before into Eq. 76 results in
) Iavg
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1 W 3 ) Iavg ¼ kn0 ½VBL1 Vthn 2 2 þ ln VDD : 4 L Q 2
ð82Þ
Substituting Iavg into Eq. 80 results in the following expression for tp3
tp3 ¼
kn0
W L
2C1 VDD
: ½V Vthn 2 2 þ 32 ln VDD Q BL1
tp4 ¼ ð83Þ
) tp3
kn0
2C1 VDD i2
W hCs VDD þCBL Vthn Vthn 2 þ 32 ln VDD ðCBL þCs Þ L Q
2C1 VDD ðCBL þ Cs Þ2 ¼ W
: kn0 L Q ½Cs ðVDD Vthn Þ2 2 þ 32 ln VDD
ð84Þ
2
tp3
1:7C W L ; L p VDD
ð86Þ
tp4 ¼ 0:015625 ns:
Substituting for the values of kp0 , VDD, Vthn, CBL, ln ¼ 0.02, and C1 ¼ 2 fF results in 0:0072ð250 þ Cs Þ ¼ ; Cs2
kp0
where CL is the load capacitance at the output of the inverter, inv2, and (W/L)p is the aspect ratio of the PMOS transistor of this inverter. Putting CL ¼ 2 fF, VDD ¼ 1.2 V, kp0 ¼128 mA/V2, and (W/L)p ¼ 1 into Eq. 86 results in
Substituting for VBL1 from Eq. 9 into Eq. 83 results in tp3 ¼
Finally, the fourth and final component of the access time of the proposed method, tp4, is the low-to-high propagation delay of the inverter, inv2; that is (Sedra, Smith, 1998)
ð85Þ
The total access time of the proposed readout scheme, tp, is thus tp ¼ 25:835 þ þ
3:23Cs 8Cs ln ð250 þ Cs Þ ð1:2Cs þ 100Þ
0:0072ð250 þ Cs Þ2 þ 0:015625: Cs2
ð87Þ
where tp3 is in ns and Cs is in fF.
Authors Sherif M. Sharroush was born in 1980 in Port Said, Egypt. He is a lecturer in the Faculty of Industrial Education in Suez, Suez-Canal University. He also worked with the Faculty of Petroleum and Mining Engineering in Suez, Suez-Canal University, the Faculty of Engineering in Ismailia, Suez-Canal University, and the Higher Institute of Engineering and Technology in New Damietta, Egypt. He received the B.Sc., M.Sc., and Ph.D. from the Faculty of Engineering in Port Said, Port Said University, in 2002, 2007, and 2011, respectively. His research interests include ferroelectric memories, dynamic random-access memories, analog and digital integrated circuits, photonics, and optical-fiber communications.
Ahmed A. Dessouki received the B.Sc. degree from Alexandria University, Egypt, in 1980, the M.Sc. degree from Suez Canal University, Egypt, in 1986, and the Ph.D. degree from Seoul National University, South Korea, in 1992, all in electronics and communications engineering. Since 1982 he has been employed by the Electrical Engineering Department at the Faculty of Engineering, Port Said, Egypt, as Demonstrator, then Assistance Lecture, then Assistance Professor. In 1988 he joined the Solid State Electronics Laboratory – Department of Electronics and Communications Engineering – Faculty of Engineering – Seoul National University as a Ph.D. candidate. His current research interests are in the general area of VLSI circuits, and include MOS and Quantum devices simulation, modeling and IC design.
Yasser S. Abdalla born in Egypt. He received B.Sc. and M.Sc. degrees from the Faculty of Engineering, Cairo University in 1994, and 1999, respectively. He joined the Department of Electrical and Computer Engineering at the University of Waterloo in Canada as a Ph.D. student in 2002 and graduated in 2006. Currently, he is a faculty member at the Suez Canal University in Cairo, Egypt. His major research interest is VLSI.
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ORIGINALARBEITEN
El-Sayed A. El-Badawy is currently Professor of Communications and Electronics and Head of EE Department, Pharos University in Alexandria (PUA), Smouha, Alexandria, Egypt, and Distinguished Professor Emeritus of Communications and Electronics, Electrical Engineering Department, Faculty of Engineering, Alexandria University, Alexandria, Egypt. He got his B.Sc. in electrical engineering with distinction, 1964, at Alexandria Univ., Egypt, and both his D.E.A. D’Electronique, 1971, and his Ph.D. (Docteur Inge´nieur) with First Degree of Honor and Written Congratulations of Jury, 1974, at Universite´ Paris VI, Paris, France. Since his graduation in 1964 from Alexandria University, he joined the Elect. Eng. Dept, Fac. of Eng., Alexandria University, Alexandria, Egypt, as Teaching Assistant; promoted Assistant Professor in 1974, Associate Professor in 1979, Professor of Communications and Electronics in 1984, and Distinguished Professor in 1994. Prof. El-Badawy was seconded as Professor of Communications and Electronics and also worked as Visiting Professor at different universities, institutions, and advanced technical schools. He has published about 215 research papers in the fields of lasers (construction, propagation, modulation, and applications), electronics and optoelectronics, communications and optical fiber communications, and microwave and MEMS devices and circuits. Furthermore, he is the author or co-author of many books and monographs in many areas of electrical engineering and advanced engineering mathematics. Prof. El-Badawy is Senior Member of IEEE and Member of The Optical Society of America.
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