IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 60, NO. 8, AUGUST 2013
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Efficient Arithmetic-Residue-Based SEU-Tolerant FIR Filter Design Zhen Gao, Pedro Reviriego, Wen Pan, Zhan Xu, Ming Zhao, Jing Wang, and Juan Antonio Maestro
Abstract—Finite impulse response (FIR) filters are commonly used in many signal processing systems. In some cases, such as space systems, FIR filters are exposed to radiation sources that cause errors. A number of techniques can be used to protect against those errors. One of them is the use of an arithmetic residue replica of the FIR filter. This replica has a lower cost than the original filter and therefore reduces the overhead compared with replicating the filter. However, some errors may not be detected by the arithmetic residue replica. In this brief, schemes that avoid undetected errors are presented. The proposed techniques are implemented and evaluated showing that they can detect all single errors affecting register bits. The results also show that their implementation requires only a small overhead in circuit complexity for the existing residue-based fault-tolerant FIR filters. Index Terms—Arithmetic residue, finite impulse response (FIR) filters, single-event upset (SEU).
I. I NTRODUCTION
F
INITE IMPULSE response (FIR) filters are widely used in communications and signal processing applications. One example is the space application which requires intensive onboard processing [1], [2]. When the FIR filters operate in extreme environments like space, they are exposed to different radiation sources that cause errors in the circuits [3]. One type of such errors is single-event upsets (SEUs) that change the value of a flip-flop or memory cell [4]. To mitigate the effects of SEUs, a number of techniques can be used [5]. Those range from modifying the manufacturing process of the integrated circuits to prevent SEUs from occurring to adding redundancy at the logic level so that SEUs do not affect the circuit behavior.
Manuscript received January 30, 2013; accepted April 17, 2013. Date of publication June 19, 2013; date of current version August 10, 2013. This work was supported in part by China’s 863 plan program “Research on the key technology for the base band signal processing for onboard payload,” by Sino–Japan Joint Fund “Key Technique Research for GSS Integrated Mobile Satellite Communications,” by Tsinghua University Initiative Scientific Research Program 2010THZ03—“Key technologies of sky–Earth integration wireless communication network,” by the National Basic Research Program of China under Grant 2012CB316000, and by the Spanish Ministry of Science and Education under Grant AYA2009-13300-C03. This brief was recommended by Associate Editor O. Gustafsson. Z. Gao, W. Pan, M. Zhao, and J. Wang are with the Tsinghua National Laboratory for Information Science and Technology, Tsinghua University, Beijing 100084, China (e-mail:
[email protected];
[email protected]. cn;
[email protected];
[email protected]). P. Reviriego and J. A. Maestro are with the Universidad Antonio de Nebrija, 28040 Madrid, Spain (e-mail:
[email protected];
[email protected]). Z. Xu is with the School of Information and Communication Engineering, Beijing Information Science and Technology University, Beijing 100085, China. Color versions of one or more of the figures in this brief are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSII.2013.2261183
Among the later group, triple modular redundancy (TMR) that triplicates the design and adds voting logic to correct errors is commonly used. However, TMR more than triples the area and power of the circuit, something that may not be acceptable in some space applications where weight and power are limited. For circuits that have algorithmic properties, another option is to exploit those properties to obtain effective protection at a lower cost. This is the case of signal processing systems for which many specific protection techniques have been proposed over the years [6]. For example, the protection of fast Fourier transforms and convolutions has been considered in [7] and [8]. In the case of FIR filters, the use of reduced precision redundancy was proposed in [9] to reduce the cost of TMR. The protection at a lower level by considering subwords has also been recently studied [10]. Other schemes use two different structures of the FIR filter to detect and correct errors with a cost that is lower than TMR [11]. In [12], the relationship between the input sequence and the contents of the registers in FIR filters was used to protect the filter. The use of redundant residue number systems (RNSs) is another option that has been explored for FIR filter protection [13]. Although RNSs can be effective, their use requires major modifications to existing designs as the input signal has to be decomposed using several moduli, and the output needs to be reconstructed using the Chinese remainder theorem. A similar but much simpler approach is to use arithmetic residues such that a replica computed modulo m is added [14], [15]. For an FIR filter, this replica has a much lower cost but will not detect all errors [16]. The probability of undetected errors can be reduced by storing several output samples [17], but this scheme cannot deal with soft errors that produce a single error output. Herein, we propose techniques to avoid undetected errors by both soft SEUs and hard SEUs in arithmetic residue errortolerant FIR filters. The techniques introduce small modifications into the input signal to ensure that errors are detected. To minimize the impact, the modifications are designed in such a way that they are attenuated by the FIR filter response. The overhead of the proposed scheme is compared to that of TMR and previous schemes for an field programmable gate array (FPGA) implementation. The results show that only a small increase in circuit resources is needed. The effectiveness of the scheme was also tested through fault injection experiments. The following section provides background information on existing arithmetic-residue-based error-tolerant FIR filter schemes and discusses the issue of undetected errors. Section III presents and analyzes theoretically the proposed techniques. Section IV presents an implementation of the proposed techniques for an FPGA and compares their cost in terms
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Fig. 1. FIR implementation using the transpose of the direct form.
Fig. 2. Architecture of the arithmetic-residue-based fault-tolerant FIR filter.
of circuit resources with TMR and existing schemes. Finally, the conclusions of this brief are summarized in Section V. II. A RITHMETIC -R ESIDUE -BASED E RROR -T OLERANT FIR F ILTERS A FIR filter implements the following equation: y[n] =
L−1
x[n − l] · h[l]
(1)
l=0
where x[n] is the input signal, y[n] is the output, and h[l] is the impulse response of the filter. There are several structures for implementing FIR filters. In Fig. 1, one of them known as the transpose of the direct form is illustrated [18]. An arithmetic residue version of the FIR filter is obtained by using the input modulo m and performing operations of all modulo m. The output of this filter yAR [n] is equal to the output of the original filter modulo m as expressed in the following equation: L−1 (x[n − l])m · (h[l])m = (y[n])m . (2) yAR [n] = l=0
m
Using this relationship, an error-tolerant FIR filter can be constructed using an arithmetic residue replica. This is illustrated in Fig. 2, where y1 and y2 are the outputs from the main filter blocks, r1 and r2 are the modulo m of those outputs, and r is the output from the modulo m filter branch. The correction logic works as follows. 1) If y1 = y2 , y1 is chosen as the output y = y1 . 2) If y1 = y2 , r is compared to r1 and r2 . a) If r1 = r and r2 = r, then y1 is output as the correct result and the second FIR branch has suffered the error. b) If r1 = r and r2 = r, then y2 is output as the correct result and the first FIR branch has suffered the error. c) Finally, if r1 = r and r2 = r, this situation indicates that an error has occurred but the checking branch cannot identify the faulty branch. This procedure corrects errors as long as they affect a single branch and are such that the residue of the affected branch is different from r.
The cost of this fault-tolerant FIR filter is lower than that of TMR as the arithmetic residue replica is much simpler than the other branches. This cost reduction comes at the expense of some uncorrected errors. Those occur when the error e at the output of the affected branch is such that (e)m = 0. For example, suppose that the first FIR branch output is correct and takes a value y1 = 15 and an error in the second FIR branch causes the output to be y2 = 22. If the modulus is m = 7, we will get r1 = r2 = r = 1, so that the faulty branch cannot be identified. For single bit errors, the probability of this occurring can be reduced by choosing m = 2k − 1. In the case of adders and multipliers, it has been observed that, when m = 2k − 1, all single errors can be detected for some implementations [19], [20]. For an FIR filter, the problem is more complex as there are also registers that store the intermediate results and the coefficients, as shown in Fig. 1. For the case that a direct FIR filter structure is used in the fault-tolerant system in Fig. 2, single bit errors on both data registers and coefficients can lead to undetected errors [16], [17]. To reduce the probability of undetected errors, one option is to store multiple output samples and perform a check on all of them to detect errors. This scheme, known as multiple sample check (MSC), has been shown to reduce the probability of undetected errors [17]. The main issue is that MSC cannot deal with soft errors that produce a single error output. For the case that a transpose FIR filter is used in the fault-tolerant system in Fig. 2, single bit errors on the data registers are always detected as they add an error e = 2q that cannot be a multiple of m = 2k − 1. However, single bit errors on the coefficients may not be detected, and the undetected errors occur only if (x[n])m = 0, the proof of which is given as follows. Proof: Assuming that the first branch is correct and an SEU happens on the qth bit of h[2] in the second normal branch, then we have: y2 [n] = x[n − 2] · 2q +
L−1
x[n − l] · h[l].
(3)
l=0
The error is undetected if (y1 [n])m = (y2 [n])m , which means that (x[n − 2] · 2q )m = (x[n − 2])m · (2q )m = 0. When m = 2k − 1, we have (2q )m = 0, and therefore, the error is undetected if and only if (x[n − 2])m = 0. End of Proof: For the input x[n] with common distributions, such as uniform, normal, Rayleigh, and so on, (x[n])m is always uniformly distributed, so the probability of (x[n])m = 0, or an error being undetected, in a given cycle would be 1/m. Therefore, using larger values of m reduces the number of undetected errors. The problem is that using larger values of m increases the cost of the arithmetic residue FIR filter and, therefore, of the overall scheme. III. P ROPOSED S CHEME For the transpose-FIR-based fault-tolerant design in Fig. 2, to avoid undetected errors when an SEU affects the coefficients,
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Finally, the PSD for the case of all ones is given by R+1 (ejw ) =
∞ 1 1 2π − 2+ 2 δ(w − 2πk). m m m
(6)
k=−∞
Fig. 3. Structure of the arithmetic-residue-based fault-tolerant FIR filter with the alternating +1/ − 1 scheme for low-pass filter.
The derivations of (5) and (6) are summarized in the Appendix. Now, assuming a filter that has a passband B, the in-band power can be calculated as 1 R(ejw )dw (7) P (B) = 2π B
which gives the following results: B 2mπ 2 m−1 B P±1 (B) = − arctan m(m − 2) 2π m(m − 2)π B × (m − 1) tan 4 1 B 1 − . P+1 (B) = m m2 2π Plsb (B) =
Fig. 4. Structure of the arithmetic-residue-based fault-tolerant FIR filter with the +1 scheme for high-pass/bandpass filter.
the input samples that make (x[n])m = 0 should be modified so that (x[n])m = 0 never occurs. For inputs with common distributions, the modification would be done for 1/m of the input samples on average. The simplest way to modify the input sample with (x[n])m = 0 is to change the value of its least significant bit, which would add a 1 or a −1 to that input sample. This modification adds some noise to the input signal that can slightly degrade the signal quality. This effect can be minimized by taking into account the characteristics of the filter. For example, if the filter is low pass, instead of changing the value of the least significant bit, a sequence of alternating +1 and −1 can be used for the input samples with (x[n])m = 0. The structure of this scheme is shown in Fig. 3. The alternating +1/ − 1 sequence has most of its energy in the stopband of the filter, and therefore, most of it will be removed by the filter. Similarly, for a high-pass or a bandpass filter, a sequence of only +1 can be used such that, again, most of the energy falls on the stopband of the filter. This is illustrated in Fig. 4. For a common distributed input, it is possible to determine analytically the power spectrum density (PSD) of the signal added to the input. The three cases described before are considered. 1) The least significant bit is changed. 2) A sequence of alternating +1 and −1 is used. 3) A sequence of +1 is used. In the first case, the added signal is random, and its PSD is given by Rlsb (ejw ) =
1 . m
(4)
In the second case, the calculation is more complex, and the following result is obtained: e−jw 1 1 ejw R±1 (ejw ) = − 2 + . (5) −jw jw m m 1− m−2 1− m−2 m e m e
(8)
(9) (10)
To better understand the benefits of the second and third modifications that take into account the characteristics of the filter, they are compared with the first. Figs. 5 and 6 show the PSD and in-band noise of the first and second modifications. It can be observed that the second modification reduces the inband noise significantly when the passband of the filter is small. The reduction is larger for smaller values of m. Since small values of m are also preferred to minimize the overhead, it can be concluded that the alternating +1/ − 1 scheme should be used with m = 3 when the passband is not too wide. For a wide passband, the simplest last bit change scheme should be applied. Figs. 7 and 8 show the PSD and in-band noise of the first and third modifications. It can be observed that the third modification also reduces the in-band noise power and that the reduction is larger for smaller values of m. Therefore, following a similar reasoning as in the previous case, the +1 scheme should be used with m = 3. In this case, the width of the passband does not influence the results. In all cases, the added noise is small, and for the second and third, the in-band noise will be, in many cases, negligible. IV. E VALUATION To evaluate the effectiveness and complexity of the proposed modifications, they were implemented in hardware description language and mapped onto an FPGA. In particular, a 16-tap FIR filter with 8-bit inputs and 8-bit coefficients is implemented in ISE11.1 for Xilinx Virtex 4 XC4VLX80. The output is quantized with 18 bits. Fault injections were performed for m = 3 and 7 for each scheme. In the fault injections, 10 000 SEUs are injected into the data registers, and another 10 000 SEUs are injected into the filter coefficients. The position of SEU for each injection is selected randomly, and whether or not the fault caused by the injected SEU is detected is recorded for each injection. The results showed that the last bit change scheme, the alternating +1/ − 1 scheme, and +1 scheme achieve zero fault missing.
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Fig. 5.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 60, NO. 8, AUGUST 2013
PSD for the last bit upset scheme and the alternating +1/ − 1 scheme.
Fig. 7.
PSD for the last bit upset scheme and the +1 scheme.
Fig. 6. In-band noise power for the last bit upset scheme and the alternating +1/ − 1 scheme for a low-pass filter.
Fig. 8. In-band noise power for the last bit upset scheme and the +1 scheme for a high-pass/bandpass filter.
To put the cost of the technique in perspective, its cost is compared with that of the following: 1) TMR; 2) a traditional arithmetic-residue-based SEU-tolerant FIR filter design; and 3) a traditional arithmetic-residue-based design in which the coefficients are also protected with a parity bit. This last scheme is an alternative to protect the coefficient registers to avoid undetected errors. The results are summarized in Table I. It can be observed that the overhead of the alternating +1/ − 1 scheme is only about 1%–3% over the traditional arithmeticresidue-based scheme. The increased overhead comes from the logic for checking of (x)m = 0 and the additions of +1 and −1. The overheads for the +1 scheme and the last bit change are even lower as they are simpler. The cost is also lower than that of a traditional residue implementation in which the coefficients are protected with a parity bit (for example, for m = 3, the number of look up table (LUT) required is reduced by more than 12%). In summary, the comparison results tell that the overhead required to implement the proposed schemes is negligible and lower than the other schemes.
TABLE I I MPLEMENTATION C OST FOR THE D IFFERENT S CHEMES
V. C ONCLUSION This brief has proposed new schemes to avoid undetected errors caused by both soft SEUs and hard SEUs in arithmeticresidue-based fault-tolerant FIR filter implementations. The proposed techniques introduce a small modification of the input signal to ensure the detection of all single bit errors affecting the coefficients or data register bits. The added signal has a small impact on the output, and its effect can be minimized for lowpass and high-pass/bandpass filters by appropriately choosing the modifications.
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TABLE II T RANSIT P ROBABILITIES FOR A LTERNATING +1 AND −1
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the autocorrelation of the modification sequence is 1 1 1 − 2 δ(l) + 2 r[l] = m m m
(14)
and the PSD is simply R+1 (ejw ) = The proposed schemes have been implemented and tested on an FPGA showing their effectiveness in avoiding undetected errors. Their overhead in terms of logic resources has also been evaluated, and the results are found to be negligible. A PPENDIX This appendix provides the mathematical derivations of (5) and (6) for the reader interested in the details. For the case of adding a sequence ak of alternating +1 and −1, the probability that ak takes a given value depends on ak−1 , as summarized in Table II. Based on Table II, the autocorrelation function r[l] = E[ak ak−l ] can be obtained as ⎧ m−2 l−1 1 ⎪ , l = 1, 2, . . . , +∞ ⎨ − m2 m 1 , l=0 r(l) = m (11) ⎪ ⎩ 1 m−2 |l|−1 , l = −1, −2, . . . , −∞. − m2 m Then, taking the z transform, we get R(z) =
+∞
r(k)z −k
k=−∞
= r(0) +
+∞
r(k)z −k +
k=1
k=1
−
r(−k)z k
k=1
1 1 − = m m2 +∞
+∞
m−2 m
k−1
z −k
k−1 +∞ m−2 1 zk m2 m
k=1
1 1 − 2 = m m
z −1 1−
m−2 −1 m z
+
z 1−
m−2 m z
(12)
which finally gives us the PSD of the added signal e−jw 1 1 ejw jw R±1 (e ) = − 2 + . (13) −jw jw m m 1− m−2 1− m−2 m e m e For the case of adding a sequence of ones, the autocorrelation is given by 1/m for l = 0 and 1/m2 for l = 0; therefore,
∞ 1 1 2π − 2+ 2 δ(ω − 2πk). m m m
(15)
k=−∞
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