Nov 28, 1994 - Abstract: The paper presents two new linear systolic architectures for the one-dimensional dis- crete Hartley transform (DHT). Both architectures.
Efficient CORDIC-based systolic architectures for the discrete Hartley transform W.-H. Fang J.-D. Lee
Indexing terms: Discrete Hartley transform, Signal processing, Systolic arrays, VLSI
Abstract: The paper presents two new linear systolic architectures for the one-dimensional discrete Hartley transform (DHT). Both architectures exhibit several desired features such as regularity, modularity and high pipelineability, which make them amenable to VLSI hardware implementation. In addition these new architectures use the CORDIC (co-ordinate rotation digital computer) algorithm as the basic function for each PE (processing element) which has been shown to be an appealing approach to compute trigonometric functions. Combination of these two array processors to form a new fully pipelined meshconnected systolic architecture for the two-dimensional (2-D) DHT is also addressed. This new architecture, which uses Horner’s rule and the symmetric property of the transform by folding the data either in the time domain or in the frequency domain, yield higher throughput with reduced hardware complexity compared with other existing ones for both the 1-D and 2-D case.
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Introduction
The discrete Hartley transform (DHT) was first presented by Bracewell in 1983 as an alternative to the well known discrete Fourier transform (DFT) [l]. For a data sequence {x},:, its DHT is defined as N-1
