Efficient Latch Optimization Using Exclusive Sets Ellen M. Sentovich , Horia Toma , Ge´rard Berry CMA – Ecole des Mines de Paris Cadence Berkeley Labs
Abstract Controller circuits synthesized from high-level languages often have many more latches than the minimum, with a resulting sparse reachable state space that has a particular structure. We propose an algorithm that exploits this structure to remove latches. The reachable state set (RSS) is much easier to compute for the new, smaller circuit and can be used to efficiently compute the RSS of the original. Thus we provide a method for obtaining the RSS, and two different initial implementations from which to begin logic optimization.
1
Introduction
The computation of the reachable state set (RSS) of a sequential circuit is important for verification, logic optimization and test generation. The RSS computation is typically done incrementally, by looping over a computation of the next states as the image of the current states by a vector of Boolean functions [3]. When BDD-based algorithms are used, the variables are the latches and the circuit inputs. Therefore, the number of latches greatly affects the efficiency, both in memory and computation time. In this paper, we propose a new latch removal algorithm that greatly increases the efficiency of the the RSS computation while optimizing the circuit (by eliminating latches). We derive an overapproximation of the RSS (called ORSS) directly from the initial high-level specification. We then use the ORSS to compute the latches to be removed. We remove them, and compute the precise RSS of the new circuit from which we can compute the precise RSS of the original circuit. We note that the ORSS, while only an approximation of the RSS, can be used for:
We concentrate on control or glue logic circuits programmed in the E STEREL synchronous language [1, 2] and on a particular kind of ORSS derived from exclusive threads of control that occur naturally in the specifications. From this ORSS based on exclusive threads, we compute precisely sets of exclusive latches in the generated circuit. Two sets of latches L1 and L2 are exclusive if all registers in L2 have value if at least one register in L1 has value and conversely. In an E STEREL sequence p q , the sets of latches generated by p and q are exclusive. Since sequencing and concurrency can be mixed at any level, the exclusive sets structure can be quite rich; consider for example p q r s t u . The richer the structure is, the better the ORSS is. Furthermore, the ORSS formula is very easy to compute, unlike the exact RSS. Exclusive sets of latches can be easily and efficiently re-encoded in such a way that the total number of latches is decreased. Let M be the initial circuit and M 0 be the re-encoded one. Since M 0 has less latches, its RSS R0 is easier to compute than that of M . Furthermore, the original RSS R can be easily recovered from R0 . Optimization and verification can then proceed either from M and R or M 0 and R0 , whichever is best. Exclusive sets can also be computed from the exact RSS. They can be used for latch removal in complement to the techniques formerly presented in [7]. In Section 2, we give an overview of the algorithm, the circuit transformation it employs and its important properties. The reencoding by exclusive sets is given in Section 3 and its properties are presented in Section 4. The results of our implementation are presented in Section 5. Conclusions of our work and directions for future developments are presented in Section 6.
0
;
1
( jj ; ); ( ; jj )
2 Overview of the Algorithm The algorithm for exclusive-set latch removal proceeds as follows:
1. verification, where an ORSS may be sufficient for checking a particular property [9, 10].
1. Derive the ORSS from the structure of the high-level language description.
2. logic optimization, where the complement of the ORSS is a set of don’t care conditions [7, 8].
2. Compute the exclusive latches and determine two maximal exclusive sets of latches using the ORSS. These two sets of latches can be multiplexed through a single set, with an additional latch for the multiplexer.
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3. Remove one of the latch sets, add the multiplexing logic and update the ORSS. 4. Iterate, removing as many latches as possible, or as many latches as desired given constraints on the size of the combinational logic.
5. Compute the exact RSS on the new circuit, and use it to compute the exact RSS for the original circuit.
2.1
General Circuit Transformation
A framework for state re-encoding was described in [7] and is illustrated in Figure 1. We use the same framework for exclusive sets. M
M’ Out
In
Out
In
C
C n
n
n
n
Y D
L
n’
L’
n’
Y
techniques of latch removal (Section 4.4 and [7]) so it can be applied in conjunction with them without affecting their efficacy. The logic added by the transformation is strictly controlled, see Section 4.2, and the initial logic structure is preserved as much as possible as it contains valuable information about the natural structure of the circuit. Thus the computations required remain tractable for very large circuits, as does the additional combinational logic, which is usually the most limiting factor in incremental re-encoding algorithms. Finally, the transformation preserves behavior on the RSS and remains correct for every other over-approximation of it, see Section 3.2. Therefore it can be used in conjunction with other efficient techniques for approximate reachability analysis [4].
E
3 The Exclusive Sets Transformation 3.1
Figure 1: General Circuit Transformation The original FSM is M and the transformed one is M 0 . We call L li i n the set of latches of M , and L0 the set of latches of M 0 . Our transformation computes two sets of latches L1 li i I1 L and L2 li i I2 L such that L1 L2 k ; it re-encodes them with a new set of0 latches L01 L0 such that L01 k and a new register denoted ln+1 . For convenience, the latches in the set L01 will have the same indices as lj0 j n ; j = I2 . those in L1 . The set L0 is then L0 . The size of L0 is n0 n k The next-state vector for L in M is generated by C and called Y . In M 0 , the encoding function E has type B n B n0 , with comn B0 , i n ; i I2 . The decoding ponents Ei B function D has type B n B n , with components Di B n0 B , i n. 0 Let R B n (resp. R0 B n ) be the set of reachable states in 0 0 M (resp. M ), and let and denote the characteristic function r 0 iff r R). Let r0 and r00 denote the of R and R0 (i.e., initial states of M and M . Clearly, M is equivalent to M 0 if r0 D r00 and D E r r for all r R. This is the equivalence property our transformation satisfies. Functions will be represented by polynomials or BDDs. The input variables will be consistently called yi for E , li0 for D, li for , and li0 for 0 . If F denotes a polynomial or BDD over a set of variables X with a set of associated indices IX , for Y another set of IY , variables with a set of associated indices IY where IX IY , we denote by F Y=X map the result of and for map IX the substitution of the xi by the ymap(i) , and F Y =X map the result of the substitution of the xi by the complements ymap(i) . We denote by Fx (Fx ) the positive (negative) cofactor of F with respect to x. If X is a set of variables, we denote by FX (FX ) the result of successive positive (negative) cofactoring of F with respect to each x X.
= f j1 g =f j 2 g j j=j j= 2 j j=
1
R
!
R( ) = 1
( )
( ( )) =
R
!
:
2
!
=
2
:
!
l1 = 1 ) l2 = 0 l2 = 1 ) l1 = 0
[
[
]
Rl1 ;l2 = 0:
The exclusive-set latch removal implies a re-encoding that is reversible: it is a one-to-one function that is easily computed. As a result, the RSS of the initial circuit can be recovered by a simple BDD operation, even after multiple iterations (see Section 4.1). This is an important feature when the algorithm is used as part of an optimization strategy. The re-encoding is also localized to the Boolean sub-space defined by the exclusive sets; the remaining latches are unchanged. This implies commutativity properties when applied iteratively (Section 4.3). The transformation also commutes with our other
L and L2 L are
8l1 2 L1 ; 8l2 2 L2 ; l1 #l2 (3) In the sequel, we assume that jL1 j = jL2 j. If jL1 j jL2 j we simply choose a subset L2 L2 such that jL1 j = jL2 j. L n fL1 [ L2 g L n fL1 [ L2 g 0
0
P2
P1
L2
L1
]
Properties of the Transformation
(2)
Definition 2 Two disjoint sets of latches L1 said to be exclusive if
j j=j j
2
(1)
The equations (1) are equivalent to :
R
R
2.2
#
= f j 1 +1 2 g
1 + 1 62
!
Definition 1 Two latches l1 and l2 are said to be exclusive, denoted l1 l2 , if for each reachable state :
=f j 2 g
= , +1
:
Exclusive Sets of Latches
P2
P1
ln+1
L1
a)
b)
Figure 2: Partition of the RSS by exclusive sets L1 and L2 A geometrical interpretation of the partition of the RSS by L1 and L2 is given in Figure 2a). The axis labeled L1 contains the circular Gray code of Boolean encodings of the integers in the interval ; jL1 j (similarly for the axes labeled L2 and L L1 L2 ). A point in the cube represents a state, and its encoding is retrieved by concatenation of the projections on the axes. If L1 #L2 , the reachable states are points in the cube only on the hyper planes P1 L1 L L1 Ln 2 and P2 L2 L L1 L2 , and the rest of is empty. the hypercube
[0 2 ,1]
n( [ ) B
3.2
n( [ )
= n( [ )
=
Transformation
The hyper planes P1 and P2 in Figure 2a) are each Boolean spaces L1 , so we can represent their union using only of dimension L L L1 state variables instead of the L state variables of
j j,j j j j,j j+1
j j
the initial circuit. Recall all reachable states lie on P1 and P2 . The purpose of the exclusive sets transformation is to replace the latches in the set L2 by a single latch ln+1 as shown in Figure 2b). That is, L1 and L2 share a single set of latches that are multiplexed through ln+1 . I2 that pairs First we define a bijective function map I1 elements of I1 and I2 in an arbitrary fashion. Given map, the equations corresponding to the circuit transformation are :
:
!
( Ei (Y ) = yi + ymap(i) ; i 2 I1 Ej (Y ) = yj ;Pj 2= I1 [ I2 En+1 (Y ) = i I1 yi ( Di (L ) = l l ; i 2 I1 n+1 i Dmap(i) (L ) = ln+1 li ; i 2 I1 Dj (L ) = lj ; j 2= I1 [ I2
(4)
2
0
0
0
0
0
0
0
(5)
0
The encoding logic En+1 creates the multiplexer control : it is the condition that any latch in L1 is active. Ei re-encodes L1 as the union of the L1 and L2 active conditions. The decoding logic D reproduces the correct reachable states : if r R, D E r r. The reachable states are updated as follows:
( ( )) =
2
R = (RL2 0
3.3
X
0
li L1 2
li )[L =L]ln+1 + RL1 [L =L]map,1 ln+1 0
0
0
(6)
Exclusive Sets Computation
For E STEREL -produced circuits, we efficiently generate exclusive sets from the ORSS which is derived directly from the structure of the specification. For arbitrary circuits, we can also compute exclusive sets from the RSS by using equation (2). We search for a pair of exclusive sets L1 and L2 of maximum size (which does not guarantee a global optimum). This problem is equivalent to the NP-hard balanced complete bipartite graph problem [5], where each node i represents a latch and each undirected edge i; j represents an exclusive pair. When the circuits have many latches with a high degree of incompatibility, the bipartite algorithm is too expensive and we have adopted a greedy bounding heuristic.
( )
4
performed for optimization purposes, the most critical point is the size of the k-input OR gate which may need to be implemented by several levels of logic depending on the technology library. In that case, it may be better to optimize the original circuit now knowing its RSS R.
4.3
Commutativity
To understand the behavior of the algorithm over several iterations, we have to examine how the removal of latches for a pair of exclusive sets affects the conditions for other pairs of exclusive sets. Proposition 2 Let L1 , L2 , L3 and L4 be sets of latches such that L1 L2 ; L3 L4 . Then L3 L4 will remain true after the exclusive L3 L4 . sets transformation over L1 and L2 if L1 L2
#
#
#
When the commutativity property holds, it simplifies the updating of the list of exclusive sets corresponding to each latch. We simply remove from them the latches implied in the previous transformation, without recomputing the incompatibilities over the new reachable state space.
4.4
Exclusive Sets Transformation single-latch Removal
R R = 0
is in general not preserved by state space re-encoding.
P1 1
L n fL1 [ L2 g P2 1
P1 0
P2 0 L2
L1
Recovering the original RSS
One can recover R from R0 knowing only the map latch assignment function:
R
Proposition 1 Let 0 be the characteristic function of the RSS of the circuit M 0 obtained by performing the exclusive set transformation using L1 and L2 of M . Then the RSS characteristic function of the initial circuit can recovered as follows :
R
R = R l +1 [L1 =L1 ] 0
0
n
Y
lj + R l
lj L2 2
4.2
+1 [L2 =L1 ]map
0
Logic Cost
Y
0
n
,1
li L1
li
2
2
(7)
The circuit transformation replaces k latches with k binary AND gates, k binary OR gates and a k-input OR gate. The additional logic is not critical if the transformation is performed with the aim of computing the reachable states. In this case, any penalty in BDD size increase caused by the additional logic is easily comlatches. If the transformation is pensated by the removal of k
,1
Versus
The single-latch removal [3, 6, 7] algorithm is useful in logic optimization because of its incremental nature and tight control of the size of the additional logic. The condition for single-latch removal, (8) li li
Properties
4.1
( [ )\( [ ) = ;
L n fL1 [ L2 g P1 0 + P1 1
P2 0 + P2 1
L2
L1
a)
b)
Figure 3: Representation of the single-latch removal of context of exclusive sets L1 and L2
lk in the
The single-latch removal of a latch li is intuitively a pairing of states in Rli and Rli . Figure 3 shows the reachable state space before and after removal of latch lk L L1 L2 . Semi; planes P1 1 and P2 1 contain all reachable states where lk P1 0 and P2 0 all reachable states where lk . The pairing is graphically equivalent to folding P1 1 onto P1 0 and P2 1 onto P2 0 as shown in Figure 3b). By cutting the planes in Figure 2b, we can make the same reasoning about the fact that the condition necessary for single-latch removal (8) remains true after an exclusive sets transformation for lk L L1 L2 . Thus, for lk = L1 L2 the exclusive latch condition is preserved during single-latch removal and the single-latch removal condition is preserved during the exclusive set transformation.
2 n( [ )
=0
2
[
2 n( [ )
=1
Circuit abc abcdef controle controlecount habault renault runner sequencer snecma tcint tcintnocount t-count t-controller-count t-mult-control t-simple-control
#in 4 7 10 10 4 23 6 55 23 19 13 3 3 2 3
#out 12 24 8 8 19 179 5 98 7 20 22 12 11 6 11
#reg 13 25 24 23 90 66 30 121 70 96 90 32 68 21 67
#states 16 128 20 211 66 257 5182 109415 10241 2826 310 358 540 32 451
ORSS 10 19 11 19 67 37 29 – 54 50 38 28 61 19 60
RSS 8 14 11 17 40 19 22 58 40 46 42 22 38 13 39
Table 1: Results of the exclusive sets in latch removal Circuit abc abcdef controle controlecount renault runner sequencer snecma tcint tcintnocount ww
#in 4 7 10 10 23 6 55 23 19 19 8
#out 12 24 8 8 166 5 98 5 20 20 99
remlatch #reg #lit 4 111 9 215 16 135 14 140 28 497 15 198 60 1021 21 407 38 237 38 194 6 217
[1] G. Berry. Esterel on hardware. Philosophical Transactions Royal Society of London A, 339:87–104, 1992. [2] G. Berry and G. Gonthier. The Esterel Synchronous Programming Language: Design Semantics, Implementation. Science of Computer Programming, 19(2):87–152, 1992. [3] C. Berthet, O. Coudert, and J.C. Madre. New Ideas on Symbolic Manipulations of Finite State Machines. In Proc of ICCAD, October 1990. [4] H. Cho, G. D. Hachtel, E. Macii, M. Poncino, and F. Somenzi. A Structural Approach to State Space Decomposition for Approximate Reachability Analysis. In Proc of the ICCD, October 1994.
2
Proposition 3 If L1 and L2 are two exclusive sets, and if lk = L1 L2 is single-latch removable, then the exclusive latch transformation for L1 ; L2 and the single-latch transformation for lk commute.
Observation : The property remains true for generalizations of the single-latch technique [7].
5
We have experimentally demonstrated that the exclusive sets transformation is very useful for circuits with sparse state encodings. Our techniques are particularly useful for controllers generated from E STEREL , for which the basic synthesis process usually generates too many latches. We are now including the algorithms in the E STEREL v5 compiling and optimization chain. A nice feature of the exclusive sets transformation is that the original RSS can be cheaply recomputed from the RSS of the transformed circuit. It will also be interesting to explore the possibility of performing a similar backwards RSS computation for other latch removal techniques.
REFERENCES
excl #reg #lit 4 111 8 209 8 187 11 187 14 509 15 198 36 1209 18 433 21 347 18 312 6 217
Table 2: Remlatch [7] followed by Exclusive sets
[
6 Conclusions
Results
The benchmarks we used are circuits synthesized by the Esterel v5 compiler, and the results are summarized in Tables 1 and 2. Some of them are simple programs, such as abc, abcdef. The remaining files come from industrial designs, and some of them are quite large (sequencer, tcint, renault, snecma). They are all control or glue logic circuits. In Table 1 we compare the number of latches removed by the exclusive sets transformation using ORSS structural information from the E STEREL description (column ORSS ) with the number obtained using exclusive sets computed from the exact RSS (column RSS ). Since the ORSS is easy to compute, the ORSS-based algorithm is orders of magnitude faster than the RSS-based one at the expensive of accuracy: fewer exclusive latches are found on the ORSS. As mentioned in Section 3.3, the algorithms compute the exclusive condition exactly, but remove latches greedily. This explains the fact that for file tcintnocount the result with ORSS is better than with RSS. In Table 2 we present the results of applying first the latch removal algorithms presented in [7] (column remlatch) and then the RSS-based exclusive sets algorithm (column excl). The exclusive sets algorithm removes latches that cannot be removed by the previous techniques, but the combinational logic tends to increase.
[5] M.R. Garey and D.S. Johnson. Computers and Intractability. W.H. Freeman and Company, 1979. [6] B. Lin and A. Richard Newton. Exact Redundant State Registers Removal Based on Binary Decision Diagrams. In Proc of the International Workshop on Logic Synthesis, may 1991. [7] E. Sentovich, H. Toma, and G. Berry. Latch Optimization in Circuits Generated from High-level Descriptions. In Proc of ICCAD, November 1996. [8] E.M. Sentovich, K.J. Singh, C. Moon, H. Savoj, R.K. Brayton, and A. Sangiovanni-Vincentelli. Sequential Circuit Design Using Synthesis and Optimization. In Proc of the ICCD, pages 328–333, October 1992. [9] T. Shiple, G. Berry, and H. Touati. Constructive Analysis of Cyclic Circuits. In ED-TC, pages 328–333, March 1996. [10] G. Stalmarck. A system for determining propositional logic theorems by applying values and rules to triplets that are generated from a formula. In U.S. patent 5 276 897, 1989.
