Analog Integr Circ Sig Process (2006) 48:231–237 DOI 10.1007/s10470-006-7741-5
Efficient, ROM-less DDFS using non-linear interpolation and non-linear DAC A. L. McEwan · S. Collins
Received: 7 December 2005 / Accepted: 13 February 2006 / Published online: 15 May 2006 C Springer Science + Business Media, LLC 2006
Abstract A non-linear interpolation based ROM-less Direct Digital Frequency Synthesisiser (DDFS) is more efficient than previous systems as each current cell in a non-linear DAC is used more effectively. This was achieved by forming an analogue voltage from a small linear DAC addressed by phase bits that are usually discarded. The analogue voltage was connected to a selected current source in a thermometer decoded non-linear DAC to allow nonlinear interpolation between the conventional, phase limited output levels. By increasing the number of phase bits the spurious free dynamic range (SFDR) was improved without increasing the size of the non-linear DAC. Modelling and simulation of the non-linear response of the differential switch based current cell revealed suitable parameters. The architecture of 64 current cells used a modified thermometer decoder and three-state switch in each current cell. Simulation and testing of 10 sample circuits demonstrated a robust DDFS with SFDR better than − 60 dBc and suitable for use in a wide range of instrumentation systems. Keywords Direct Digital Frequency Synthesis . DDFS . Instrumentation systems . Waveform generation . Nonlinear DAC A. L. McEwan () · S. Collins Department of Engineering Science, University of Oxford, Parks Road, Oxford, UK, OX1 3PJ e-mail:
[email protected] S. Collins e-mail:
[email protected] Present address: A. L. McEwan Department of Medical Physics and Bioengineering, Gower St, London, UK, WC1E 6BT
1. Introduction Direct Digital Frequency Synthesis (DDFS) is a useful technique for generating a signal with a good spectral purity and an easily variable frequency that is conveniently integrated with digital electronics. It is therefore not surprising that this technique is increasingly used in a wide range of instrumentation systems for impedance measurement [1, 2], AC metrology [3], determination of dielectric loss in lossy capacitors [4], capacitance microscopy [5], blood volume meters [6], force sensors [7], audiometers [8] and acoustic wave sensors [9]. These systems are based upon commercially available DDFS systems. However, in some instrumentation applications low power, inexpensive synthesizers are desirable to create integrated arrays of disposable sensors [10, 11]. A recent trend in the development of DDFS systems has been the emergence of ROM-less architectures that have been devised to avoid the high power consumption and slow access times of the large ROMs required in conventional architectures. We have previously suggested a novel method of reducing the size of the non-linear DAC used in some ROM-less DDFS systems [12]. Analogue interpolation was used in one of the cells of a current steering non-linear DAC in order to improve the spectral purity of the DAC output without significantly increasing its size. The resulting system had a better spurious free dynamic range than the equivalent systems. This paper presents the essential implementation details and compares simulation with prototype chip results. Section 2 introduces the DDFS method and reviews recent ROM-less DDFS systems. Section 3 describes the proposed ROM-less architecture based on a nonlinear DAC. Two integral components are a three state switch and a modified thermometer decoder which are specified in Section 4. Circuit simulations of the
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system in Section 5 show surprisingly good performance for a system based upon a small non-linear DAC. These simulation results are confirmed by the measurement results in Section 6.
ing approach should be used to synthesis high frequency output signals. In particular, a system containing 192 current sources in a non-linear DAC has been shown to achieve a SFDR of better than −55 dBc.
2. Direct digital frequency synthesis (DDFS)
3. The proposed architecture
2.1. Conventional DDFS
The starting point for the proposed architecture is a thermometer decoded DAC. Using the most-significant bit from the accumulator to exploit the symmetry of a cosine function means that the non-linear DAC only needs to represent half of one period. Then to represent a cosine function the ith current source in a non-linear DAC containing N current sources is designed so that
A conventional DDFS architecture, Fig. 1 [13], uses an overflowing accumulator to produce a digital phase. This forms the address to a ROM lookup table of amplitude values that are then converted into an analogue output by a DAC [14]. The result is an output signal whose frequency is determined by the clock frequency and a user defined digital input to the accumulator. The key advantages of a DDFS architecture is that the frequency of the output signal is stable, can be controlled accurately and changed quickly. The main challenge when designing a DDFS system is to ensure that these advantages are achieved at an acceptable price and power consumption. A key factor in limiting both the price and the power consumption of a conventional DDFS system is the size of the ROM. Most of the recent developments in DDFS architectures have therefore focused upon a variety of techniques to minimise the size of the ROM [14–16]. The challenge for all these techniques is to shrink the ROM whilst maintaining the spectral purity of the output signal. For a sinusoidal output signal this spectral purity is characterised by the Spurious Free Dynamic Range (SFDR), which is the ratio of the power at the desired output frequency to the power of the most powerful unwanted frequency in the output spectrum. An alternative approach to solve the problems caused by a large ROM is to combine the functions of the ROM and the DAC to create a ROM-less architecture. The two different approaches to ROM-less DDFS that have been explored are based upon either resistor-based [17, 18] or current steering non-linear DACs [19]. A comparison of these two approaches shows that the resistor-based system is more power efficient at low output frequencies, but that the current steer-
Ibiasi = Iamp ∗ (cos((i − 1)π/N ) − cos(iπ/N ))
(1)
The number of current sources within the DAC must then be chosen to prevent the corresponding phase truncation from degrading the SFDR of the output signal. For a non-linear DAC with a W-bit address phase truncation will give a SFDR of −6(W + 1) dBc. This means that it will require a 9-bit address, and hence 512 current sources, to achieve a SFDR of −60 dBc. One method to reduce the size of the non-linear DAC, whilst maintaining the SFDR of the output signal is to segment the digital phase word to address a coarse and a fine DAC whose outputs are combined to create the final output [20]. This paper investigates an improvement by following an alternative strategy of using only a few current sources in the non-linear DAC by making efficient use of each current source. In a high speed, CMOS current steering DAC differential current switches such as the one in Fig. 2 are employed in each cell to reduce glitches in the output signal. In a conventional design the input voltage to the switching circuit is one of two values chosen to switch the output current with the minimum distortion. However, if an analogue voltage is applied to this circuit and it is assumed that the two switch transistors are both matched and operating in saturation, then a simple model of these MOSFETS predicts
Fig. 1 The architecture of a conventional direct digital frequency synthesizer. First proposed by Tierney, Rader and Gold
Reference Clock Fclk
Fclk Phase Accumulator
Fclk ROM lookup table
Fclk DAC
Fout
L Phase Word (PW) digitally determines F out
Digital Phase
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Digital Amplitude
Analogue Amplitude
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Fig. 2 A differential current switch. The current is steered between the two transistors by changing the input voltage
I out1
I out2 I bias I out2
Current Switch
V in
M1
M2
V ref
I out1
I bias 2
I bias 0 Vbias
that the the current flowing through M1 will be
Iout
2 (Vin − Vref )2 Ibias β (Vin − Vref ) − − = 2 2 β 4
2Ibias β
(2)
(3)
This suggests that this circuit will act as a digital switch when either voltage Vlow = Vref −
2 Ibias /β
(4)
2 Ibias /β
(5)
or Vhigh = Vref +
are applied to the circuit. More importantly, Eq. (2) shows that if a voltage between these values is applied to the circuit then a fraction of available bias current is steered to the output.
L bit Phase Accumulator for frequency resolution
Fig. 3 The proposed architecture of a DDFS system based on analogue interpolation
V high
V in
An architecture which applies an analogue voltage to one current cell within a non-linear DAC to improve the SFDR of the resulting signal is shown in Fig. 3. This architecture includes an L-bit accumulator to ensure good frequency resolution. As in other DDFS systems the most significant bit of the accumulator output is used to take the 1s complement of the remaining phase bits (XOR) to take advantage of the half wave symmetry of the cosine wave. The next W bits are used to thermometer decode the non-linear DAC. In addition to the conventional components of a ROM-less DDFS system, this new architecture includes a linear DAC, referred to as the Phase DAC, whose output analogue voltage represents the D most significant phase bits that would otherwise be discarded by the system. The output voltage from this Phase DAC forms an additional input to the non-linear DAC. Within the non-linear DAC this analogue voltage is applied to the current source that is next to the last cell turned on by the thermometer decoder. In this way the system uses analogue interpolation within the non-linear DAC to improve the SFDR of the output signal by increasing the phase accuracy.
where Vin is the input voltage, Vref is a constant reference, Ibias the constant current source and β is the transconductance parameter of the two, well matched switch transistors (M1 and M2). This equation predicts that Iout = 0 when (Vin − Vref )2 =
V ref
V low
Current Source
4. A modified thermometer decoder A nonlinear DAC with 64 current cells was chosen as the basis of a prototype system [21]. In a typical high speed
XOR
W MSB
P bits
Interpolation Nonlinear
Thermometer Decoder
DAC Sine Output
D LSB
Phase DAC (linear)
Vphase Analogue Phase Interval
L–P Phase bits Discarded
Vphase 0
Π/64 time
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Fig. 4 The decoding logic necessary for the interpolating thermometer decoder
rowi rowi+1
Latch
Cell fully off (Lo)
colj
rowi rowi+1
Latch
Analogue phase voltage to cell (An)
Latch
Cell fully on (Hi)
colj colj+1
colj+1 rowi rowi+1 clk
current steering DAC the 64 current cells are arranged in an 8 × 8 array and the thermometer decoder consists of row and a column decoders each of which receives three of the six input bits. Decoding logic within each current cell is then used to decode the row (row) and column (col) signals from the decoders to determine if the cell should be switched on or off. To allow the analogue input voltage to be applied to the correct cell this decoder must be modified. In particular, the decoder must identify the current cell that would be switched on next if the phase of the signal increased. The analogue voltage can then be applied to this cell so that it contributes part of its current to the output. The information required to identify this cell is contained in the signals from two neighbouring rows and two neighbouring columns. The logic needed to decode these four signals, referred to as rowi , rowi+1 , col j and col j+1 , is An = (rowi XOR rowi+1 ) AND (col j XOR col j+1 )
(6)
H i = (rowi AND rowi+1 ) OR (rowi XOR rowi+1 )col j+1
(7)
Fig. 5 A conventional current cell with a three state analogue switch. The sequence shown in figure is: Initially Lo is enabled to hold the gate of the differential pair low, An and Hi disabled. An is enabled to connect the analogue signal, Vphase through the transmission gate switch. Hi is enabled to hold the output high. The logic defines that only one enable signal is valid at any one time. The response of the cell when the phase word is one is shown for clarity, most phase words result in a more discontinuous output
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Lo = (rowi AND rowi+1 ) OR (rowi XOR rowi+1 )col j+1 (8) This logic can be implemented using the circuit shown in Fig. 4. The three outputs from the cell decoding logic are applied to a three state analogue switch shown in Fig. 5 to connect the differential switch in each current cell to one of three possible input voltages. 5. Circuit simulations To determine the spectral purity that can be achieved by using interpolation in a nonlinear DAC, the proposed architecture was simulated using the device parameters for the AMS C35 0.35 µm CMOS process. The size of the current sources in each cell were set proportional to Ibiasi from Eq. (1). This meant that the total output current could be controlled via a single voltage bias, Vbias which is connected I out
Hi
V high
0 Hi An
V high I out V low
V high
V phase
An Lo
time
V
time
V low
0 0 1
0 1 0
1 0 0
0 1 0 I bias
V low Lo V bias
enable settings: Hi An Lo
ref
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Fig. 6 Circuit simulations of the system based on an array of 64 current cells in Cadence
low V
–6
=0.5mV
bias
x 10
current (A)
8 6 4 2 0
0.1
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1
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bias
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high V
–3
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bias
x 10 4 current (A)
3.8 3.6 3.4 3.2 0
0.1
to the gates of the 64 current sources. The quarter wave symmetry of the cosine wave (about π/2) means that the parameters are duplicated for half of the current cells (Ibias1 = Ibias64 , Ibias2 = Ibias63 , . . . Ibias31 = Ibias32 ). Next, to ensure that the same voltage swing, Vhigh − Vlow = 200 mV, can be used within each cell the β parameter for the switch devices in each cell was chosen to ensure that (Ibiasi /β) is the same in all the current cells. This scheme results in the output current (controlled via Vbias ) as the only undetermined paFig. 7 A zoomed in view of the smallest eight current cells in the simulated array of 64 current cells
0.2
0.3
0.4
low Vbias=0.5mV
–7
current (A)
0.6
rameter that can control the performance of the nonlinear DAC. The optimum value of this one remaining parameter was determined by simulating the circuit. Due to the high quality of the approximation to a cosine wave produced by the nonlinear DAC it is difficult to see any difference between the output signals at different bias voltages shown in Fig. 6. However, a closer inspection of part of the signals in Fig. 7 shows that when Vbias is too low the output from each cell
x 10 6.2 6 5.8
0.47
0.48
0.49
–4
0.5 optimum V =0.9mV
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bias
x 10
current (A)
0.5 time(s)
1.49 1.48 1.47 0.47
0.48
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high Vbias=1.5mV
–3
x 10
current (A)
3.034 3.032 3.03 3.028 3.026 3.024 0.47
0.48
0.49
0.5 time(s)
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Fig. 8 The relative power of various harmonics of the output frequency from a system based upon a 6-bit non-linear DAC predicted by circuit simulation
–50 2nd 3rd 5th 127th 129th
–52
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–56
SFDR (dBc)
–58
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1
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1.2
1.3
1.4
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vbias (V)
saturates before its neighbouring cell starts to contribute to the output. In contrast at higher values of Vbias the transitions between the output of each cell are quite abrupt and there are sudden changes in the gradient of the output signal. As shown in the central panel of Fig. 7, between these two types of behaviour there are bias conditions for which neither behaviour dominates. The effect of these subtle changes in the output signal on its quality are most clearly seen by calculating the spectrum of the output signal. The trend of the dominant harmonics at different bias current is shown in Fig. 8. As expected the change in behaviour observed in the output signal is reflected Fig. 9 Variation in the SFDR against the bias voltage of the current sources for 64 cells. The trends of the dominant harmonics are similar to those simulated in Cadence
as a change in the dominant harmonics at low and high bias voltages. Between these two different regimes there is a bias condition, at approximately 0.85 V, where the signal has an optimum SFDR of −66.5 dBc. These simulations therefore suggest that this circuit can generate an output signal with an SFDR that is 6 dB better than the previous designs.
6. Measurement results The simulated system has been fabricated in the AMS 0.35 µm C35 process. The prototype was based on the archi-
–45
chip1 chip2 chip3 chip4 chip5 chip6 chip7 chip8 chip9 chip10
–50
SFDR (dBc)
–55
–60
–65
–70 0.5
1
1.5 Bias voltage (V)
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tecture described so far with a current steering, 6-bit linear phase DAC included to provide the interpolating input signal. To ensure that faults could be identified in this novel architecture, the accumulator was not included on this chip. Alternatively the 13-bit digital input was generated in MATLAB and driven by a PowerDAQ data acquisition system that was also used to generate the bias and reference voltages. The output data for different bias voltages was transferred from an Agilent 4155B semiconductor analyser to a PC. MATLAB software was then used to calculate the spectrum of each response to determine the magnitude of the dominant harmonics in the spectrum. Results from a sample of circuits on ten different chips are shown in Fig. 9. All chips behaved in a similar way. The most variation was at the optimal bias voltage and is due to device variations as the architecture depends on matched geometry across the array of current cells. The circuits achieve an optimum SFDR of −65 dBc and the trend of the SFDR in Fig. 9 follows a similar pattern to the envelope of the trend of the dominant harmonics predicted by circuit simulation, Fig. 8. This demonstrates that the model is a good indicator of performance and that the new architecture can produce a better output signal than previous designs despite having fewer current sources and more easily determined parameters.
7. Conclusion A new ROM-less DDFS architecture based on a thermometer decoded nonlinear DAC and nonlinear interpolation has been demonstrated. The design for this new architecture is based upon a few parameters most of which are calculated simply and one of which is easily determined by simulation. This simple design process leads to an architecture that gives a better quality output that previous designs despite using only 64 current sources. This compact architecture appears to be ideal for integration in emerging applications of DDFS in integrated instrumentation systems. Acknowledgment This work was supported by the Engineering and Physical Sciences Research Council, grant GR/N18048, and Analogue Devices Incorporated.
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