AN EFFICIENT CMOS DDFS ARCHITECTURE ... - University of Oxford

AN EFFICIENT CMOS DDFS ARCHITECTURE SUITABLE FOR BLUETOOTH Alistair McEwan and Steve Collins Department of Engineering Science University of Oxford Parks Road Oxford UK OX1 3PJ [email protected] ABSTRACT A promising candidate for signal generation in modern communications systems is direct digital frequency synthesis (DDFS) which is capable of well controlled, rapid changes in signal frequency, over a relatively large frequency range. Unfortunately, a conventional DDFS system requires a high frequency ROM which consumes most of the power. To avoid this problem a new architecture based on a small nonlinear digital to analogue converter (DAC) is proposed. The resulting low-power architecture meets the specifications of low power communication standards such as Bluetooth. 1. INTRODUCTION The Bluetooth specification requires a channel bandwidth of 1MHz which is frequency hopped over 79 channels every 625 s, with frequency resolution of 1ppm. Direct digital frequency synthesis (DDFS) is a good candidate for the frequency synthesizer in a Bluetooth system as it is capable of generating signals of high frequency resolution, low phase noise and fast frequency hopping. Additionally the DDFS is controlled completely by digital signals providing a good interface to digital baseband systems. Reference Clock

L−bit Phase Accumulator k

W−bit word ROM for Phase to Amplitude Conversion

DAC

Frequency Control Word (k bits) specifies output frequency as a fraction of reference clock

In Digital Domain

Fig. 1. Conventional DDFS Architecture A conventional DDFS system consists of an L-bit accumulator which occasionally overflows, providing a periodic sequence of numbers which represents phase. This phase is used to address a lookup table of amplitude values stored in a ROM and passed thorough a corresponding DAC to create a synthesised, analogue signal. The ROM consumes most of power of the system and several alternative architectures have therefore been investigated. [1, 2, 3]. 1.1. Spurious Frequencies A DDFS system is theoretically able to generate a pure synthesised signal with the phase and amplitude accurately defined by a digital input. However quantisation caused by ROM size reduction and non-idealities associated with the DAC cause the

generation of spectral power at unwanted frequencies, corrupting the output. This effect is measured as SFDR which is the difference in power between the synthesised signal and the next most powerful (unwanted) frequency in the output spectrum. Often commercial DDFS systems will quote ’narrow-band SFDR’ which assumes that a high-order low pass filter will be used to remove spurious frequencies. However a low power system must avoid the use of large filters hence Nyquist rate SFDR is quoted in this paper. The SFDR requirement of a Bluetooth system is
  [4]. 1.1.1. DAC Imperfections SFDR is an important figure of merit for comparison of high speed DACs that describes both the static and dynamic performance. While various techniques have been developed to reduce mismatch and improve the static performance, it has been more difficult to improve dynamic performance which rapidly degrades with frequency due to transient glitches. One solution is thermometer decoding which is able to reduce dynamic errors by ensuring that the minimum number of current cells switch simultaneously. Additionally the use of latches for all switching signals ensures that all cells switch synchronously and the use of differential switches allows reduction of the voltage required to switch current (Figure 2). However timing skew cannot be completely removed and state of the art RF CMOS DACs are limited to approximately
   SFDR. [5]. 1.1.2. Approximation Errors In a conventional DDFS system power conumption is minimised by reducing the size of the ROM. Common methods to reduce the size of the ROM are quarter wave symmetry, magnitude-phase difference and trigonometric approximations which segment the ROM into coarse and fine segments [6]. These techniques introduce approximation and quantisation errors in the output and hence their use is limited. Even in state of the art low power DDFS systems the ROM still consumes the majority of power [1]. Algorithmic methods such as CORDIC can be used as a replacement for the ROM by calculating the phase to amplitude conversion in digital circuitry [7, 8]. However the additional digital circuits increase the path delay and consume additional power. This paper introduces an interpolation DAC in the form of a nonlinear array of current sources which can be used to replace both the ROM and DAC, providing a low power DDFS alternative to a conventional DDS system. 2. ROM-LESS INTERPOLATION BASED DDFS The ROM may be replaced by using a nonlinear DAC to perform both phase to amplitude conversion as well as digital to analogue conversion. A nonlinear array of current cells is used to store the phase to amplitude information within the DAC. Using a trigonometric approximation Jiang and Lee [2] designed a ROM-less DDFS system consisting of 192 current cells. This system has an SFDR of better than
 at low synthesised frequencies (less than  ), which degrades to worse than
 at higher frequencies (up to   ). To reduce the number of current cells a technique is propsed which employs each current cell more efficently. 2.1. Non-linear Interpolation Consider the devices which form the differential current switch (Figure 2). If the two transistors in the differential switch are in saturation then the current flowing through one of them is:

!"$#&% ')(+*-,/.10
' ,325476+8
:9  ; =.
*-,/.10
A ,/2547687@ B @ (1) % ; Where ,3.10 is the input voltage, ,32C476 is a constant reference, .1 the constant current source and % the transconductance # @!DFEHL G1IKJ ,  !" #  and the parameter of the two, well matched switch transistors (M1 and M2). When *-,/.10
,325476 8 @ '; .=R % determines the minimum input voltage swing to fully switch the current to the output. condition M , .10
, 25476 MONQP

Smaller swings will steer part of the current to the output. Figure 3 shows the response of a single current cell. If the input voltage, ,3.S0 is swept up and down the output responds with a nonlinear shape. By choosing the input voltage range and transconductance of the current source carefully a surprisingly pure output signal with SFDR of -28dBc can be created from one DAC cell. However to comply with current communications standards, such as Bluetooth, the SFDR needs to be increased by using more devices. To increase the SFDR of the system more current cells must be used in order to improve

I out

Time Current Switch

V in

I out Wsw M1 L sw

V in

M2

Wsw L

V ref

sw

Time I bias

V bias

Wso L

so

Mbias

Current Source

Fig. 2. A single current cell based synthesizer. Iout Imax

large Ibias β small Ibias β −200mV

−100mV

0

100mV

200mV |Vin−Vref|

Fig. 3. Transfer function of a single current cell

the accuracy of the phase-to-amplitude conversion. A simple scheme to achieve a good approximation is to ensure that each current cell represents the change in amplitude corresponding to a change in phase, thus for a cosinusoidal wave:

K" *UTWVXY8 # ?Z\[ *^] . 8
_ ?Z\[ *^] .U`ba 8

(2)

;

Furthermore, it has been found that it is important to ensure that the slope ( .1 R % ) of the nonlinear transfer function remains constant across the current cells. The % of the switches in each current cell is therefore varied by changing the geometry of the switch transistors, c >Fd and e >Fd to keep this ratio constant.

2.2. Linear Interpolation

;

One of the critical decisions that must be made when designing a system is the value of ratio .=R % and the maximum differential input voltage that should ; be used. In particular the characteristics shown in Figure 3 indicate that by using a small voltage swing and a large .1 R % it might be possible to limit the circuit to the relatively linear part of it’s transfer characteristic. When using the linear part of the transfer characteristic only a small fraction of bias current in a cell is used to form the output. A system using linear interpolation will therefore use more power than an alternative system that exploits the whole, non-linear transfer characteristic of the differential switch. However a sinusoidal function is approximately linear over a large section of its argument and linear interpolation may give a better SFDR.

2.3. System Performance

' 0

current cells was investigated as thermometer decoding will be chosen as the switching The performance of systems of scheme in the final circuit. Table 1 presents the performance of Matlab emulations of both nonlinear and linear interpolation systems for increasing f . The performance is surprisingly good for a small number of current sources. Compared to Lees system which requires 192 cells to produce a signal that complies with the Bluetooth requirements of
 SFDR [2], only 16 cells are required here. Matlab was also used to investigate the tradeoff between power consumption and SFDR in this system of 16 current sources. The results of this investigation in Figure 4 clearly show the gradual degradation in SFDR as the power efficiency of the system is improved. These results show a rapid improvement in SFDR as the efficiency is reduced from  g to h+g . This g increase in power results in an improvement of i in SFDR. This initial rapid improvement in performance is followed by a slower improvement. However a system with j+g efficiency has an SFDR of better than
 k . Number of current cells 8 16 32 64 128

SFDR Non-linear interpolation - 37.4 dBc - 48.0 dBc - 53.9 dBc - 59.0 dBc - 61.5 dBc

SFDR Linear interpolation - 47.0 dBc - 59.6 dBc - 72.0 dBc - 84.1 dBc - 96.2 dBc

Table 1. Matlab results of using a linear interpolation compared to a non-linear interpolation.

−40 −42 −44 −46

SFDR

−48 −50 −52 −54 −56 −58 −60 0

0.2

0.4 0.6 efficiency (Iout/Ibias)

0.8

1

Fig. 4. Tradeoff between SFDR and efficiency (amount of current switched to the output) for a system with 16 cells

3. CIRCUIT DESIGN A 16 current cell array using interpolation and thermometer decoding has been designed in Ol j  T CMOS technology. A schematic of the system is shown in Figure 5. Only 16 current cells have been chosen as this is the minimum required to meet the most stringent SFDR requirement of the Bluetooth specification of -57dBc. This corresponds to the j+g efficiency point in the graph, which represents nearly-linear interpolation. A 20-bit accumulator is used to ensure frequency resolution of better than 1ppm, in line with the Bluetooth specification. The first 11 MSB bits are used to represent the phase to ensure that the system is not limited by phase resolution. In order to reduce the number of current cells half wave symmetry is exploited by using the MSB to take the 1s complement of the other phase bits using XOR gates. The next 4 bits are used to thermometer decode the nonlinear DAC. On its own this non-linear DAC would therefore be limited by phase errors arising from using only 5 phase bits to a SFDR of
j m . To ensure the overall system is limited by the phase-to-amplitude conversion, rather than phase quantisation, 6 more phase bits are used to create an analogue voltage that forms the input to the interpolating non-linear DAC.

1st MSB

20 bit Phase Accumulator for frequency resolution

10 bit XOR

next 4 MSB

10 bits

Conventional Non−linear DAC Thermometer Decoder Interpolation Non−linear DAC

6 LSB

Phase DAC (linear)

Sine Output

Vphase Analogue Phase Interval

9 Phase bits Discarded

Currents summed

2.1 Vphase 1.9

0

Π/16 time

Fig. 5. The architecture of a DDFS system based on analogue interpolation. 3.1. Conventional nonlinear DAC

;

In the conventional nonlinear DAC each current cell is biased by a common voltage ( , .= ) while the geometry of the current ; K" is different source, n s J-oFpqGSr in each cell encodes the phase to amplitude information ( .1 ). The resulting output current, J^oFpqG1r for each cell and represents the amplitude change when the input phase changes. Simulations show that, as expected, the performance of the nonlinear DAC alone is limited to
j by phase quantisation errors. The conventional nonlinear DAC uses a conventional thermometer decoder which uses row and column decoders and local logic within each cell to determine which cells are on and which are off [5]. In the conventional decoder, the local logic ensures that at any one instant current cells 1 to t contribute to the output. 3.2. Interpolation nonlinear DAC To improve the SFDR of the system the interpolation DAC provides an additional contribution to the output by current summation. The current source in each cell of this DAC is the same as the current source in the corresponding cell of the non-linear DAC. A simple interface for the interpolation DAC is to provide each cell with the same analogue representation of the phase ( ,+uvw74 ) as a the differential voltage input ( ,3.S0
,325476 ). This is created by a small linear phase DAC which converts the additional 6 phase bits into an analogue voltage. The use of the 6 additional phase bits from the accumulator, raises the #
 . This will ensure that the system performance phase quantisation limitation on SFDR to a possible
Wx: "v is limited by the the interpolation. The interpolation DAC requires the local " thermometer decoding logic to be modified to v identify only the * tzy{ 8 cell which should receive , uv74 . The * tyQ 8 cell can be determined by the XOR of two adjacent rows and two adjacent columns. If this cell is provided with the analogue input the output will increase by the partial amount that this cell is turned on causing interpolation between the phase values encoded in this cell and the previous cell. 4. CIRCUIT RESULTS 4.1. Preliminary Simulations Mixed signal simulation was employed with the accumulator represented by a behavioural Verilog model and the other digital ' A € model. When the accumulator is loaded with a phase word ' gates by their full analogue of 1 the system generates a synthesised € 0 frequency of |}-~S R  . With a clock frequency of  the SFDR was
 l  . The dominant spur was the harmonic suggesting that the SFDR is limited by amplitude quantisation as opposed to transients which would appear as a high frequency spur. 4.2. Frequency Performance As expected the SFDR decreases at higher frequencies when glitches become the dominate source of errors in the output. The SFDR requirement for Bluetooth is
  [4]. The results in Table 2 suggest that this system is better than required for clock frequencies of less than \   . This is significantly higher than the bandwidth required by Bluetooth.

| }-~S 10MHz 100MHz 500MHz 1GHz

circuit SFDR - 58.4 dBc- 58.0 dBc- 57.02 dBc - 54.35 dBc-

Table 2. Performance as |

}-~S

is increased

5. CONCLUSION An analogue interpolation technique for DDFS has been described which is able to synthesise signals with a spectral purity that complies with the Bluetooth specification using a small nonlinear DAC. This method also has applications in the generation of spectrally pure signals at low power for a wide range of other systems which require synthesis of spectrally pure systems at low power. 6. REFERENCES [1] A. Bellaouar, M. O’brecht, A. Fahim, and M. Elmasry, “Low-Power Direct Digital Frequency Synthesis for Wireless Communications,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 385–390, Mar. 2000. [2] J. Jiang and E. Lee, “A ROM-less Direct Digital Frequency Synthesizer Using Segmented Nonlinear Digital-to-Analog Converter,” in IEEE Custom Integrated Circuits Conference, 2001, pp. 165–168. [3] Bastos, J. and Marques, A. M. and Steyaert, M. S. J. and Sanasen, W., “A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC,” IEEE Journal of Solid State Circuits , vol. 33, no. 12, pp. 1959–1969, 1998. [4] Haartsen, J., C. and Mattisson, S., “Bluetooth - A New Low-Power Radio Interface Providing Short-Range Connectivity,” Proceedings of the IEEE, vol. 88, no. 10, pp. 1651–1661, Oct 2000. [5] A. Van den Bosch and M. A. F. Borreman, “A 10-bit 1-GSample/ s Nyquist Current Steering CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 315–324, Mar. 2001. [6] V. F. Kroupa, Direct Digital Frequency Synthesizers, IEEE Press, 1998. [7] Avanindra Madisetti, Alan Y Kwentus, and Alan N Wilson, “A 100MHz, 16-b Direct Digital Frequency Synthesizer with a 100dBc Spurious Free Dynamic Range,” IEEE Journal of Solid State Circuits , vol. 34, no. 8, pp. 1034–1043, August 1999. [8] R. Larson and S. Lu, “Interpolation Based Digital Quadrature Frequency Synthesizer,” in 13th IEEE Annual ASIC/SOC Conferernce Proceedings, 2000, pp. 48–52. 7. ACKNOWLEDGEMENTS This work is supported by funding from the Engineering and Physical Sciences Research Council, EPSRC.