Efficient Single-Pattern Fault Simulation on Structurally ... - CiteSeerX

Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs Jaan Raik, Raimund Ubar, Sergei Devadze, and Artur Jutman Tallinn University of Technology, Department of Computer Engineering, Raja 15, 12618 Tallinn, Estonia {jaan, raiub, serega, artur}@pld.ttu.ee http://ati.ttu.ee/english.php

Abstract. Current paper proposes an efficient alternative for traditional gatelevel fault simulation. The authors explain how Structurally Synthesized Binary Decision Diagrams (SSBDD) can be used for representation, simulation and fault modeling of digital circuits. It is shown how the first phase of any fault simulation algorithm: the fault-free simulation can be accelerated using this model. Moreover, it is pointed out that simultaneous to simulation on SSBDDs, the set of potential fault locations can be significantly reduced. In addition, algorithms for deductive and concurrent fault simulation on SSBDD models are introduced in the paper. While full implementation of the new SSBDD based algorithms needs to be carried out, the paper presents experimental data revealing the advantages of the proposed data structure in the fault simulation process.

1 Introduction Fault simulation is a widely used procedure in the digital circuit design flow. Most of the dependable computing and test design tasks (fault injection, test pattern generation, built-in self-test, etc.) rely on it. Thus, accelerating the subtask of fault simulation would consequently improve all the above-mentioned applications. In this paper we consider speeding up single-pattern fault simulation, for cases where pattern parallelism cannot be exploited (e.g. fault simulation with fault dropping). Traditionally, single-pattern fault simulation has been based on concurrent [1] or deductive [2] approaches. The research topic of fault simulation is very mature. A lot of approaches and efficient circuit models have been proposed in the past. In [3], the logic netlist is partitioned into supergates. In other works, fault simulation is carried out for circuit lines corresponding to the fanouts [4]. Current paper combines the two above ideas and goes much further by introducing the circuit model of Structurally Synthesized Binary Decision Diagrams (SSBDD) for fault simulation. SSBDD models allow considerably coarser partitioning than supergates. Furthermore, the approach allows to restrict the number of considered circuit lines to the fanout points while allowing to work on the higher level of abstraction, without any need to descend to simulation at the gate-level. Additional benefit of SSBDDs lies in the fact that it provides for a fault collapsing in the model itself without a need to specify the list of collapsed faults explicitly. In all the nodes of an SSBDD, both, stuck-at 0 and stuck-at 1 faults have to be covered M. Dal Cin, M. Kaâniche, and A. Pataricza (Eds.): EDCC 2005, LNCS 3463, pp. 332 – 344, 2005. © Springer-Verlag Berlin Heidelberg 2005

Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs

333

in order to guarantee 100 % fault coverage of the corresponding gate-level circuit. This means that, contrary to traditional gate-level collapsing techniques, it is not necessary to check if a fault at a circuit line is included to the collapsed list. This in turn results in time savings during the simulation process. The paper is organized as follows. Section 2 introduces the circuit model of SSBDDs for representing logic circuits. Section 3 explains how logic circuit simulation can be accelerated using SSBDDs. It is also shown how, simultaneously with SSBDD simulation, a restricted set of circuit lines with potential fault positions is extracted. In Section 4, SSBDDs are categorized by the nature of reconvergent fanout paths. Sections 5 and 6 present new, efficient fault simulation algorithms based on the deductive and concurrent approaches, respectively. Section 8 provides preliminary experimental results and Section 8 concludes the paper.

y 1 2 3 4 5 6

71 & a 7 72 b & & 73 c &

&

FFR

6

e

1

1

73

d &

&

5

y

2 0

a)

71

72

1-edges

0-edges

b) Fig. 1. a) Logic circuit and b) its SSBDD

2 Structurally Synthesized BDDs Structurally Synthesized Binary Decision Diagram (SSBDD) [5-7] is a planar, acyclic BDD that is obtained by superposition of elementary BDDs for logic gates. SSBDDs were first introduced in [5]. The most significant difference between the traditional BDD and the SSBDD representations is the method how they are generated. While traditional BDDs are generated by Shannon's expansions, which extracts the function of the logic circuit, SSBDD models are generated by a superposition procedure that extracts both, function and data about structural paths of the circuit. Another difference between the classical and the SSBDD approach is that in SSBDDs we represent a digital circuit as a system of BDDs, where for each fanout-free region (FFR) of the circuit a separate SSBDD is generated. An SSBDD G is a triple (M, X, Γ), where M is a set of nodes, X(m) is a function, which defines line variables labeling the node m and Γ(m, e) is a function, which gives the successor node of m with X(m)=e, e∈{0, 1}. The set of nodes M is divided into a set of nonterminal nodes MN={m0,..,mk-1} and to a set of terminals MT including 0- and 1-terminals, where M = MN ∪ MT.

334

J. Raik et al.

SSBDD models for gate-level digital circuits are created as follows. Starting from the output of the FFR (i.e. primary output or a fanout stem), logic gates are recursively substituted by their respective elementary BDDs. The procedure of superposition terminates in those nodes, which represent a primary input or a fanout branch. Figure 1 shows an FFR of a logic circuit with an output line y and its corresponding SSBDD. Note, that in the Figure 1 we have omitted the 0- and 1-labels at the edges, since their direction (down or right) replaces the corresponding label. Downward edges correspond to 0-edges and rightward edges correspond to 1-edges. 0- and 1-terminal nodes are illustrated by dashed lines and can be also omitted. In the latter case, exiting the BDD downwards corresponds to y=0 and rightwards to y=1, respectively. In addition, SSBDD nodes can also be labeled by inverted variables (e.g. 1 , 5 , and 7 2 in Figure 1). In order to consider simulation on SSBDD models, let us introduce some basic definitions. Let us denote Γ(m, e) by me. Then m0 is the successor of m for the value X(m) = 0 and m1 is the successor of m for the value X(m) = 1. By the value assignment X(m) = e, e ∈ {0,1}, we say that the edge between nodes m and me is activated. Consider a situation where all the variables X(m) are assigned by a Boolean vector Xt ∈ {0,1}n to some value. The edges activated by Xt form an activated path l = (m0, …, mT) from the root node m0 to one of the terminal nodes mT∈ MT. In [7], it has been proved that Gy represents a Boolean function y=f(X), and for all the possible vectors Xt∈{0,1}n a path l = (m0, …, mT) is activated so that y=f(Xt)= x(mT). Definition. High-path (low-path) is the path l = (m1, … , mL), where mi+1 = mi1 (mi+1 = mi0) for every i : 1 ≤ i < L. Definition. Node m in the SSBDD is a final node if m1 = 1-terminal and m0 = 0terminal. The following theorem characterizes some simple properties of SSBDDs. The proof for the properties is provided in [7]. Theorem 1. If G is an SSBDD, then:

1. G is a planar graph. 2. There exists a high-path from every node to the 1-terminal. 3. There exists a low-path from every node to the 0-terminal. 4. G has exactly one final node. 5. There exists a directed path through all nonterminal nodes. 6. For every pair of nonterminal nodes m1, m2 there exists a directed path from m1 to m2 or from m2 to m1. The above properties are the basis of the fault simulation acceleration ideas presented in Sections 3 to 5. Proof for the theorem has been published in [7]. Differently from traditional BDDs, SSBDDs support test generation for gate-level structural faults in terms of signal paths without representing these faults explicitly. Furthermore, the worst case complexity and memory requirements for generating SSBDD models for FFRs are linear in respect to the number of logic gates in the circuit, while for traditional BDDs the total storage space exceeds 2n bits for an n-

Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs

335

input combinational circuit [8]. Hence, SSBDDs for an arbitrary realistic-sized digital circuit can be generated very rapidly using only a small amount of computer memory.

3 Simulation on SSBDD Representations The main contributions of the paper is the study of fault-free simulation on SSBDD models. Fault-free simulation is the initial step of any fault simulation algorithm. The proposed algorithm is based on two basic properties of SSBDD models: 1) We previously saw that any Boolean vector Xt ∈ {0,1}n activates a path l = (m0, …, mT) from the root node m0 to one of the terminal nodes mT∈ MT in an SSBDD Gy. Thus, faults at nodes which do not belong to the main activated path l cannot influence the value of y calculated by Gy with the selected vector Xt. Furthermore, it can be shown that faults at only those nodes mi, where X(mi)=f(Xt) can potentially influence the output. We call such faults fault candidates or potential fault locations. 2) Logic value for every primary output line yO of a circuit with a Boolean vector Xt {0,1}n can be calculated by activating a path l = (m0, …, mT), where values X(mi) that do not correspond to primary outputs are calculated recursively. Obviously, faults in SSBDDs that are not traversed in such a recursion cannot change the value of yO. Properties 1 and 2 are illustratedin Figure 2. SSBDD model in that figure decribes a combinational circuit that consists of 7 FFRs, thus, represented by a model of 7 SSBDDs. The bold arrows indicate activated edges in each SSBDD simulated in a recursive manner starting from the SSBDD corresponding to the output line y. Recursive simulation starts from SSBDD Gy, traverses nodes a, c, d, f and then recursively simulates corresponding SSBDDs Ga, Gc, Gd and Gf. As a result, basing on the above properties, only 8 nodes out of 17 are identified as potential fault locations in this recursive simulation example. Note, that there was no need to simulate SSBDDs for b and e for finding the fault locations. However, in order to carry out fault propagation these graphs have to be simulated as well. These simple properties are also applied in Algorithm 1, which both, marks the nodes containing potential faults, and performs full fault-free simulation. As the first step of the algorithm, primary outputs of the design are recursively simulated on the SSBDD representation in order to identify SSBDDs in which faults could be activated. Then, the rest of the SSBDDs will be simulated. As the experiments carried out in Section 7 show, recursive simulation on SSBDDs is generally faster than simulation on the gate-level representations. What is more important, SSBDD simulation allows to considerably minimize the list of circuit lines to be regarded as potential faults in further fault simulation. The improvement achievable by the proposed SSBDD simulation is twofold: 1) SSBDD models provide implicit fault collapsing. The list of potential fault locations is reduced in average to 66 % of the uncollapsed one (See Section 7). While there exist more agressive fault collapsing approaches, this reduction has to be taken into account.

336

J. Raik et al.

2) As experiments in Section 7 show, Algorithm 1 narrows the circuit lines with potential fault locations to less than 40 % Algorithm 1. Fault-free simulation and identification of potential faults

FaultfreeSimulation() { for each primary output yO RecursivelySimulate(yO) end for for each SSBDD G if G is not marked as simulated then simulate G end if end for } RecursivelySimulate(y) { if y is a primary input then return the value of y. else mark Gy as simulated m = m0 while m ∉ MT if GX(m) is marked as simulated then m = mX(m) else e = RecursivelySimulate(X(m)) m = me end if end while end if }

y

a

b

c

d

a

x1

x2

c

b

x1

x3

d

x1

f

x2

x3

x4

e e

x2

f x2 y – primary output; a,b,c,d,e,f – internal signals (fanout stems); x1…x4 – primary inputs.

Fig. 2. Recursive simulation and fault candidate identification on SSBDDs

x4

Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs

337

In addition to that, only one of two stuck-at faults per location can be active at a time. Thus, the SSBDD simulation proposed in Algorithm 1 reduces the set of faults to be simulated to 0.66 . 0.4 . 0.5 = 0.13. In other words, in the fault simulation phase we have to operate with only 13 percent (!) of faults from the entire fault list.

4 Circuit Structure Analysis for SSBDD Fault Propagation Efficient fault simulation methods carry out fault simulation for the list of faults within a Fanout-Free Region (FFR) of a circuit and subsequently replace this list by the fault at the output of the FFR [4]. The fault at the fanout stem will then represent all the faults inside the corresponding FFR. This approach is very well supported in SSBDD models, where FFRs and SSBDDs have one-to-one correspondence. It provides for minimization of the size of the fault list, which is crucial in accelerating single-pattern fault simulation, since the speed of deductive and concurrent fault simulation algorithms greatly depends on the speed of set operations on fault lists. Current paper introduces additional means for improving fault simulation by applying structural analysis. We propose that the FFRs (i.e. SSBDDs) of the circuit should be categorized into three categories by the nature of reconverging fanout paths in them:

… fault y

… y fault

propagation

SSBDD

No … xn fanout

x1

… cone1

No overlap cone n

cone1

b)

SSBDD

x1

… xn fanouts! … No overlap cone n

primary inputs

primary inputs a)

propagation

propagation

SSBDD

x1

… y fault

… xn cones … overlap

cone1

cone n

primary inputs c)

Fig. 3. SSBDDs a) w/o reconvergencies, b) with reconvergencies of depth 1 and c) with complex reconvergencies of depth > 1

1. FFRs with no reconvergent paths; 2. FFRs with reconvergent paths with directly preceding FFRs (i.e. maximum reconvergence depth = 1); 3. FFRs with arbitrary reconvergencies (i.e. max. reconvergence depth > 1). Figure 3 explains that concept for an SSBDD Gy containing nodes with variables x1, ...., xn.

338

J. Raik et al. Table 1. Distribution of SSBDDs according to reconvergencies

circuit

total SSBDDs

c17 c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552

5 96 187 151 291 248 430 378 633 1488 920

SSBDDs w/o reconv. 5 95 123 133 187 180 391 344 529 1488 736

max reconv. depth = 1 0 1 64 18 40 68 24 31 91 0 160

max reconv. depth > 1 0 0 0 0 64 0 15 3 13 0 24

In the following Sections we will present a fault simulation algorithm that takes advantage of the above-mentioned classification. Fault propagation through an SSBDD with no reconvergencies can be done simultaneously to fault activation. In order to propagate faults through an SSBDD with reconvergent paths with maximum depth 1, faults in variable values of X(m) have to be additionally simulated (See Algorithm 2). Finally, for SSBDDs with a more complex reconvergency structure we can resort to the deductive fault propagation method described in Algorithm 3. Table 1 shows such classification of SSBDDs according to reconvergency properties for the ISCAS’85 circuits. As we can see, in most of the circuits there are no reconvergencies with depths exceeding one FFR. The average percentage of such FFRs is only 2.5 %. The only circuit with a large portion of complex reconvergencies is c1355, where 22 % of all the FFRs fall to the third category.

5 Concurrent Fault Simulation Concurrent fault simulation [1] can be viewed as an extension to event-driven fault simulation. Lists of activated faults are propagated concurrently through the circuit and faulty circuit events are simulated. In the following, a concurrent fault simulation algorithm for SSBDD representations is proposed. Let us start with notations. For each SSBDD Gy the following fault simulation algorithm is implemented. First, all the nodes belonging to M1 are traversed. If a node corresponds to a line of fanout reconvergence then the variable labeling the node is changed to a faulty value and Gy is simulated. Otherwise, fault is injected at the node and simulation is performed. Fault injection and simulation is used also for determining the faults activated in Gy in order to compute the set A. If A will be an nonempty set then after the simulation y stuck-at-⎤ f(Xt) will represent all the faults in A because it is dominated by them for the vector Xt.

Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs

339

Algorithm 2. Concurrent fault simulation on SSBDDs.

ConcurrentFaultSimulation() { R = ∅, A = ∅ for each m ∈ M1 FaultSimulateNode(m) if S(m) contains faults reconverging in m then X(m) = ⎤ X(m) simulate Gy if the faulty value of y differs from the fault-free one then R = R ∪ S ( m) end if X(m) = ⎤ X(m) else if fault at node m is mrked as active inside the FFR R = R ∪ S ( m) end if end if end for } FaultSimulateNode(m) { follow the activated path l = (m⎤ X(m), ..., mT) if(X(mT) = ⎤ f(Xt)) then A = A ∪ { m-stuck-at-⎤ X(m) } mark fault at node m as active inside the FFR end if } Notations: • MT - set of terminal nodes (i.e. 0-terminal and 1-terminal). • MN - set of nonterminal nodes. • M1 - set of nonterminal nodes at the main activated path lmain, where { m∈M1⏐ X(m)=f(Xt) } • m’= mX(m) m”= m⎤ X(m) • S(m) – fault list propagated to m from previous SSBDDs. • A – the set of faults active in the FFR. • R – the set of faults propagated to circuit line corresponding to the FFR output y.

Note, that the method described by Algorithm 2 can only be applied to graphs, whose reconvergencies are of depth 1 or less (See Section 3). For SSBDD graphs with no reconvergent fanout paths, the check for reconvergencies can be omitted.

340

J. Raik et al.

6 Deductive Fault Effect Propagation In deductive fault simulation [2], signal values for the fault-free circuit are computed and faults that will cause each line to have a value different from its fault-free value are deduced. In the following algorithm the computation is performed on SSBDDs based on the properties stated by theorems 1 and 2. Notations: • MT - set of terminal nodes (i.e. 0-terminal and 1-terminal). • MN - set of nonterminal nodes. • M1 - set of nonterminal nodes at the main activated path lmain, where { m∈M1⏐ X(m)=f(Xt) } • m’= mX(m) m”= m⎤ X(m) • S(m) – fault list propagated to m from previous SSBDDs. • L(m) – temporary fault list for calculating the propagated faults R. • R – the set of faults propagated to circuit line corresponding to the FFR output y. Algorithm 3. Deductive fault propagation on an SSBDD.

DeductivePropagation() { R =Ø for each m∈MN L(m)=Ø end for for each m∈MN if m∈M1 then if m”∉ MT then L(m”)= L(m”) ∪ S(m) else R=R ∪ L(m) end if else if m’∉ MT then L(m’)=L(m’) ∪ (S(m) \ L(m)) else if X(m)=⎤ f(Xt) then R= R ∪ L(m) end if if m” ∉ MT then L(m”) =L(m”) ∪ (S(m) ∩ L(m)) else if x(m)= ⎤ f(Xt) then R= R ∪ L(m) end if end if end for }

Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs

341

The task of the presented deductive fault propagation algorithm is to calculate the set of faults R propagated through the SSBDD Gy by a given input vector Xt and S(m). Note, that the proposed algorithm does not include fault activation. This can be carried out in the similar manner as described in Algorithm 2. One of the main shortcomings of the deductive approach is relatively timeconsuming set operations on long fault lists. However, as experiments show, SSBDD models allow to significantly reduce the list of faults to be considered. Furthermore, as circuit structure analysis presented in Section 4 showed the number of graphs where deductive fault simulation is usually very small. Finally, Algorithm 4 combines the ideas proposed in this paper into a single fault simulation approach.

7 Experimental Results A useful property of SSBDDs is its ability to provide fault collapsing in the model. While in the gate-level descriptions we model stuck-at faults at the interconnections between the gates, in SSBDD representations the faults are present at nodes. For example, stuck-at-0 fault at a node is modeled with the 0-edge of the node being constantly activated, regardless of the value of the variable labeling this node. Each SSBDD node represents a distinct path in the corresponding fanout-free circuit. By testing all the SSBDD node faults we will consequently test all the signal paths in the circuit and thus all the single stuck-at faults. This ability of SSBDDs to implicitly model logic level stuck-at faults is a very important property, which distinguishes it from other classes of BDDs. Algorithm 4. Fault simulation on SSBDD models.

SSBDDfaultSimulation() { Recursively simulate SSBDD model and identify the list of potential faults // Algorithm 1 for each SSBDD G if G has no reconvergent paths then Simultaneous fault activation and fault propagation // See Algorithm 2! else if G has reconvergent paths with max. depth = 1 ConcurrentFaultSimulation() // Algorithm 2 else Fault activation in SSBDD // FaultSimulateNode in Alg. 2 DeductivePropagation() // Algorithm 3 end if end for }

342

J. Raik et al.

Table 2 compares the number of uncollapsed faults, the number of standard collapsed faults and the number of SSBDD faults in the ISCAS’85 benchmark set. As we can see that reduction provided by collapsing in the SSBDD model is about 1.5 times. While there exist more aggressive fault collapsing approaches the advantage of the SSBDD based collapsing over the traditional one is that it allows us at the same time to rise to a higher abstraction level of circuit modeling. In the traditional case we would only minimize the number of faults but would still be working at the level of logic gates. Table 3 presents the fault-free simulation results, which were carried out to evaluate the speed of SSBDD simulation and its ability to restrict the number of simulated faults (See Algorithm 1). The simulation algorithms were compiled by GNU C compiler using –O option and experiments were run on a 366MHz SUN Ultra60 server using SUN Solaris 2.8 operating system. Table 2. Number of collapsed and SSBDD faults in ISCAS85 circuits

circuit c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552

Faults 1550 2194 2788 4150 5568 8638 9728 11590

collapsed 942 1574 1879 2747 3428 5350 7744 7550

SSBDD 994 1618 1732 2626 3296 5424 7744 7104

Table 3. SSBDD simulation experiments

circuit

vectors

c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552

100000 10000 10000 10000 10000 10000 10000 1000 1000 1000

Gate SSBDD simulation, simulation, recursive, SSBDD density, % s s s 3.76 1.56 2.12 66.45 1.06 0.33 0.55 94.74 0.70 0.27 0.44 89.83 0.97 0.58 0.89 93.73 1.28 0.50 0.75 81.13 2.13 0.85 1.16 80.55 2.74 0.87 1.21 76.38 0.42 0.17 0.21 67.45 0.49 0.34 0.52 100 0.57 0.25 0.34 79.82

node density, % 30.80 46.84 44.74 52.33 37.54 38.09 30.27 27.92 58.30 37.37

Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs

343

The second column of the table shows the number of simulated vectors. The third column shows the time spent by gate-level simulation, in seconds. The fourth column presents the time needed to simulate all the SSBDDs in the model. The fifth column shows the time for recursive SSBDD based simulation as shown in Algorithm 1. The run times in the fifth column include identification of the potential faults to be simulated.

Fig. 4. Fault simulation speed-up and average SSBDD/gate ratio

The two last columns reflect the ability of recursive SSBDD simulation to reduce the set of considered faults. ‚SSBDD density’ shows the percentage of SSBDDs traversed by recursive simulation from the total number of FFRs. The column ‚Node density’ the percentage of SSBDD nodes identified as fault candidates by Algorithm 1. The average SSBDD density was 80 % and node density 40 %. In the worst case, c6288 (a parallel multiplier), SSBDD density was 100 %, i.e. all the SSBDDs were traversed by recursive simulation, and the node density was 58.3 %. For all the benchmarks except c6288 Algorithm 1 performed faster than the fault-free simulation at the gate-level. Figure 4 presents comparison of implementation of the event-driven fault simulation algorithms on SSBDDs and logic gates. We can see from the Figure that the speedup of SSBDD fault simulation (‘Fault Simulation’) ranges from 2 to 7 times and that it is well correlated with the average number of logic gates in an FFR (‘g/m ratio’).

8 Conclusions and Future Work The paper proposes an efficient alternative for traditional gate-level fault simulation based on Structurally Synthesized Binary Decision Diagrams (SSBDD). It is shown how fault-free simulation can be accelerated using this model. Moreover, it is pointed out that simultaneous to simulation on SSBDDs, the set of potential fault locations

344

J. Raik et al.

can be significantly reduced. Experiments show that this reduction is in average 13.3 % from the total fault list (i.e. 26.6 % of the circuit lines). In addition, new algorithms for deductive and concurrent fault simulation on SSBDD models are introduced in the paper and structural analysis allowing a trade-off of these algorithms is performed. As a future work we plan to compare the speed of the proposed algorithm to existing state-of-the-art commercial software. For additional speed-up we plan to implement dynamic node reordering [9] to the SSBDD models to be simulated.

Acknowledgements This work was supported by EU projects IST 2000-30193 REASON, IST-2001-37592 eVIKINGS II, Estonian Science Foundation grants 5637, 5649, 5910, and by Enterprise Estonia Competence Center of Mission Critical Embedded Systems (ELIKO).

References 1. E. G. Ulrich, T. Baker, “Concurrent Simulation of Nearly Identical Digital Networks”, Computer, vol. 7, pp. 39-44, Apr. 1974. 2. D. B. Armstrong, “A Deductive Method for Simulating Faults in Logic Circuits”, IEEE Trans. Comput., vol. C-21, pp. 464-471, May 1972. 3. S. C. Seth, L. Pan, V. D. Agrawal, “Predict-Probabilistic Estimation of Digital Circuit Testability”, Dig. Papers FTCS-15, June 1985, pp. 220-225. 4. K. J. Antreich, M. H. Schulz, “Accelerated Fault Simulation and Fault Grading in Combinational Circuits”, IEEE Trans. on CAD, vol. CAD-6, no. 5, Sept. 1987, pp. 704-712. 5. R. Ubar. “Test Generation for Digital Circuits Using Alternative Graphs”, in Proc. Tallinn Technical University, 1976, No.409, Tallinn TU, Tallinn, Estonia, pp.75-81. 6. R. Ubar, “Test Synthesis with Alternative Graphs,” IEEE Design & Test of Comp. Spring 1996, pp. 48-59. 7. A. Jutman, A. Peder, J. Raik, M. Tombak, R. Ubar. Structurally synthesized binary decision diagrams. 6th International Workshop on Boolean Problems, pp. 271-278, Freiberg, Germany, Sept. 23-24, 2004. 8. H.-T. Liaw, C.-S. Lin, “On the OBDD-representation of general Boolean functions”, IEEE Trans. on Computers, Vol. C-41, No. 6, pp. 61-664, June 1992. 9. R. Ubar, T. Vassiljeva, J.Raik, A.Jutman, M. Tombak, A. Peder. Optimization of Structurally Synthesized BDDs. Proc of the 4th IASTED International Conference on Modelling, Simuation, and Optimization MSO 2004, pp. 234-240, Kauai, Hawaii, USA, Aug. 17-19, 2004.