Design, Fabrication and Characterization of Γ Gate GaN HEMT for High-Frequency/WideBand applications. Marco Peroni1, Paolo Romanini1, Alessio Pantellini1, Antonio Cetronio1, Luigi Mariucci2, Antonio Minotti2, Giovanni Ghione3, Vittorio Camarchia3, Ernesto Limiti4, Antonio Serino4, Alessandro Chini5. (1)
Selex Sistemi Integrati S.p.A., Engineering Division; Via Tiburtina, Km 12,400; 00131 Roma, Italy; e_mail:
[email protected] (2) CNR- Istituto di Fotonica e Nanotecnologie, Via Cineto Romano 42, 00156 Roma, Italy. (3) Politecnico di Torino, Department of Electronics, Corso Duca degli Abruzzi 24, 10129 Torino, Italy. (4) Electronic Engineering Department, University of Roma Tor Vergata, 00133 Rome, Italy. (5) Dipartimento di Ingegneria dell’Informazione - Università di Modena e Reggio Emilia, Via Vignolese 905, 41100 Modena, Italy. Abstract We report a study on AlGaN/GaN HEMT performances optimization by using Γ-Gate technology. The influence of the adopted technological parameters, like the field plate extension, through the analysis of small/large signal RF performances, including the comparison of the obtained results with conventional LG=0.5µm gate-length devices is investigated. The introduction of a field plate overhang of 0.2µm over the underlying SiN layer at the drain side of the gate foot, has brought approximately to a factor two improvement on the device breakdown voltage. On the other hand, a reduction of RF gain has been observed in presence of the FP metallization, especially if longer than 0.2µm, even though such negative effect is less significant if drain bias higher than 30V has been applied. Keywords: AlGaN/GaN high-electron mobility transistors (HEMTs), field plate, gate current leakage
1. INTRODUCTION AlGaN/GaN high-electron mobility transistors (HEMTs) are excellent candidates for high-power and highfrequency applications due to their superior material properties. As a result of improved material growth and processing technologies, microwave power densities have been demonstrated in GaN HEMTs that are five to ten times greater than that of corresponding GaAs-based devices. This is mainly due to the wide band-gap, the high peak saturation velocity of the Gallium Nitride semiconductor and to the charge induced by the spontaneous and piezoelectric field of AlGaN/GaN heterostructure, to develop HEMTs exploiting the channel formed by the two dimensional electron gas (2DEG) induced at their interface. In facts the obtained very high sheet carrier concentration (typically 1×1013 cm-2) increase the device current handling capability about five times higher than in AlGaAs/GaAs HEMTs. Moreover the critical breakdown electric field is about one order of magnitude with respect GaAs (0.4 MV/cm), making feasible devices with very high Drain to Source Voltage Bias.These superior performances will result in simplifying the design and fabrication of monolithic microwave integrated circuits (MMIC) allowing the reduction of the chip size and simplifying device impedance matching. However, in spite of these promising performances AlGaN/GaN HEMT devices technology suffers of various limiting factors related both to the material growth and fabrication processing. In particular surface and bulk traps affects devices Drain current slump under pulsed and RF operation, dislocations and defects at the Gate junction induces Reverse bias current leakage and soft breakdown, poor 2DEG confinement can enhance short channel effects etc.The main issues that must be taken into account concern drain current collapse, knee voltage walkout, short channel and soft breakdown effects and strongly limit the RF current/voltage swing and consequently output power and PAE of the device. While applying high bias voltage such detrimental effects are all enhanced, in particular when sub half micron gate length is used for very high frequency/wide band application. For this reason several papers report on the benefical effects on the mentioned issues obtained by the use of a Field Plate (FP) Gate topology trough the reduction of the electric field in the device channel [1] - [5]. The solution of a field plate metallization intimately connected to the gate electrode, providing a “T” or “Γ” shape to its cross section, has been commonly used as one of the preferred solution for sub-half-micron footprint gate geometry, when devices operating for frequency applications above 10GHz must be attained. In this work we study different Γ-Gate topologies applied to AlGaN/GaN HEMT. This comparison has been carried out by applying different gate fabrication technologies on the same substrate in order to evaluate the influence of different gate geometries. The obtained characterization results of DC and RF (small and large signal) measurements will be illustrated and interpreted trough numerical simulations.
2. DEVICE DESIGN AND FABRICATION GaN HEMTs have been fabricated on both Sapphire and SiC substrate where an 22nm AlGaN/GaN layer were grown over a GaN layer of 1.4 µm, as buffer layer. Device fabrication technology is based on a mix and match approach by using both Stepper and Electron Beam Lithography (EBL). Drain and Source ohmic contacts were obtained by metal deposition (Ti/Al/Ni/Au) and subsequent high temperature Rapid Thermal Processing (over 850°C). Finally, the wafer surface is passivated using SiN plasma-enhanced chemical vapor deposition (PE-CVD) for surface protection, while the active device isolation is achieved by means of fluorine ion implantation. SiN layer deposition has been optimised in order to minimize the carrier trap concentration at the interface with the semiconductor. Gate formation is based on a double step EBL process: first we define the gate foot with L G = 0.25µm, by opening the SiN layer by Reactive Ion Etching, second we define the Γ-gate Field Plate “Head” partially overhanging the SiN layer at the Drain Side, as shown in the channel section schematic picture of the device shown in Fig. 1. The overhanging length be identified in the following of the paper as the Field Plate length LFP. The 70 nm thickness has been chosen to guarantee a reproducible and high yield footprint definition (LG=0.25μm).
Fig. 1. Schematic Channel section of the GaN HEMT In order to better distinguish geometrical and technological aspects from the material properties influence, discrete devices has been manufactured with different gate fabrication technologies on the same substrate. In particular, devices with Γ-Gate geometry has been fabricated with different LFP length, namely with LFP =0.2 and 0.4 µm, as well as standard 0.5 µm I-gate device. In Fig. 2 FIB images from the Gate section are reported. In addition to discrete RF devices, Process Control Monitor (PCM) test structures has been also fabricated (like TLM, Schottky diodes, metallization meanders etc.), and in particular Metal Insulator Semiconductor FATFETs has been obtained by means of the deposition of the Gate metallization on the 70nm SiN layer. Said structure has allowed a control of the 2DEG charge modulation channel below the field plate metallization in the Γ-Gate devices, and in particular the measured MISFET pinch-off voltage of VMISPO=-26V is an indication that the field plate metallization can induce a voltage drop broadening at the Drain side in the device channel, reducing the breakdown voltage of the device, when VDG≥VMISPO. This is an indication that the adopted 70nm SiN thichness allow the desired protection from eccessive Gate leakage and/or soft breakdown effects that, as often obswerved, occurs at reverse bias voltager higer than 30V [2]. The obtained experimental evaluation of the correlation between devices figures and Gate geometry, like device breakdown and RF gain, and the compared analysis obtained by means of numerical simulations, has allowed the achievement of an optimization tool on the basis of the developed technology, as will be discussed in the next section.
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b) Fig. 2. Γ gate section with a) LFP =0.2 and b) LFP 0.4 µm
3. SIMULATIONS AND EXPERIMENTAL RESULTS A drift-diffusion 2D Numerical Simulation GaN HEMT model (based on Atlas-Blaze Silvaco Iternational Inc. software) has been developed basing on PCM material and process characterization to evaluate the effects of device geometry on DC and RF small signal performances, as well as to estimate the distribution of physical parameters (like the Electric field, current density, electron concentretion etc.) within the channel section area of the devixce. The estimated the breakdown voltage of the device by extracting the electric field peak (3.6MV/cm). As shown for a non-FP device this value is obtained at VGS=-10V and VDS=100V (Fig. 3a). The breakdown voltage rapidly increases for FP overhangs up to 0.2μm (VB=150V) and then slowly increases for further FP extension. In fact such configuration, for a fixed Gate-Drain voltage, permits a distribution of the electrical field over a wider area under the Gate at the drain side as shown in Fig 4. In Fig. 3 is also shown the reverse Gate current leakage results for two devices realized on the same wafer: one with standard 0.5µm I-Gate technology (Fig. 3b), the second with Γ-Gate (LFP=0.2μm and 70nm thick SiN) (Fig. 3c). Similar results are obtained in the case of LFP=0.4μm. The measurements were performed increasing maximum reverse voltage, in order to evaluate the presence of “soft breakdown”, i.e. the effect of irreversible reverse current leakage degradation consequent to high bias voltage stress). The introduction of a field plate overhang of 0.2µm over the underlying SiN layer at the drain side of the gate foot, has brought approximately to a factor two improvement on the device breakdown voltage (considered as catastrophic breakdown as well as the “soft breakdown”) as predicted by simulations. Gate: LG=0.25µm;LFP=0.2µm 70nmSiN
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From pulsed IV measurements using different quiescent bias points, as shown in Fig. 5, limited Drain current slump on high voltage biased devices has been observed on the fabricateddevices, as well as a little influence of the FP presence and the Field Plate length LFP has been observed. This positive result can be associated to low trap concentration at the semiconductor surface due to SiN optimization and good native material properties, as well as the electric field reduction obtained by FP presence is not so critical on Drain current collapse in case of a little surface trap presence, whose concentration has been estimated from numerical simulations lower than 2x1012cm-2, by considering the measured MIS FATFET pinch off V MISPO as well as the SiN and AlGaN dielectric constants and the CV measured 2DEG concentration. LG=0.25µm LFP=0.2µm LG=0.25µm LFP=0.4µm
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RF simulations and measurements were performed in order to investigate the effect of different FP geometries on RF gain at various biasing conditions. We can see that by biasing the device at VDS=10V Drain voltage of and Drain current ID=30%IDSS (Fig. 6 A and B), device with 0.5µm I-Gate technology has similar gain with respect to 0.25µm ΓGate with LFP = 0.2µm, in spite of the factor two of the footprint length, while MAG/MSG values results 2 dB higher in when a field Plate lenght LFP=0.4µm is adopted. The negative effect on RF gain observed in presence of the FP metallization, on the other hand results less significant if drain bias higher than 30V is been applied: as shown in Fig. 6C, the measured small signal Gain at ID=30%IDSS and VDS=30V, Γ_Gate MSG increases +3÷4dB with respect VDS=10V, and LFP=0.4µm device gain results closer to what obtained with LFP=0.2µm. Numerical simulations predict the effect of Γ-Gate geometry the observed trends on small signal RF gain at various biasing conditions, as shown in Fig. 7, since as observed experimentally small signal gain differences at VDS=30V with respect VDS=10V are more pronunced in the case of Γ-Gate FP and longer LFP. The map of the electron concentration distributions across the HEMT channel section obtained with the simulation tool, provides a key of interpretation for the achieved RF results, since 2DEG is depleted below the FP metallization at VDS=30V (Fig.8)while it is not in the case of VDS=10V, ad this can be associated to an higher Drain to Gate capacitive coupling in case of lower VDS and/or higher LFP. Results on Load pull measurements to investigate power performances at AB calss operation, are reported in Fig. 10. The tested devices has 1mm Gate periphery, and GaN HEMT LG=0.25µm/LFP=0.2µm Γ-Gate performances has been compared with LG=0.5µm I-Gate devices fabricated on SiC substrate. Conventional I –Gate 1mm device Drain bias has been limited to VDS=15V to avoid excessive Gate leakage issues consequent to soft breakdown effects, while for Γ-Gate a Drain bias voltage of VDS=30 Volt has been possible thanks to FP protection. The advantage of Γ-Gate superior Drain bias voltage results not only in higher output power (POut=4.1Watt vs. POut=2.8Watt at 3dB compression), but also in higher linear Gain of 12.7dB Vs. 10.8dB at 10GHz), as predicted by numerical simulation analisys.
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Fig. 6. Small signal gain measurements on device 2x50µm Γ-Gate Vs. I-Gate a) Sapphire substrate: VDS = 10V, 30% Idss b) SiC substrate: VDS = 10V, 30% Idss c) SiC substrate: VDS = 30V, 30% Idss
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Fig. 7. RF Gain simulation results distribution at V DS=10V and 30V a) 0.5µm I-Gate Vs b) 0.25µm Γ-Gate with 0.2µm overhang c) 0.25µm Γ-Gate with 0.4µm overhang.
Fig. 8. Simulated charge distribution at VDS=10V and 30V
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b) Fig. 9. Large signal Load Pull measurements results at 10GHz (1mm Gate periphery) and a) 0.25µm Γ-Gate LFP = 0.2µm (VDS=30 Volt and ID=30%IDSS) b) 0.5µm I-gate (VDS=15 Volt and ID=30%IDSS)
4. CONCLUSIONS An optimization of AlGaN/GaN HEMT performances by using Γ-Gate technology is presented. An analysis of devices performances and the associated typical limiting factors related to AlGaN/GaN HEMT power devices (like drain current collapse and breakdown) has been obtained trough the comparison of devices fabricated on the same substrate with different Field-Plate geometries as well as the numerical simulation tool. For a Field-Plate overhang length of 0.2µm we obtained very high breakdown devices (about 180V) and an output power of POut=4.1Watt at 3dB compression and PAE=41% with linear Gain of 12.7dB at 10GHz. ACKNOWLEDGMENTS This work was supported by the E.U. I.P. Project KORRIGAN REFERENCES [1] Vipan Kumar, Guang Chen, Shiping Guo, and Ilesanmi Adesida, “Field-Plated 0.25-μm Gate-Length AlGaN/GaN HEMTs With Varying Field-Plate Length,” IEEE Transactions on Electron Devices, Vol. 53, No. 6, June 2006 [2] Shreepad Karmalkar, Michael S. Shur, Grigory Simin, Senior Member, M. Asif Khan, “Field-Plate Engineering for HFETs”, IEEE Transactions on Electron Devices, Vol. 52, No. 12, December 2005 [3] Huili Xing, Y. Dora, A. Chini, S. Heikman, S. Keller, and U. K. Mishra, “High Breakdown Voltage AlGaN-GaN HEMTs Achieved by Multiple Field Plates”, IEEE Rlectron Device Letters. Vol. 25, No. 4, April 2004 [4] Yuji Ando, Akio Wakejima, Yasuhiro Okamoto, Tatsuo Nakayama, Kazuki Ota, Katsumi Yamanoguchi, Yasuhiro Murase, Kensuke Kasahara, Kohji Matsunaga, Takashi Inoue, Hironobu Miyamoto, “Novel AlGaN/GaN Dual-Field-Plate FET With High Gain, Increased Linearity and Stability”, Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International [5] J. S. Moon, Shihchang Wu, D. Wong, I. Milosavljevic, A. Conway, P. Hashimoto, M. Hu, M. Antcliffe, and M. Micovic “Gaterecessed AlGaN-GaN HEMTs for high-performance millimeter-wave applications”, IEEE El. Dev.Lett., 26, NO. 6, 348 (2005)
