A High Data Rate X-Band Transmitter with an Efficient Solid State Power Amplifier Dr.Ozlem A. Sen(1), Celal Dudak(1), Hacer K. Sunay(1),A. Neslin İsmailoglu(1), Tunahan Kırılmaz(1) (1)
TUBITAK-BILTEN ODTU kampusu, Inonu Bulvari, 06531Ankara, TURKEY Email:
[email protected],
[email protected] [email protected] [email protected] [email protected]
INTRODUCTION Low earth orbit (LEO) satellites have large areas of applications, including earth observation, disaster monitoring, wireless communication, multimedia applications, and hyperspectral imaging. This increases the demand for high data rate transmitters for LEO satellites. In this study, the work on a transmitter that is planned to have a data rate up to 100Mbps with BPSK/QPSK/OQPSK modulation and 7W (38.5 dBm) output power at 8.2 GHz center frequency is summarized. This output power satisfies the link budget for a LEO satellite, having patch antenna structure and 650 km altitude orbit, with 40° minimum elevation angle, utilizing required source-channel coding schemes in baseband and a 3.7m. dish at the ground station with BER performance of 10-6. It is also possible to decrease the data rate in order to communicate with mobile ground station with small antennas. In addition to high data rate property, a satellite communication system requires high-efficiency and simple transmitters, without sacrificing linearity depending on the modulation scheme. The power consumption of the transmitter is mainly determined by power amplifiers, which should be improved according to these constraints. For this purpose, a two stage narrowband power amplifier with a total gain of 20.5dB and output power of 38.5 dBm at 8.2 GHz with a bandwidth of 95 MHz (Gain flatness is ± 0.6 dB in 8.17-8.265 GHz band) is designed, realized and measured. The transistors are biased for class AB operation and obtained an efficiency of 35% in the second stage, 17% in the first stage and overall efficiency of 26%. Main advantage of the second stage is that the current driven from drain bias source decreases when the input current decreases. This is obtained using a specific matching circuitry at the output of the transistor that shows desired impedances at the fundamental and harmonic frequencies. With this matching circuitry, gate current increases with the increased input power and actual gate voltage decreases (due to the series resistance in the gate bias circuitry), so the drain current of the transistor increases with the input power. At 32.8 dBm output power, the total current from 8.8V supply is 2.1 A; whereas at 38.7 dBm output power, total current reaches up to 3.1 A, without any change in predetermined bias circuitry and voltages. By this way, the efficiency degradation in the low input power values is limited. Another important point of this system is, in the design process, commercial of the shelf components are used. In the following sections, first the system design of the transmitter is given, followed by the realization of this novel power amplifier and finally the measurement results of the completed parts are given with the related discussions.
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SYSTEM DESIGN For satellite applications, it is very important to have simple and reliable systems. For this purpose, a simple heterodyne transmitter structure with the given block diagram in Fig.1 is chosen. Besides, all the baseband and modulation processes are summarized in Fig.2.
Patch Antenna
MODULATOR
Output=7 Watt
RF=8200 MHz
IF=2210 MHz
25/50/100 Mbps
POWER AMPLIFIER
UPCONVERTER
Fig. 1 Block diagram of transmitter The modulation scheme of the transmitter can be chosen as BPSK, QPSK or OQPSK. In addition to BPSK/QPSK/OQPSK modulation scheme choice, the transmitter will have three different data rates, 25Mbps, 50 Mbps, and 100Mbps which will be chosen according to the needs and facilities of the ground station. For example, for mobile ground stations, it is possible to download the signal at low data rates with a small antenna. With 100Mbps, a state of the art technology will be demonstrated and the demand for high data rates will be satisfied. As encoding scheme, a nested structure is chosen which combines powerful parts of the subcodes. As the outer code Reed Solomon with (255,223,33)256 is used for error correction coding for burst errors due to multipath fading. As inner code a convolutional code with rate (1/2) is utilized, which provides correction for random errors in channel with a moderate bandwidth expansion. Between inner and outer codes convolutional interleaver with depth 5 is used. This concatenated encoder structure is also recommended by CCSDS [10]. Also, nonlinear turbo coding will be an alternative choice for future applications. LVDS I
25/50/100 Mbps Data
Spacewire Node + Controller
Reed Solomon Encoder (255,223,33) (CCDSC Recommended)
Interleaver
QPSK/BPSK/ OQPSK Bit/Symbol Mapping
Convolutional Encoder
Pulse Shaping
LVDS
D/A Converter
LVDS Differential Amplifier RF Modulator
LVDS Q
Pulse Shaping
LVDS
D/A Converter
2210 MHz
Differential Amplifier LVDS
FPGA (Xilinx)
Fig. 2 Block diagram of baseband and modulation processes Appropriate nested-interleaving and scrambling techniques are used to minimize DC component of the signal, to improve the timing recovery at receiver; and hence effectively making the bursty channel appear like a random error channel to the decoder. Then, output is pulse shaped by an FIR-RRC (finite impulse response root raised cosine) filter, which is anticipated to dominate the size of the design in the baseband process, planned to be implemented digitally in Xilinx Virtex-II FPGA. Both number of taps and bit resolution (number of bits that identifies an amplitude level) drive the complexity/size of the filter. Simulations are performed in order to optimize/minimize former values, trading-off out-of-band spectral response and data-rate. 64 taps and 10 bit resolution is the best trade-off number, meeting SFCG spectral mask and allowing 100 Mbps data rate whose BER performance will also be a future work. Additionally, for reliability against Single Event Upset logic errors in FPGA configuration, Xilinx "Readback" Capability is used. For necessity of reconfiguration, a CRC checksum based upon all the configuration bits that have been read back is generated and this CRC is compared with the expected checksum.
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As a result, Fig.3 shows spectrum analyzer (SA) output of RF modulator in Fig.2, which is a 50 MHz sinewave in BPSK mode and marker shows fundamental signal. Differential characteristic of modulator is evident in that even order harmonics of digitally produced sinewave are suppressed. Additionally, carrier suppression must, also, be enhanced in Fig.4, where 100 MHz RRC filtered QPSK signal is given.
Fig.3 50 MHz sinewave spectrum analyzer (SA) output of RF modulator
Fig.4 100 MHz RRC filtered QPSK signal
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Signal is direct quadrature modulated at 2210 MHz as the IF stage (Fig. 5). Then, it is filtered and amplified properly in order to obtain the required signal level. After that with the help of a phase locked source oscillating at 5990 MHz, the analog signal is upconverted to 8.2 GHz, operating center frequency. Required attenuation and filtering operations are accomplished, taking related current, voltage and impedance matching conditions. BPF from modulator
Att
Amp
PLO Fig. 5 Block diagram of IF Stage POWER AMPLIFIER: DESIGN, REALIZATION METHODS AND MEASUREMENT RESULTS For the realization of the power amplifier, for the first and second stages, respectively, FLM7785-4F and FLM7785-12F internally matched transistors from Fujitsu Quantum Devices are used (Fig.6). All parts used, especially transistors, are commercial, not space qualified. This provides us a highly cost-effective process. In order to increase the reliability of the transistors, drain voltage lower than the specified value in the data sheet is used, i.e., instead of 10V, 8.8V is used. According to the results of space environment compatibility verification tests, the power amplifiers that meet the requirements will be chosen for space flight model. Input Matching
FLM7785-4F Output Matching
Input Matching
FLM7785-12F
Output Matcing
Fig. 6 Block diagram of IF Stage It is planned to obtain an output of 21 dBm output from the driver stage which will be realized using a medium power amplifier from MITEQ, AMF-08120-25-15P, and an output 31 dBm and 38.5 dBm from the stages with FLM7785-4F and FLM7785-12F respectively. Since the type of the modulation is planned to be QPSK/ OQPSK it is important to choose the transistors according to 3dB peak to average ratio. Although the transistors that are used in the design are internally matched, our studies proved that, it is better to use input and output matching circuitry for both of the stages. Nonlinear simulations are carried out on RF Spectra for the amplifier by using the models of the transistors depending on the data given by Fujitsu Quantum Devices. The aim of these nonlinear simulations are to observe the efficiency and linearity of the system and this matching circuitry effects the efficiency of the power amplifier and the maximum power available from the power amplifier. Especially the impedance seen at the harmonic frequencies is important. For instance, the second stage can be realized using harmonic termination where this concept relies on the fact that – i.e. for a Class A amplifier - at the second order harmonic of the carrier frequency, very low impedance is introduced at the output of the amplifier and at the third order harmonic of the carrier frequency, very high impedance is introduced at the output of the amplifier. Then, the drain voltage adds odd harmonics so as to build its shape and exhibits sharper edges (squaring the sinewave) than a sinusoidal does, rising up the efficiency. Meanwhile, even harmonics contribute to the other drain waveform (i.e. current) to build its shape toward a half sinewave. But, since these waveforms (drain voltage and current) are shifted in phase by 180° from
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eachother, the time which the transistor sustains current and voltage is reduced. This phenomenon decreases the extra power consumption taking place in the transistor, which results in a net efficiency increase [8]. By this way, 15%-30% efficiency increase can be obtained with an acceptable distortion in linearity, i.e. at S-band, 73% efficiency with -25dBc third order distortion at an output of 2.9W and this can be applied to X-band power amplifiers [3]. So, different output matching circuitry designs are made, including ‘desired impedance at fundamental - short circuit at the second harmonic’, and are realized to see the difference. However when the impedance seen at the output of the transistor is short circuit at the second harmonic, the maximum output power of the transistor is limited. When the impedance seen at the output of the transistor is conjugately matched at the fundamental frequency and the impedance at the second harmonic is less than 1:3 VSWR with inductive imaginary part, the desired drain current performance with a maximum output power of 41.2 dBm is obtained. Another alternative to increase the efficiency is to make the impedance at the second harmonic open circuit while keeping the impedance at the fundamental at conjugately matched. Studies on this latter topic is currently continuing, which are, with the former topology, applications of so-told harmonic termination concept. Hence, using S-parameters of the FLM7785-4F and FLM7785-12F internally matched transistors from Fujitsu Quantum Devices, matching circuitry for the first and second stage are designed. In these designs, it is assumed that matching circuitry layouts will be realized on the high frequency laminate, Rogers-TMM6 / Thickness: 0.05`` / Dielectric constant: 6. Simulations of matching circuitry and harmonic termination effects are carried out on Sonnet, considering probable loading of bias circuitries. After the measurements, it was clear that the matching circuitries are not at the desired frequency. This may be because of the parasitic effects of the package of the transistor, slight differences between the specified S-parameters of the transistors due to the bias conditions, effects that are not included in the simulations. In addition, it is observed that, especially at high power, there is grounding and shielding problems which limit the gain of the second stage to 5dB. Although, the case of the transistor and the printed circuit board (PCB), containing the bias circuitry and transmission lines used for matching, are on the same carrier aluminum, in order to avoid the gain problem, the case of the transistor is connected to the ground of the printed circuit board with copper pieces (Fig. 7). Also a copper shield is put, surrounding the transistor. Besides, microstrip matching is used and placement strategy of this shield is optimized for maximum output power. extra groud
transistor
around
copper i
Fig. 7 Grounding strategy to avoid gain problem When different matching circuitries are investigated, it was seen that the one which shows short circuit at the second harmonic limits the maximum output power to 38dBm. However, the one with the impedance given in Fig.8 has an output up to 41 dBm and the drain current decreases with the decreasing input power which is desirable for high peak to average value signals.
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Fig. 8
Impedances seen at the output of the transistor at (a)fundamental and (b) second harmonic frequencies
Measurement results of the first stage and the second stage with the impedance in Fig. 8 are given in Table 1. The output power of the second stage is measured at different drain currents with the drain bias of 8.8V (Drain current values are measured at an output power of 38.9 dBm). The adjacent channel power for different current values are also given. As can be seen from these results, the second stage is only 0.1 dB compressed at the operating point (8.2 GHz) so the adjacent channel power increases only up to 30dBc which satisfies CCSDS recommendations with sufficient margin when the drain cuurent is 2.2 A from 8.8V power supply. In addition, the operating point of the second stage transistor is 2.5 dB below the maximum output power specified in the data sheet. Table 1 Frequncy (GHz)
7.9 7.95 8.0 8.05 8.1 8.15 8.2 8.25 8.3 8.35 8.4 8.45
Output Power of Driver stage power (dBm)
Output power of the first stage (dBm)
Output power of second stage with Id=2.2A (dBm)
Adjacent channel power of second stage with Id=2.2A (dBc)
Output power of second stage with Id=2.5A (dBm)
Adjacent channel power of second stage with Id=2.5A (dBc)
8.3 13.3 16.3 18.3 19.3 20.3 21.3 22.3 23.3 24.3 25.2 25.8
19.9 24.9 27.9 29.9 30.9 31.9 32.9 33.9 34.6 35.0 35.5 35.7
26.8 31.8 34.8 36.8 37.8 38.8 39.7 40.2 40.5 40.7 40.9 41.1
