ENHANCING SYSTEM-LEVEL EDUCATION WITH REUSABLE DESIGNS
D. W. BOULDIN Electrical & Computer Engineering University of Tennessee Knoxville, TN 37996-2100 U.S.A.
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Abstract Now that silicon manufacturing has enabled the cost-effective production of single-chip implementations for what previously were considered full systems, designers are increasingly reusing significant portions of previous designs. Thus, today’s integrated circuits require that designers create and integrate reusable building blocks or intellectual property (IP). It is, therefore, imperative that universities provide the appropriate courses so that more students can become system-level designers. Curricula need to be updated at several points to include team projects. Universities need to collaborate with one another to share course materials, intellectual property blocks and ideas. Several possibilities for collaboration are presented and discussed.
1. Introduction Multi-million transistor integrated circuits can now be produced cost-effectively [1]. Thus, designers are faced with the challenge of creating and verifying the content of these chips as quickly as possible in order to reduce the time-to-market. It has been estimated that a one-month delay in bringing a product to market can result in a loss of ten percent of the potential revenue [2]. Hence, not all of the transistors on these chips can be customized but instead must be ported from previous designs. These reusable cores or intellectual property (IP) blocks include CPUs (like ARM, MIPS and Sparc), MPEG decompression engines, PCI bus controllers, specialized DSPs, etc. Combining several complex cores using gates and standard cells is much more manageable and quicker than designing millions of transistors one at a time. Creating and integrating reusable blocks is a system-level design style that must be adopted and implemented rigorously in our universities. Curriculum needs to be updated at several points to include team projects. However, totally revolutionizing curricula is extremely difficult with all of the pressures from other
groups to include their own items of interest. However, it is relatively straightforward to adapt or upgrade existing courses to provide for formal training and experiences in system-level design. These may include: Advanced graduate-level electives can focus on open-ended design problems, use the latest CAD tools and the most advanced IP to provide students with experiences in creating and integrating IP. Senior undergraduate capstone sequences can focus on more constrained problems which involve a mixture of hardware and software, thereby giving students experience integrating existing IP with a limited amount of time devoted to creating new IP. Freshman introductory design courses can focus on highly supported and bounded projects which provide motivation to attract students into the more advanced curricula. Universities need to collaborate with one another to share course materials, intellectual property blocks and ideas. Existing and potential collaborative efforts are discussed in this paper.
2. Requirements for Reusable IP The myth that characterises today’s IP is that these components are blocks that have well defined contents and interfaces. However, they are often fuzzy and hence appear more like patches in a quilt which must be stitched together. The components cannot be assembly blindly and rapidly but rather must be carefully pieced together to form a working system. Therefore, design for reuse does not come free. Rather it involves much more indepth documentation and characterisation than for a design that is not intended to be reused. Based on the experiences of software engineers [3], it is estimated that preparing a component for reuse will require about 50% additional effort. Once this has been done, the designer who is reusing the component may naively think that his design time for that component will be reduced to zero. But alas, he must take care to understand fully how the component works and how it should be integrated with other components. Again from the experiences of software engineers [3], the second design generally requires about 30% of that required to produce the component originally. Thus, the reuse is not for free but does make a significant (70% reduction) impact on the next design.
The information required to document soft IP consists of far more than just the source code. Also needed are: (1) functional description, (2) application intent, (3) interface specifications, (4) authors and owners, (5) packaging information, (6) input stimuli and output responses (test bench), (7) tools and versions used, (8) FPGA or ASIC foundry used for fabrication, (9) size, delay and power measurements, and (10) testability features including BIST, JTAG and SCAN.
3. Candidate Projects In our advanced graduate electives at the University of Tennessee [4], the initial course in a two-semester sequence provides the students with the opportunity to learn how to synthesize small pieces of HDL source code into FPGAs. In the second semester, larger projects are assigned that require a team of generally four students to implement. The application requirements are first presented in narrative form and the team members must partition the design into manageable modules. Each module is the responsibility of an individual to capture in VHDL, synthesize and simulate as well as verify in an FPGA. Once each student believes his design is “known good”, the team then integrates the components into a singlechip ASIC. Obviously, any deficiencies not already corrected by individual designers must be dealt with during this integration or design with reuse phase. It is not unusual for a student to recognize that the quality of his component or his documentation is substandard and hence some redesign or additional documentation is performed until the full system works properly. Projects following the model just described are intended to provide individual students with the experience of designing for reuse and the team of designers with the experience of design with reuse. Example projects completed or underway include: Wavelet Image Compression, Huffman Encoding, LZ Data Compression, Discrete Cosine Transform, Fast Fourier Transform, CORDIC 2-D Vector Rotation, Automatic Target Recognition, Constant False Alarm Rate, Data Encryption, and Boolean Satisfiability.
4. Potential Collaboration The development of large team projects like those described in the previous section are marked by the partitioning of the full design into several manageable modules. Presently in our classes, all of the modules are being designed “live” by students in the same class on the same team. However, a tougher standard for design for reuse and design with reuse would involve having one (or more) of the components be taken from a previous course. Thus, the system integrators would not have the benefit of being able to talk with the original author to gain more information or to ask for portions to be redesigned. Moreover, the IP component
could potentially be obtained from a student in a course taken at another university. The component could have been designed the year before or even “live” using the Internet for collaboration. All of this discussion brings me to one of the central points of this paper: namely, universities should collaborate on the creation of portable, soft IP that can be reused at other universities. One possibility is for a complete multi-component project to be shared so that the next team of designers can utilize one or more of the pre-existing blocks. If one of the team members is unsuccessful in doing his module, the instructor could then reveal the previously developed solution. This approach provides the instructor with a “known good project” and its solution manual. It also potentially permits a team to tackle a more complex project by adding to its members the “virtual” designers who have preceded them. In essence, this is the approach that commercial companies are seeking to employ. They want to be able to create a system which would normally require a team of 20 designers but have perhaps only 5 on hand. The efforts of the missing designers are replaced by the reusable components. All of the examples given so far have been for developing soft IP using a HDL for implementation using FPGAs or single-chip ASICs. These are appropriate for advanced graduate electives which are targeted at developing system-on-a-chip designers. For senior capstone courses, projects must generally involve integrating existing hardware and software components with only a limited amount of time available for creating new components. Again sharing of previously developed modules could be performed by reusing those from a prior semester or another university. Similarly, sharing of resources for freshman introductory courses could also be undertaken. 5. Conclusions Sharing of IP modules that have been designed for reuse is a viable means of enhancing system-level education and several possibilities for collaboration have been proposed in this paper. 6. References [1] International Technology Roadmap for Semiconductors, http://www.itrs.net.ntrs/publntrs.nsf. [2] Smith, M., ASICs, Addison-Wesley-Longman (1997). [3] Design For Reuse Workshop, http://aemp.eeel.nist.gov/reuse. [4] Bouldin, D., Graduate Courses Using Synthesis, University of Tennessee, http://microsys6.engr.utk.edu/ece/bouldin_courses.
