Evolvable Hardware with Genetic Learning Tetsuya Higuchi (
[email protected]) 1-1-4, Umezono, Tsukuba, Ibaraki, 305 Japan Electrotechnical Laboratory
1 Introduction Neural networks can recognize patterns very flexibly as humans do, even if inputs with noise or incompleteness are given. We aim at the implementation of this flexible mechanism for association by taking a completely different approach from neural networks. We name this approach “Evolvable Hardware” (EHW). EHW is a hardware device which can adapt its own hardware structure to the environment to give the best performance. EHW has the pattern recognition capability like neural network. In addition to it, EHW can attain real-time performance which could not be obtained by neural networks. Specifically, EHW is built on Programmable Logic Device (PLD) or Field Programmable Gate Array (FPGA) where a software bit string determines the hardware structure of the device. EHW finds out by GAs such a bit string which adapts best to the environment and then reconfigures its own hardware structure according to the bit string. In EHW, adaptation takes the form of direct modification of the hardware structures according to rewards received from the environment. This results in a number of advantages. Adaptation in real-time is feasible due to a speed-up by many orders of magnitude. The system will be flexible and fault-tolerant since EHW can change its own structure in the case of environmental change or hardware error. Our long-term goal is to implement EHW on one chip so that it can be utilized as an “off-the shelf” device. This paper reports on the ongoing EHW-research project.
ist whose architecture and as a results whose function can be specified by a number of architecture bits [7]. If these bits change then the architecture and the function of the logic device also change. The basic idea of EHW is to let the architecture bits evolve in order to adapt the function of logic devices to a given environment. By incorporating both reinforcement learning and genetic learning, EHW can choose by itself a logic device architecture which gives the best performance with respect to the environment. The genetic learning scheme used is a parallel version of the genetic algorithm (GA). The GA operates on a population of bit strings, each of which determines the architecture of a hardware-reconfigurable logic device. Depending on the architecture bit string, the logic device will behave differently. The performance of all these logic devices on a given task is evaluated in parallel and the resulting performance measure is the fitness of the corresponding architecture of the logic device. The GA gives the better architecture bit strings a higher chance to survive and to recombine. This way, we get a new generation of architecture bit string which might incorporate good features of their parent architectures. This new generation is then fed into the logic devices which will behave accordingly. Their performance is again evaluated and this process continues that way. VLSI EHW chip could consist of the 3 following key components: 1. hardware-reconfigurable logic devices (RLD) 2. parallel GA hardware (i.e. chromosomes vector registers, vector processing units, and distribution network)
2 Evolvable Hardware Architecture Here, we describe a parallel processing architecture for Evolvable Hardware (EHW). The adaptation process is a combination of genetic learning with reinforcement learning. A first version of genetic learning component is in place already while the reinforcement learning component is future work. Nowadays, hardware-reconfigurable logic devices ex-
3. reinforcement learning components (RLC) Details of the schematic and these components are given in [6].
3 Applications Probably the most frequently asked question to EHW is “whether hardware evolution which gives useful logic cir-
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cuits is possible or not.” We have already reported the feasibility of hardware evolution in previous papers; the gate-level hardware evolution [2,6] and the HDL (Hardware Description Language) level hardware evolution [3]1. Combinatorial logic circuits like 6-multiplexer and sequential circuits like 3-bit counter and 4-state machine have been evolved successfully. Following these experiments. we are now going to more practical application domains. The advantages of EHW such as its execution speed and its re-adaptability (reconfigurability) may contribute considerably to industrial applications in future. Autonomous agents and pattern recognition are potentially promising candidates for EHW’s application domain.
3.1 Subsumption Architecture Subsumption architecture is a new approach to building behavior-based robots [1]. In such a robot, a goal is attained through interactions among simple modules. For example, to make a robot walk, a module to raise a leg may cooperate with a module to move a leg forward. Adding a new module to a robot leads to improving the performance of a robot. However, in that case, a mechanism is required to arbitrate the interactions between the new module and existing modules. For example, if two modules try to perform opposite goals (i.e. moving forwards and moving backwards), one of the modules should be suppressed (or subsumed) by the arbitration mechanism. However, as the number of modules increases, the arbitration becomes more difficult. It is almost impossible for programmers to specify all the occasions where arbitration is necessary when the robot contains many modules. This is one of problems associated with the subsumption architecture. EHW is one of the promising candidates to solve this. In [4], we have shown that such an arbitration can be done through EHW and that EHW can reconfigure its hardware structure when some hardware error occurs. A robot with two motors and sensors is successfully controlled with an arbitration through EHW in order to reach to the destination, even if one motor fails.
4 Conclusions This paper described the EHW concept and ongoing research. Our current design efforts towards VLSI EHW proceed in two directions. The first is the design of hardware reconfigurable device. The main concern is how to express versatile hardware functions with less architec-
ture bits, which directly influences the GA search space. The second is the design of parallel GA hardware [5]; analyses especially on the interconnection network performance are being conducted carefully. We believe that EHW will be a key component for flexible mechanism for association from the following reasonings: 1. The execution speed of the evolved system will be extremely fast (at least three orders of magnitude faster than a software implementation) because the result of adaptation is the hardware structure itself. 2. Fault tolerant and flexible design is realized because EHW can change its own structure in the case of hardware error or environmental change, utilizing its on-line re-adaptation capability.
Acknowledgement: The author thank Dr. Otsu, Dr. Ohta, Dr. Iba and Dr. Manderick for their advice.
References [1] Brooks, R. A. “A robust layered control system for a mobile robot,” IEEE Journal of Robotics and Automation, Vol. 1, 1986. [2] Higuchi, T., Niwa, T., Tanaka, T., Iba, H., de Garis, H. and Furuya, T., “Evolvable Hardware with Genetic Learning,” in Proc. of Simulated Adaptive Behavior, MIT Press, 1993. [3] Higuchi, T., Niwa, T., Tanaka, T., Iba, H., de Garis, H. and Furuya, T., “Evolvable Hard ware – Genetic Based Hardware Evolution at Gate and Hardware Description (HDL) Levels,” ETL Tech. Report, 934,1993. [4] Higuchi, T., Iba, H., and Manderick, B., “Applying Evolvable Hardware to Autonomous Agents,” ETL Tech. Report (to appear), 1994. [5] Higuchi, T., Niwa, T., Tanaka, T., Iba, H., “A Parallel Architecture for Genetic Based Evolvable Hardware,” Proc. of 2nd Workshop on Parallel Processing for Artificial Intelligence, PPAI-93 (IJCAI-93 Workshop), 1993. [6] Higuchi, T., Iba, H., Manderick, B., “Evolvable Hardware,” in “Massively Parallel Artificial Intelligence,” AAAI/MIT Press, to appear in 1994. [7] Lattice Semiconductor Corporation, “GAL Data Book,” 1990.
1 The HDL level hardware evolution may be suitable for LSI, but lacks in re-adaptability. In [3], genetic programming is used for HDL evolution. On the other hand, the gate level evolution is suitable for on-line adaptation, but the circuit scale is not large.
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