A Bird's Eye View of FPGA-based Evolvable Hardware - CiteSeerX

A Bird’s Eye View of FPGA-based Evolvable Hardware Fabio Cancare∗ , Sheetal Bhandari† , Davide Basilio Bartolini∗ , Matteo Carminati∗ and Marco Domenico Santambrogio∗‡ ∗ Dipartimento

† Department

di Elettronica e Informazione - Politecnico di Milano - Milano, Italy of Microelectronics and VLSI Design - International Institute of Information Technology - Pune, India ‡ CSAIL, Massachusetts Institute of Technology - Cambridge, MA, USA

Abstract—The Evolvable Hardware research area has achieved very important progresses in the last two decades. However, it is still quite far from being as revolutionary as depicted in the earlier visionary papers. To have a positive impact on the Embedded Design Automation field, Evolvable Hardware systems should start to deal with more complex problems instances efficiently. This paper describes some interesting results achieved so far in the Evolvable Hardware area and gives some hints on what should be done for increasing the efficiency of Evolvable Hardware systems.

I. I NTRODUCTION The era of digital electronics has witnessed many design techniques and approaches aimed at keeping the pace with the increasing number of transistors on a silicon chip [1]. For decades, this trend in silicon technology has been closely following Moore’s law.In spite of facilities like powerful Electronic Design Automation (EDA) tools, high-level abstraction design techniques and advancement in IP-core libraries, the design-productivity gap is increasing. The complexity of electronic systems is also increasing and so do the faults and errors seen in these systems. This has posed a challenging situation in front of researchers demanding a next breakthrough in design techniques. Looking elsewhere, however, Nature has been able to create (biological) systems whose complexity is far higher than the one characterizing the (artificial) ones created by the humankind; such systems are the result of a continuous ongoing evolutionary process started millions of years ago. One could wonder if it is possible to make use of a similar process for creating circuits and, at the same time, for complying with the requirements of the modern design processes, e.g. time to market. On the basis of such hypothesis, several researchers started to work on what has been later called Evolvable Hardware (EHW) [2]–[5]. The past two decades represent a period of intense creativity in the EHW field. Turning away from traditional design techniques, which follow the various phases of design and testing [6], in Evolvable Hardware circuits are evolved until a suitable solution is found [5]. EHW can be considered as a scheme for designing hardware components that can change their behavior dynamically and autonomously to adapt to the surrounding environment. This is accomplished thanks to

evolutionary strategies aimed at improving the components behavior with respect to a given specification. These evolutionary strategies are stochastic search methods that try to mimic the process of natural biological evolution and are implemented as Evolutionary Algorithms (EAs) [7]. This approach permits the exploration of a very large design search space, which can ideally enable EHW to find solutions that are more optimal than those found using traditional design methods. The goal of this paper is to provide an overview of the Evolvable Hardware research field and of its ongoing research trends. Even if it is possible to distinguish between analog EHW systems, mixed analog-digital EHW systems and digital EHW systems, this paper focuses on just digital EHW systems and, in particular, on those relying on commercial FPGAs. The rest of the paper is structured as follows: Section II provides some definitions of EHW terminology and a general description of the EHW approach. Section III outlines the most important EHW historical phases and turning points. Section IV presents the most recent works proposing or making use of FPGA-based EHW systems. Finally, Section V gives some hints on how research in the EHW fields could evolve in the near future. II. EHW AT A GLANCE A simple, yet meaningful, representation of how an evolvable hardware system works is shown in Figure 1, which highlights the fundamental steps of such a system. First, the initial circuits population is randomly generated and each circuit is evaluated using a fitness function. In the scenario where the computed value is greater than a predefined target value, representing a satisfaction threshold, a solution for the problem has been found. This does not mean that the evolution is necessarily finished, as explained below. Otherwise a new generation of circuits is derived from the individuals of the last generation by applying a set of genetic operators (e.g. elitism, cross-over, mutation, . . . ), and the cycle is repeated. The afore described flow is at the basis of all the Evolvable Hardware systems presented in Section III. These systems are however characterized by different objectives and different implementations. For these reasons, before getting into the description of the theoretical concepts EHW is based on, it


              

          

             

                





  

Fig. 1.

Evolutionary circuit design flowchart

is worthwhile providing some terminology for classifying the different approaches. The first and the most important classification is related on how candidate solutions are evaluated; there are two main techniques [8]: • Extrinsic evolution: circuits are evolved using a simulation environment. This means that the EA relies on simulated evaluations: once a suitable solution is found, such solution is implemented within the device. • Intrinsic evolution: the candidate solution is directly mapped and evaluated on the target device, i.e. the EA relies on actual evaluations. Obviously, the latter method is more accurate, providing better performance and allows to create self-evolvable hardware systems. On the other hand, the main drawback of the intrinsic approach is the high amount of time lost during the reconfiguration process [15]. Focusing the attention on intrinsic evolution, it is possible to distinguish two sub-categories [8]: • Complete intrinsic evolution: in this case the evolving systems is improved by implementing the EA as a hardware module (there is no more need for an external environment, not even to load the bitstream on the FPGA). • Open-ended intrinsic evolution: in this last case new solutions are evolved endlessly, while having the best solution found so far up and running. Another way to classify the approaches to EHW is based on the level at which evolution is performed. More formally, the devices for EHW experiments are made of several elementary

blocks, connected through a communication interface. The complexity level of these building blocks is called granularity and can be divided in [9]: • Gate-level: the building blocks correspond to simple logic gates (AND, OR, . . . ). • Function-level: this case represents a further abstraction with reference to the previous one, since the building blocks can implement functions characterized by a high complexity. Sections III and IV present some relevant works in the EHW field which realize in different ways the general approach described above. III. A DEVICE - DRIVEN HISTORY Evolvable hardware was born in 1993. It has been conceived by Higuchi et al. [2] and de Garis [3]. Both these theoretical works envision that the circuit design process should rely on principles and mechanisms similar to those that characterize natural evolution. As in Nature, where the genotipic information stored in the Genome determines part of the phenotypic traits of living beings, circuits could be synthesized according to finite strings of symbols determining their behavior. Both Higuchi et al. and de Garis conclude that the proposed technique is perfectly suited for the creation of digital circuits, to be evolved using digital programmable hardware devices and varying their configurations. One of the first FPGA-based EHW practical experiments was conducted by Thompson in 1996 [10]. He used a Xilinx XC6216 FPGA to evolve a frequency discriminator able to distinguish between 1 kHz and 10 kHz square waves. Circuits were evolved targeting a subset of the FPGA area (a square made of 10x10 CLBs) and using a canonic genetic algorithm executed on an external workstation. The workstation deploys the circuit configuration bitstream1 on the FPGA and evaluate each individual providing inputs and monitoring the corresponding outputs (intrinsic evolution). After a three-week experiment, Thompson was able to get a working circuit. Further experiments demonstrated that such a solution can be simplified (i.e. some of the CLBs within the targeted area were not used), it is device-dependent (i.e. the circuit behavior changes when the circuit is deployed to a different device) and it is susceptible to external conditions (i.e. if the temperature changes, the circuit behavior changes). However this work can be considered a very important milestone because it demonstrates the effectiveness of the EHW approach. To cope with the dependencies introduced by the device used and the external conditions, Thompson developed a new evolutionary circuit design system, the so-called evolvatron [11]. Using this system, still based on Xilinx XC6216 FPGAs, Thompson was able to evolve circuits whose behavior is not dependent on the device used, the temperature and the power supply. Such results were confirmed and strengthened 1 Where a configuration bitstream is a file used to implement a desired circuit/functionality on a reconfigurable device like an FPGA

by Thompson and Layzell in a 2000 paper [12]. Other very interesting practical experiments, still relying on Xilinx XC6200 family FPGAs, were conducted by Keymeulen et al. [13] and by Huelsbergen et al. [14]. The fact that most of the early practical EHW works were based on the Xilinx XC6200 device family is motivated by the following devices features [15]: • Static RAM configuration storage. The device configuration is stored in a quickly available static RAM, that can be read and write using a standard interface; • Dynamic Partial reconfiguration. Selected portions of the device can be reconfigured without affecting the remaining device portions, which can continue to work during the reconfiguration process; • Fast reconfiguration. The parallel configuration static RAM interface allows to achieve very high reconfiguration rates; • Targeted reconfiguration. The configuration bitstream format is known, it is possible to change the bitstreams according to well-defined needs; • Safe reconfiguration. Random configuration bitstreams always yield to valid circuits; the chip can not be damaged by invalid configurations. Unfortunately, the XC6200 device family was discontinued by Xilinx in May 1998. The main reason was that the open bitstream format was allowing the reverse engineering of proprietary hardware IP-cores; moreover, the unidirectional routing mechanism was limiting the circuit design process. After some months Xilinx introduced the Virtex device family, featuring characteristics very similar to those described above, but for the targeted and safe reconfiguration features. The Xilinx XC6200 family discontinuation and the Xilinx Virtex family introduction was a major turning point for FPGA-based EHW. Researchers started to propose new methodologies and approaches to overcome the limits imposed by the Xilinx Virtex family [4], [15]–[17]. Most of the subsequently proposed FPGA-based approaches can be classified into two categories: Virtual Reconfigurable Circuits (VRCs) and direct bitstream manipulation systems. VRC-based solutions [18], [19] consist in having one or more programmable structures, defined using a Hardware Description Language (HDL), deployed to the target FPGA. The behavior of these virtual circuits is determined by a configuration memory, whose content is evolved according to the fitness of the corresponding virtual circuit. Direct bitstream manipulation techniques focus on the evolution of low-level configuration bitstreams that determine the behavior of either the entire target FPGA or of a subsection of it. A correct bitstream manipulation can be achieved either using well-defined APIs [15], [20] or by reverse engineering parts of the configuration bitstream and then directly manipulating them [21], [22]. From the year 2000 on, many works describing new EHW systems, techniques, and applications have been published.

Most of these works can still be classified according to the criteria just described, and consist in proposing improvements to existing systems and showing how real-world applications can benefit from EHW (see Table I). The main problem addressed by most of these publications is indeed the overall scalability. Section IV describes some of the most recently proposed works. Further details about FPGA-based Evolvable Hardware history and approaches can be found in [5], [8]. IV. A STEP TOWARDS EHW FOR REAL - WORLD PROBLEMS EHW is a research topic in constant growth. The initial drive was to study the topic theoretically and prove the concept by evolving simple circuits using evolutionary algorithms. As a consequence to this, researchers have proved that EHW techniques are capable of designing simple electronic circuits in an optimal way. In recent years, researchers have worked to make EHW systems able to deal with real world applications. Good work is being carried out around every aspect of EHW: evolutionary algorithm used, fitness calculation and the overall hardware implementation. In this Section are described some recent scientific works having as goal the enhancement of the EHW systems effectiveness and efficiency. Researchers have tried different approaches like employing different evolutionary algorithms, using different techniques to solve the issues of scalability, using different devices and platforms, proposing various models for the overall FPGA implementation, designing complex circuits/applications using EHW. Since the beginning FPGAs have been prime candidate for EHW systems implementation. With advent of time, FPGAs also have changed with respect to the resources, ability and access to the information. With more resources and features like dynamic partial reconfiguration (DPR) it has become possible to use the device to carry out different types of evolution. Lambert et al. proposed three different FPGAbased approaches for implementing intrinsic EHW systems in [35], namely Run-Time Configuration system, JBits-based Run-Time Configuration systemand Multi-board functionallevel Run-Time Configuration system. Based on theoretical studies, authors conclude that use of multi-board or multichip system will allow to overcome at the certain level the scalability problems and reduce the time required to re-design the system every time the new FPGA platform has been chosen or new chip has been considered. One of the major challenges in using EHW to solve realworld problems is scalability, which limits the size of the circuit that may be evolved through it [5]. Decomposition (divide and conquer) is the solution perceived by researchers for the same. Stomeo et al. presented Generalized Disjunction Decomposition (GDD) method in [30]. GDD is based on the fact that, the number of generations required to evolve a circuit depends upon the number of inputs. GDD proposes decomposition of the inputs in smaller subset. Using the technique, authors have evolved multipliers, n-bit parity function, randomly generated logic circuits and MCNC benchmark circuits.

TABLE I OVERVIEW OF THE MAIN FPGA- BASED EHW WORKS THAT CAN BE FOUND IN LITERATURE . A LL THE ENTRIES ARE CLASSIFIED ACCORDING TO THE CRITERIA INTRODUCED IN [8], [9], [16] Author

Year

Methodology

Target FPGA

Evolutionary algorithm

Case study

Thompson [10]

1996

Gate-level intrinsic evolution

Xilinx XC6216

Canonic genetic algorithm

Frequency discriminator

Thompson [11]

1998

Gate-level intrinsic evolution

Xilinx XC6216

Canonic genetic algorithm

Robust frequency discriminator

Porter and Bergmann [23]

1998

Gate-level intrinsic evolution

Xilinx XC6216

Canonic genetic algorithm

Image filters

Huelsbergen [14]

1999

Gate-level intrinsic evolution

Xilinx XC6216

Canonic genetic algorithm

Oscillators

Levi and Guccione [20]

1999

Gate-level intrinsic evolution (JBits)

Xilinx XC4028EX and XC4085XL

Canonic genetic algorithm

Counters and frequency dividers

Torresen [24]

1999

Gate-level/function-level intrinsic evolution

Xilinx XC6200

Canonic genetic algorithm

Characters recognition

Kalganova [25]

2000

Function-level extrinsic evolution

N.A.

(1+λ) Evolution Strategy

z5xp1 d.pla benchmark

Gallagher and Vigraham [26]

2002

Function-level intrinsic evolution

N.A.

Compact genetic algorithm

Neural Networks

Yasunaga et al. [27]

2003

Gate-level extrinsic evolution

Xilinx XCV300

Canonic genetic algorithm

Human gene recognition

Sekanina and Friedl [28]

2004

Function-level intrinsic evolution

Xilinx XC2V3000

Cartesian genetic programming

Adders, multipliers and parity generators

Upegui and Sanchez [21]

2005

Gate-level intrinsic evolution

N.A.

Canonic genetic algorithm

None, the FPGA systems are proposed but not implemented

Upegui and Sanchez [22]

2006

Gate-level intrinsic evolution

Xilinx Virtex-II

Cellular programming

Synchronization mechanisms

Glette et al. [29]

2006

Function-level intrinsic evolution

Xilinx XC2VP30

Canonic genetic algorithm

Image recognition

Stomeo et al. [30]

2006

Gate-level extrinsic evolution

N.A.

(1+λ) Evolution Strategy

multipliers, parity generators and MCNC benchmarks

Sekanina [31]

2007

Function-level extrinsic evolution

FPGA simulator

Cartesian genetic programming

Fault tolerance

Vasicek and Sekanina [32]

2007

Function-level intrinsic evolution

Xilinx XC2VP50

Random search, hill climbing and canonic genetic algorithm

Image Processing

Wang et al. [33]

2007

Function-level intrinsic evolution

Xilinx XCV2000E

Parallel (1+λ) Evolution Strategy

Adders and multipliers

Oreifej et al. [34]

2007

Gate-level intrinsic evolution

Xilinx Virtex-II Pro

Canonic genetic algorithm

Self-healing adders

Lambert et al. [35]

2009

Gate-level/function-level intrinsic evolution

N.A.

Not described

None, the FPGA systems are proposed but not implemented

Glette et al. [36]

2009

Function-level intrinsic evolution

Xilinx Virtex-II Pro

Canonic genetic algorithm

Sonar return and face image recognition

Vasicek et al. [37]

2010

Function-level extrinsic evolution

Xilinx XC2V50

Cartesian genetic programming

Image impulse bursts noise filtering

Cancare et al. [38]

2010

Gate-level/Function-level intrinsic evolution

Xilinx Virtex-4

Cartesian genetic programming

Parity generators, forwarders, counters

Experimental results put forth by authors show that the GDD technique requires smaller generations and improves scalability while compared to traditional techniques like bidirectional incremental evolution (BIE). Authors also have presented a very good survey of circuits designed by EHW technique with respect to the complexity of the circuit. Wang et al. [33] have proposed a multi Virtual Reconfigurable Circuits (multiVRC) core for addressing the scalability issue. The basic idea behind the proposed scheme is to divide a combinational logic circuit into several sub-circuits, and each sub-circuit is evolved independently as a sub-component by its corresponding VRC core. Parallel EA is used to evolve two sub-circuits at a time. Authors implemented this approach on Xilinx XCV2000E FPGA. Evolution is carried out for a 3-bit adder and a 3-bit multiplier. Results obtained are compared with methods like direct evolution and incremental evolution. Reported results indicate that the multi-VRC technique reduces number of generations required and so the time for evolving circuits. Moving ahead from simple applications like adders, multipliers and parity generators, new interesting applications have also been developed using EHW. In Glette et al. [36] an intermediate-level FPGA partial reconfiguration approach is used for implementing a pattern recognition architecture. Authors propose SRL (Shift Register LUT) technique to achieve an intermediate level of reconfiguration. With the help of face and SONAR classification applications implemented on Xilinx Virtex-II, a comparison of the proposed technique with the conventional VRC technique is done. Results indicates significant reduction in the resource requirements by the SRL method. Vasicek et al. [37] have used EHW to design an impulse burst noise filter employing an extended Cartesian Genetic Programming (CGP) algorithm. The evolution is carried out on a cluster consisting of 100 PCs (Pentium IV, 2.4GHz, 1GB RAM) using the Sun Grid Engine (SGE). The filters chromosome were converted to a VHDL description and synthesized using Precision Synthesis to a Xilinx Virtex II Pro XC2VP50. A filter designed using the proposed evolutionary algorithm and different types of conventionally designed filters are compared. The evoluted filter is compact (i.e. it requires less resources when synthesized for the target FPGA) and is characterized by a good filtering quality. Challenges of implementing working intrinsic evolutionary strategies based on bitstream manipulation include the mapping of the genotype into its corresponding phenotype on the fabric, and the limited control over process automation of altering and downloading safe bitstream onto the device. These issues are more prominent as the critical portions of bitstream representation are proprietary. Recently Oreifej et al. [34] proposed an approach to carry out bitstream manipulation for Xilinx Virtex-II Pro device. They have developed data structures and an Application Programming Interface (API) to perform mapping operations directly on the bitstream to modify Lookup Table (LUT) configurations and reconfigure the device. A 4-bit adder is evolved using the platform and results shows considerable saving in time with respect to other

tools for bitstream manipulation like JBits and the Xilinx tool flow. Another work dealing with the intrinsic evolution of circuits through bitstream manipulation is the one proposed in [38], [39]. Thanks to a reverse engineering process authors were able to get some information about the Virtex-4 bitstream format [40]. Such information were used to create an intrinsic EHW system able to evolve circuits characterized by a 8bit I/O datapath. Besided the classical EHW benchmarks like adders, forwarders and parity generators, the authors were able to evolve a controller for the inverse pendulum problem. V. B REAKING THROUGH The Evolvable Hardware scientific field has achieved very important progresses in the last two decades. However, it is still quite far from being as revolutionary as depicted in the earlier visionary papers [2]–[4]. Up to now, two main EHW branches can be identified: evolutionary circuit design and open-ended circuit evolution [8]. Both of them need considerable efforts to achieve their full potential. For what concerns the evolutionary circuit design, scalability is still an issue from different points of view: • evolved circuits do not scale well with respect to the complexity of problems instances. As an example, while it is feasible to obtain a 3x3 multiplier from an evolution process, emergence of a 16x16 multiplier requires a substantially longer time and higher computational effort; • portability across different devices family is difficult to implement (especially true for EHW systems relying on bitstream manipulation); • evolved solutions are most of the times far from cost optimality (especially true for EHW systems relying on virtual reconfigurable circuits). To have a positive impact on the EDA field, EHW systems should start to deal with more complex problems instances. To be able to scale to such problems, several improvements should be introduced, like (i) faster circuit fitness evaluation methods, (ii) increased candidate solutions size and complexity, (iii) more effective ad-hoc evolutionary algorithms, (iv) hardware implementation of the evolutionary algorithms adopted, and (v) flexible and easy-to-use frameworks for supervisioning circuits evolution. EHW systems based on bitstreams manipulation and virtual reconfigurable circuits can both scale to more complex problems. The former kind of systems should solve the problem of scaling to the most recent device families while the latter kind of systems should be able to evolve more cost-effective circuits. However, another possible solution could be the development of hybrid EHW systems summing up the advantages of both methods. Both [36] and [38] are interesting preliminary works in this direction. Besides of their nature, all the different approaches should improve the performance of the evolutionary process. It should be possible to evaluate a candidate solution over billions of test cases in a reasonable amount of time. Moreover, the

evolutionary process should be implemented using hardware modules instead of relying on external workstations or embedded processors. The evolutionary algorithm employed should be tailored for circuits evolution. Generic canonic genetic algorithm should be abandoned. A tight collaboration with the Evolutionary Computation scientific field should be set up and insights such as hierarchical evolution and linkage learning [41], [42] should be taken into account while evolving hardware circuits. Recently, some examples of evolved image hardware filters that have a better performance/cost ratio than those created using traditional design flows have been described [37]. To make the evolutionary circuit design flow an appealing alternative to traditional circuit design flows similar results should be obtained in the image processing application field as well as in others like crypthography, non-linear algebra and data mining. For what concerns the open-ended circuit evolution, it must be said that, even if it better fits the original definition of Evolvable Hardware, it has been explored much less than evolutionary circuit design. In evolutionary circuit design candidate solutions are evolved until a suitable one is found; at that point the process is terminated, the canditate solution is extracted and is employed into successive designs. In openended circuit evolution the process of creating and evaluating new candidate solutions is never terminated. When it finds a suitable circuits, it enters in a standby state and the circuit found starts to work processing the actual inputs and providing its corresponding outputs. When the actual working circuits behavior evaluation falls below a certain threshold (e.g. because it was not tested thoroughly or because the external conditions have changed), the evolutionary process is awakened and a new solution is searched. Comprehensive open-ended circuit evolution systems need still to be created and evaluated. An interesting preliminary work is the one described in [34]. It would be very interesting to apply such systems in the field of automatic control and fault tolerance. ACKNOWLEDGMENT The authors would like to thank HIPEAC for their support. This research was partially founded by HIPEAC Reconfigurable Computing Cluster through a collaboration grant. R EFERENCES [1] J. O. Kephart and D. M. Chess, “The vision of autonomic computing,” Computer, vol. 36, pp. 41–50, 2003. [2] T. Higuchi, T. Niwa, T. Tanaka, H. Iba, H. de Garis, and T. Furuya, “Evolving Hardware with Genetic Learning: a First Step Towards Building a Darwin Machine,” in Proceedings of the second international conference on From animals to animats 2 : simulation of adaptive behavior: simulation of adaptive behavior. Cambridge, MA, USA: MIT Press, 1993, pp. 417–424. [Online]. Available: http://portal.acm.org/citation.cfm?id=171174.171223 [3] H. De Garis, “Evolvable Hardware Genetic Programming of a Darwin Machine,” in Artificial Neural Nets and Genetic Algorithms, R. F. Albrecht, N. C. Steele, and C. R. Reeves, Eds. Springer Verlag, 1993, pp. 441–449.

[4] X. Yao and T. Higuchi, “Promises and Challenges of Evolvable Hardware,” Systems, Man, and Cybernetics, Part C: Applications and Reviews, IEEE Transactions on, vol. 29, no. 1, pp. 87 –97, Feb. 1999. [5] G. W. Greenwood and A. M. Tyrrell, Introduction to Evolvable Hardware: A Practical Guide for Designing Self-Adaptive Systems. WileyIEEE Press, November 2006. [6] G. D. Micheli, Synthesis and Optimization of Digital Circuits, 1st ed. McGraw-Hill Higher Education, 1994. [7] D. B. Fogel, Evolutionary Computation: Toward a New Philosophy of Machine Intelligence (IEEE Press Series on Computational Intelligence). Wiley-IEEE Press, 2006. [8] A. Upegui and E. Sanchez, Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation. Morgan Kaufmann, 2008, ch. Evolvable FPGAs, pp. 725–752. [9] J. Torresen, “An Evolvable Hardware Tutorial,” in FPL, ser. Lecture Notes in Computer Science, J. Becker, M. Platzner, and S. Vernalde, Eds., vol. 3203. Springer, 2004, pp. 821–830. [10] A. Thompson, “An evolved circuit, intrinsic in silicon, entwined with physics,” in Proceedings of the First International Conference on Evolvable Systems: From Biology to Hardware. London, UK: Springer-Verlag, 1996, pp. 390–405. [Online]. Available: http: //portal.acm.org/citation.cfm?id=645507.656736 [11] ——, “On the automatic design of robust electronics through artificial evolution,” in Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware. London, UK: Springer-Verlag, 1998, pp. 13–24. [Online]. Available: http://portal.acm.org/citation.cfm?id=645508.656773 [12] A. Thompson and P. J. Layzell, “Evolution of robustness in an electronics design,” in Proceedings of the Third International Conference on Evolvable Systems: From Biology to Hardware, ser. ICES ’00. London, UK: Springer-Verlag, 2000, pp. 218–228. [Online]. Available: http://portal.acm.org/citation.cfm?id=645509.656911 [13] D. Keymeulen, M. Iwata, Y. Kuniyoshi, and T. Higuchi, “Online evolution for a self-adapting robotic navigation system using evolvable hardware,” Artif. Life, vol. 4, pp. 359–393, oct 1998. [Online]. Available: http://portal.acm.org/citation.cfm?id=1107352.1107357 [14] L. Huelsbergen, E. Rietman, and R. Slous, “Evolving oscillators in silico,” Evolutionary Computation, IEEE Transactions on, vol. 3, no. 3, pp. 197 –204, Sep. 1999. [15] G. Hollingworth, S. Smith, and A. Tyrrell, “Safe intrinsic evolution of virtex devices,” in Evolvable Hardware, 2000. Proceedings. The Second NASA/DoD Workshop on, 2000, pp. 195 –202. [16] J. Torresen, “Possibilities and Limitations of Applying Evolvable Hardware to Real-World Applications,” in FPL, ser. Lecture Notes in Computer Science, R. W. Hartenstein and H. Gr¨unbacher, Eds., vol. 1896. Springer, 2000, pp. 230–239. [17] P. Haddow and G. Tufte, “An evolvable hardware fpga for adaptive hardware,” in Evolutionary Computation, 2000. Proceedings of the 2000 Congress on, vol. 1, 2000, pp. 553 –560 vol.1. [18] L. Sekanina and S. A. M., “Toward uniform approach to design of evolvable hardware based systems,” in Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications, ser. FPL ’00. London, UK: Springer-Verlag, 2000, pp. 814–817. [Online]. Available: http://portal.acm.org/citation.cfm?id=647927.739390 [19] C. Slorach and K. Sharman, “The design and implementation of custom architectures for evolvable hardware using off-the-shelf programmable devices,” in Proceedings of the Third International Conference on Evolvable Systems: From Biology to Hardware, ser. ICES ’00. London, UK: Springer-Verlag, 2000, pp. 197–207. [Online]. Available: http://portal.acm.org/citation.cfm?id=645509.656910 [20] D. Levi and S. A. Guccione, “Geneticfpga: Evolving stable circuits on mainstream fpga devices,” in Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware, ser. EH ’99. Washington, DC, USA: IEEE Computer Society, 1999. [Online]. Available: http://portal.acm.org/citation.cfm?id=787262.787827 [21] A. Upegui and E. Sanchez, “Evolving hardware by dynamically reconfiguring xilinx fpgas.” in ICES, ser. Lecture Notes in Computer Science, J. M. Moreno, J. Madrenas, and J. Cosp, Eds., vol. 3637. Springer, 2005, pp. 56–65. [22] ——, “Evolving hardware with self-reconfigurable connectivity in xilinx fpgas,” in Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems, ser. AHS ’06. Washington, DC,

[23]

[24]

[25] [26]

[27]

[28] [29]

[30]

[31]

USA: IEEE Computer Society, 2006, pp. 153–162. [Online]. Available: http://dx.doi.org/10.1109/AHS.2006.38 R. B. Porter and N. W. Bergmann, “Evolving fpga based cellular automata,” in Selected papers from the Second Asia-Pacific Conference on Simulated Evolution and Learning on Simulated Evolution and Learning, ser. SEAL’98. London, UK: Springer-Verlag, 1999, pp. 114– 121. [Online]. Available: http://portal.acm.org/citation.cfm?id=645859. 669971 J. Torresen, “Increased complexity evolution applied to evolvable hardware,” in Smart Engineering System Design: Neural Networks, Fuzzy Logic , Evolutionary Programming, Data Mining, and Complex Systems, Proc. of ANNIE’99, 1999, pp. 429–436. T. Kalganova, “Bidirectional incremental evolution in extrinsic evolvable hardware,” in Evolvable Hardware, 2000. Proceedings. The Second NASA/DoD Workshop on, 2000, pp. 65 –74. J. C. Gallagher and S. Vigraham, “A modified compact genetic algorithm for the intrinsic evolution of continuous time recurrent neural networks,” in Proceedings of the Genetic and Evolutionary Computation Conference, ser. GECCO ’02. San Francisco, CA, USA: Morgan Kaufmann Publishers Inc., 2002, pp. 163–170. [Online]. Available: http://portal.acm.org/citation.cfm?id=646205.682964 M. Yasunaga, I. Yoshihara, and J. H. Kim, “Gene finding using evolvable reasoning hardware,” in Proceedings of the 5th international conference on Evolvable systems: from biology to hardware, ser. ICES’03. Berlin, Heidelberg: Springer-Verlag, 2003, pp. 198–207. [Online]. Available: http://portal.acm.org/citation.cfm?id=1766731.1766754 ˇ Friedl, “An evolvable combinational unit for fpgas,” L. Sekanina and S. Computing and Informatics, vol. 23, no. 5, pp. 461–486, 2004. K. Glette, J. Torresen, M. Yasunaga, and Y. Yamaguchi, “On-chip evolution using a soft processor core applied to image recognition,” in Adaptive Hardware and Systems, 2006. AHS 2006. First NASA/ESA Conference on, Jun. 2006, pp. 373 –380. E. Stomeo, T. Kalganova, and C. Lambert, “Generalized disjunction decomposition for evolvable hardware,” Systems, Man, and Cybernetics, Part B: Cybernetics, IEEE Transactions on, vol. 36, no. 5, pp. 1024 – 1043, Oct. 2006. L. Sekanina, “Evolutionary functional recovery in virtual reconfigurable circuits,” J. Emerg. Technol. Comput. Syst., vol. 3, July 2007. [Online]. Available: http://doi.acm.org/10.1145/1265949.1265954

[32] Z. Vasicek and L. Sekanina, “Evaluation of a new platform for image filter evolution,” in Adaptive Hardware and Systems, 2007. AHS 2007. Second NASA/ESA Conference on, Aug. 2007, pp. 577 –586. [33] J. Wang, C. H. Piao, and C. H. Lee, “Implementing multi-vrc cores to evolve combinational logic circuits in parallel,” in Proceedings of the 7th international conference on Evolvable systems: from biology to hardware, ser. ICES’07. Berlin, Heidelberg: Springer-Verlag, 2007, pp. 23–34. [Online]. Available: http://portal.acm.org/citation.cfm?id= 1792161.1792165 [34] R. Oreifej, R. Al-Haddad, H. Tan, and R. DeMara, “Layered approach to intrinsic evolvable hardware using direct bitstream manipulation of virtex ii pro devices,” in Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on, 2007, pp. 299 –304. [35] C. Lambert, T. Kalganova, and E. Stomeo, “FPGA-based Systems for Evolvable Hardware,” International Journal of Electrical, Computer, and Systems Engineering, vol. 3, no. 1, pp. 62–68, 2009. [36] K. Glette, J. Torresen, and M. Hovin, “Intermediate level fpga reconfiguration for an online ehw pattern recognition system,” in Adaptive Hardware and Systems, 2009. AHS 2009. NASA/ESA Conference on, 2009, pp. 19 –26. [37] Z. Vasicek, L. Sekanina, and M. Bidlo, “A method for design of impulse bursts noise filters optimized for fpga implementations,” in Design, Automation Test in Europe Conference Exhibition (DATE), 2010, 2010, pp. 1731 –1736. [38] F. Cancare, M. Santambrogio, and D. Sciuto, “A Direct Bitstream Manipulation Approach for Virtex4-based Evolvable Systems,” in Proceedings of thee IEEE International Symposium on Circuits and Systems, 2010, pp. 853–856. [39] D. B. Bartolini, F. Cancare, M. Carminati, and D. Sciuto, “Hera: Hardware Evolution over Reconfigurable Architecture,” in Proceedings of the 1st Computing in Heterogeneous, Autonomous ’N’ Goal-oriented Environments Workshop, 2011, p. to appear. [40] F. Cancare, M. Castagna, M. Renesto, and D. Sciuto, “A Highly Parallel FPGA-based Evolvable Hardware Architecture,” in Advances in Parallel Computing, vol. 19, 2010, pp. 608–615. [41] G. Harik, “Linkage Learning via Probabilistic Modeling in the ECGA,” 1999. [42] M. Pelikan, D. E. Goldberg, and E. Cant´u-Paz, “Linkage learning, estimation distribution, and bayesian networks,” Evolutionary Computation, vol. 8, no. 3, pp. 314–341, 2000.