False Path Problem - CiteSeerX

False Path Problem: Analyzing Hierarchical Designs of Sequential Circuits P. Altenbernd, J. Strathaus CADLAB Cooperation { University of Paderborn { Siemens-Nixdorf Informationssysteme AG Bahnhofstrae 32 { D-4790 Paderborn { Germany Tel.: ++49/5251/284-123, Fax.: ++49/5251/284-105, E-mail: [email protected]

Abstract Most existing path sensitizing algorithms are only available for at, combinational designs. We present a new dynamic path sensitizing algorithm for use in timing analysis of synchronous circuits. The algorithm processes hierarchical designs of sequential circuits. Edge triggered ip ops are modeled using impulse gates. The algorithm is based on a set of sensitizing conditions which include the properties of impulse gates. We introduce a new concept to deal with hierarchical design by recursive processing steps, and to reuse hierarchical information.

1 Introduction To ensure proper functioning of circuits, timing veri cation has to be performed. The goal of timing veri cation is to identify all paths in a circuit to check for timing problems. This can be performed by static timing veri ers without resorting to tedious simulation. Timing problems are located by static veri ers timing in paths (error paths). Because static timing veri ers do not take in consideration the functional behavior of the blocks of the circuit, an error path may never be sensitized by any input vector (false paths). False paths lead to a loss of accuracy in the analysis results, and hence hide the essential critical paths and the real problem areas of the developed circuit. A blind analysis may report a false path to be critical, and hence the designer wastes time in correcting errors which will never occur. To overcome this, sensitizing algorithms are applied. To decide whether a given path is a false path or not is called the sensitization problem. Static path sensitization techniques [2, 3, 11, 9] do not take delay times into account. Static sensitization techniques may fail because delay time information is not considered, and hence the dynamic behavior of the circuit due to the time is ignored. However, dynamic path sensitization techniques [5, 6, 7, 1] overcome the limitations of static methods. An additional problem is the analysis of hierarchical designs. Most methods are only applicable for at designs and/or generated information can't be reused. Others, like [9], try to abstract 1

the logical behavior of higher level blocks, which hides internal logic and timing behavior. Others, like [6], use converting algorithms which are very time consuming. D

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Figure 1: Presentation of a data path Furthermore, most sensitization methods are only applicable for combinational designs. These methods assume that paths delivered by the timing veri er do not include sequential circuits. Regarding static timing veri ers for analyzing synchronous circuits, like [10], we can claim that data paths include exactly one sequential circuit (see Fig. 1). The data path C1{FF1.C{ FF1.Q{FF2.D (notation: ... {[.]{ ...) shown in Fig. 1 stops at the data input of ip op FF 2. We can also claim that this kind of data paths always stop at data inputs of ip ops. This paper describes a new sensitizing algorithm which overcomes the limitations of existing methods to deal with hierarchical designs and sequential circuits. Our approach reduces the runtime on the batch analysis of hierarchical blocks. Furthermore, sequential circuits, in particular edge triggered ip ops, are modeled by using standard logic cells. The ecient heuristic algorithm represents a dynamic method based on our previous work [1] where other problems of sensitization techniques are considered. In section 2 some of the previously proposed sensitization methods are discussed. Section 3 introduces a new method how to model sequential circuits. The main algorithm for approximately computing the sensitization problem including sequential circuits is presented in section 4. In section 5 concepts for dealing with hierarchical designs are added. Experimental results are presented in section 6.

2 Related Work Considering static and dynamic algorithms in general, the proper analysis depends on sensitizing conditions which de ne a set of constraints to be hold at each gate along a sensitizable path. For example, static algorithms use incorrect sensitizing conditions. Some dynamic methods, like [5], fail at this point as well [1]. Post processing sensitization techniques [5, 11] are applied after all critical paths are determined by the timing veri er. In our previous work [1], we presented a post processing sensitizing algorithm. The proposed dynamic method approximately computes in linear time with respect to the size of the circuit if a given path is sensitizable or not. We restricted our view to correct sensitizing conditions, eciency, and the handling of feedback loops, only. We did not point out in detail how to deal with hierarchical designs and sequential circuits. To work with sensitizing algorithms dealing only with at designs, hierarchical circuits have to be attened rst. The step of converting hierarchical circuits to at designs can be skipped and some information can be reused if the sensitizing algorithm works directly on the hierarchical design. 2

A D B

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Figure 2: A simple combinational circuit To achieve this, some proposals, like [9], use truth table information or equivalent constructs, like BDDs (binary decision diagrams) [4] for higher level blocks. Truth table representations hide the internal logic and timing behaviors, which can be seen in the example of Fig. 2. If the delay information of the combinational circuit is not regarded in the example, the logical value of E is always 1. The corresponding truth table de nes for each possible input pattern of the circuit an entry that assigns 1 to E . Assume all the propagation delays of gates are 1 ns and all the signal delays are 0 ns. Changing input vector (A = 0; B = 1) to (A = 0; B = 0) toggles the value of E to 0 after 1 ns. This contradicts to the information contained in the truth table. The SLOCOP-II timing veri cation system [6] assures the correct handling of hierarchy. It uses an event graph to get only sensitizable paths for use in static timing veri cation. The event graph is converted by optimization algorithms into a graph including no false paths. But these algorithms are very time consuming. Reusing hierarchical information is not provided by any dynamic sensitization technique. But reusing hierarchical information in an ecient way improves runtime behavior when analyzing large designs. Perremans [7] models sequential circuits by methods that are restricted to static ip ops only. This method, like all the others, lack the handling of edge triggered ip ops that are frequently used in IC-design at present. The dynamic sensitization technique presented in this paper overcomes all mentioned shortcomings due to sensitizing conditions, hierarchical designs and sequential circuits. New sensitizing conditions including the properties of edge triggered ip ops are given as well as new concepts for dealing with hierarchical designs. Our concepts are embedded into a post processing algorithm. The algorithm analyzes hierarchical designs by recursive processing steps, and reuses as much hierarchical information as possible.

3 Modeling Sequential Circuits The logic behavior of a given circuit is modeled in path sensitizing algorithms by considering (N)AND- and (N)OR-gates. In this section we want to include sequential circuits into this model. Sequential circuits can be divided into two groups, using either static ip ops or edge triggered ip ops. Static ip ops are either unclocked, or level sensitive triggered. Modeling these kind of ip ops is trivial, since gates could be used to implement them. In Fig. 3 an example of an implementation of a high level sensitive triggered SR- ip op is shown. If a sensitizing algorithm is able to handle feedback loops, no problem occurs when running the algorithm on this 'quasi-logic design'. Modeling edge triggered ip ops is more dicult, since the behavior of these ip ops depends 3

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Figure 3: A high level sensitive triggered SR- ip op S

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Figure 4: A positive edge triggered SR- ip op on rising or falling edges. For modeling edge triggered ip ops in the same way as static ip ops it is necessary to deal with impulse gates. In Fig. 4 an example of the implementation of a positive edge triggered SR- ip op using an impulse gate is shown. The output of this impulse gate is 0 if the signal at its data input is 1 and the signal at its clock input is rising from 0 to 1. Otherwise, its output is 1. Four dierent kinds of impulse gates may be distinguished depending on its AND- or NAND-functionality and on its positive or negative triggering behavior. For example, the impulse gate of Fig. 4 has the NAND-functionality and is of course positive edge triggered.

4 The Sensitizing Algorithm After some de nitions in subsection 4.1 we present the basic algorithm in subsection 4.2 which deals with at designs. In section 5 we extend the algorithm to deal with hierarchical designs. We restrict our view without loss of generality to only two-input one-output gates.

4.1 Basic De nitions Our algorithm uses a hierarchical description of the circuit topology which has to be analyzed. This is a directed, vertex- and edge-labeled, hierarchical graph G = (V; E ), corresponding to the internal structure of the design. In Fig. 5 an example of this model structure is given. The graph shown in Fig. 5 depicts the internal structure at the top level in the hierarchical graph representing the given circuit. The structure of the design is represented by the vertices (pins) and edges (connections between pins) of the graph. A net is described by a set of directed edges from each sender to each receiver of the net. The delay information is re ected by labels on edges and vertices. Each block is represented by a subgraph. Every design is based on a set of basic cells (bottom level blocks). Each basic cell is described by its delay information mapped to labeled edges and vertices. As an extension to Fig. 5 sequential circuits are modeled via 4

Figure 5: A design circuit with its corresponding graph basic logic cells and impulse gates. De nition 1: A path is an acyclic sequence of vertices (p1 , p2 , ..., pn ) with: for all 1  i < n: (pi; pi+1 ) is an edge of the graph and p1 describes a primary input and pn describes a ip op input. This de nition ts to the kind of paths which are reported by timing veri ers (see Fig. 1). Note, all paths run over at most one clock input and over no data input. De nition 2: A boolean value x is called to be the control value [5] of gate g , i { x = 1 and g has a (N)OR-functionality or { x = 0 and g has a (N)AND-functionality. The notation is: x = cv(g). De nition 3: A boolean value x is called to be the non-control value [5] of gate g , i { x = 0 and g has a (N)OR-functionality or { x = 1 and g has a (N)AND-functionality. The notation is: x = ncv(g). Note, control values at gate inputs in uence gate outputs immediately. In the following, let P = (p1, ..., pn ) be the path to be checked for sensitizability, and g be a gate or an impulse gate on P . Furthermore let a and b be the inputs of g with a 2 P and b 62 P . If g is an impulse gate, a is assumed to be the clock input and b is assumed to be the data input. The output of g will always be denoted as c. De nition 4: TP (a) is the delay of the partial path of P starting from p1 and ending with a. Let v(u) denote the boolean value of vertex u. De nition 5: The worst-case arrival time of b is de ned as: 5

MAX fTP (b) j P 2 P (b)g if P (b) 6=  with P (b) = fP j P stabilizes v(b)g. 1 if P (b) =  De nition 6: We de ne reach(a; val) as TRUE, i there exists an input vector that forces v(a) to be val. Otherwise, reach(a; val) is de ned as FALSE. De nition 7: change(g ) is de ned as TRUE, i { g is a positive edge triggered impulse gate with: v(a) = 1 and reach(a; 0) = TRUE ,

wcat(b) =

or if { g is a negative edge triggered impulse gate with: v(a) = 0 and reach(a; 1) = TRUE . Otherwise, change(g) is de ned as FALSE. Intuitively, change(g) is TRUE if there exists a suitable pair (data signal, clock signal) that causes to change the value at the output of the impulse gate. De nition 8: A path P is called sensitizable, i for each gate or impulse gate g along P the following sensitizing conditions hold. If g is a gate: (C1) v (a) = ncv (g ) ) v (b) = ncv (g ) (C2) v (a) = cv (g ) ^ wcat(b) < TP (a) ) v(b) = ncv(g) If g is an impulse AND-gate: (C1') change(g ) ) v (b) = v (c) (C2') change(g ) ) v (c) = 0 If g is an impulse NAND-gate: (C1") change(g ) ) v (b) 6= v (c) (C2") change(g ) ) v (c) = 1 The intuitive meaning of this de nition of a sensitizable path P = (p1, ..., pn ) is that there exists any input vector that aects the value of pn by tracing a signal from p1 to pn along P .

4.2 Main Algorithm The worst-case arrival times are approximately computed in a preprocessing step [1]. The sensitizing algorithm can be divided into the scanning phase and the propagation phase. During the scanning phase the current path is traced from its source node towards its target node. For each gate g along the path the sensitizing conditions are evaluated. For example: If g is a gate and the value of a is ncv(g), then ncv(g) is assigned to b. After terminating the scanning phase the propagation phase begins: the assigned values are propagated to all reachable vertices with the D-algorithm. It is checked whether the conditions lead to inconsistencies (dierent values belonging to the same vertex), which proves this path not to be sensitizable under the considered assumptions. The sensitizing algorithm will be used rst assigning the value 0 to v(p1). If inconsistencies appear, a second attempt is started assigning 1 to v(p1). If an impulse gate is met within the scanning phase and change(g) is TRUE , the algorithm chooses the rst possible pattern (v(b); v(c)) satisfying the condition C1', or C1". For example: If the impulse gate has the ANDfunctionality, v(b) and v(c) are both set to 0. If inconsistencies appear within the propagation 6

phase, the algorithm reruns the scanning phase, but this time choosing the other possible pattern (v(b); v(c)) satisfying the condition C1', or C1". If no inconsistency appears in a certain attempt, the algorithm terminates and declares the path to be sensitizable. In a more formal way the algorithm to check one path for sensitizability may be de ned as follows. 1. v(p1) := 0; first := TRUE . 2. Scanning Phase: for all vertices u 6= p1 : v (u) := undef ; for all (impulse) gates g on P : if (g is a gate and v (a) = ncv (g )) v (b) := ncv (g ). if (g is a gate and v (a) = cv (g ) and wcat(b) < TP (a)) v (b) := ncv (g ) if (g is a gate) Assign the resulting output value of g . if (g is an impulse AND-gate) if (change(g ) = TRUE ) if (first = TRUE ) v(b) := 0; v(c) := 0; first := FALSE else

v(b) := 1; v(c) := 1; first := TRUE else v (c) := 0. if (g is an impulse NAND-gate) if (change(g ) = TRUE ) if (first = TRUE ) v(b) := 0; v(c) := 1; first := FALSE else

v(b) := 1; v(c) := 0; first := TRUE

else v (c) := 1.

3. Propagation Phase: Propagate the values to all reachable vertices and check for inconsistencies (D-algorithm). 4. if (inconsistencies and v(p1) = 0) if (first = TRUE ) v (p1 ) := 1 go to (2). if inconsistencies and v (p1 ) = 1, if (first = FALSE ) go to (2) else P is a false path. Otherwise, P is sensitizable. The use of the two phases is demonstrated in Fig. 6, considering the data path P1=FF1.C{ FF1.A{FF1.Q{G1{G2{G3{FF2.S (denoted by a solid line). The path attaches one impulse gate g. The propagation delays of all (impulse) gates are assumed to be 1 ns and all the signal delays are assumed to be 0 ns. The digits inside the boxes show the boolean values for starting the sensitizing algorithm with dierent values and for evaluating change(g). The upper digits represent assignments starting 7

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Figure 6: An example of a false path with value 0. In this case change(g) is FALSE . The two lower digits show the value starting with value 1. In this case change(g) is TRUE . The upper one of both shows the values satisfying condition C1" by assigning v(S ) := 0 and v(FF 1:A) := 1. The remaining lower digit represents the assignments resulting from v(S ) = 1 and v(FF 1:A) = 0. The scanning phase rst starts with assigning value 0 to v(FF 1:C ). Since change(g) is FALSE and the impulse gate has the NAND-functionality, condition C2" is evaluated. 1 is assigned to v(A). To deal with the following NAND-gate it is necessary to use condition C1. This forces its remaining input to 1 and its output to 0. The value 0 is inverted to 1 by gate G1. In the same manner the gates G2 and G3 are evaluated by the conditions C1 and C2, leading to v(G2:b) := 1, v(G2:c) := 1, v(G3:b) := 0, and v(G3:c) := 1. The dierent values at the connected inputs of G2 and G3 lead to an inconsistency. Thus, a second run with v(FF 1:C ) := 1 is needed. Now change(g) is TRUE . Since 1 is again assigned to v(A), the result of the second run is the same as the result of the rst run. However, in the third run 0 is assigned to v(A), which is the input of the following NAND-gate. The NAND-gate is evaluated by condition C2, and consequently its output value is assigned to 1. The gates G2 and G3 are evaluated by the conditions C2 and C1, leading to v(G2:b) := 1, v(G2:c) := 0, v(G3:b) := 0, and v(G3:c) := 0. This leads to the same inconsistency as detected in both runs before, which proofs path P1 to be non-sensitizable. If P1 is reported by the timing veri er to be an error path, the designer can ignore this information. FF1

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Figure 7: An example of a sensitizable path An additional example within the same circuit is shown in Fig. 7, where the path P2=FF1.C{ FF1.B{FF1.Q~ {G2{G3{FF2.S is traced. The values which are determined by the propagation phase are neglected in this example. Evaluating the sensitizing conditions in the case of starting with value 0 leads to assigning the other values as shown in Fig. 7. In this composition no inconsistency appears in the rst attempt, and therefore path P2 is considered to be sensitizable. In the following we discuss some details concerning the implementation of the above algorithm. Propagating values through the circuit (Step 3) can be achieved by applying the D-algorithm 8

[8]. We have shown [1] that a modi cation of the D-algorithm to a heuristic method reduces the run-time of the propagation phase to a linear behavior with respect to the dimension of the design. Determining the predicate change() (see De nition 7) which is used in the sensitizing conditions, depends on the evaluation of predicate reach(a; v) (see De nition 6). The problem of deciding if there exists an input vector that forces the value of vertex a to be v can be solved by using the (modi ed) D-algorithm as well. Then v is propagated through the circuit. If no inconsistency is detected we de ne reach(a; v) to be TRUE , and FALSE otherwise. One part of sensitizing conditions are the worst-case arrival times wcat(b). We presented an ecient abstraction of a determination of all worst-case arrival times in [1]. Flip ops are modeled in section 3 by gates and impulse gates. The corresponding subgraphs of such models are cyclic. A special regard on problems occurring with feedback loops within path sensitizing algorithms is also made by [1], where adequate solutions are given.

5 Hierarchy

Figure 8: Hierarchical sensitizing The algorithm presented in the last section is applicable on at designs. In this section we extend the algorithm to hierarchical circuits. We use the presentation of the circuit as a graph. For example, see again Fig. 5. Higher level blocks are represented by subgraphs. To deal with hierarchical designs our algorithm performs recursive steps. We de ne a function sensi(H; P; val) which performs the check for sensitizability (steps (2) and (3)) with respect to a given block H , a given path P inside the block, and a given start value val. In Fig. 8 a scenario for reaching a complex block B lying on the path within the scanning phase is shown. The initial call for activating the sensitizing algorithm inside of block A is sensi(A; (src; :::; dest); v), where (src; :::; dest) is the path inside A of interest. Let w be the actual logic value on the path at the input of B (see Fig 8). We continue by recursively calling the sensitizing algorithm with respect to B , to check the path inside of B for sensitizability. This is symbolized in Fig. 8 by a call of function sensi(B; (s; :::; t);v). Because this call includes the application of the propagation phase, the values at the some ports of B may change afterwards. After applying sensi() recursively with respect to B , the scanning phase goes on tracing the rest of the path (t, ..., dest) inside A. If the last vertex on the path has been reached, the propagation phase at the current level (in Fig. 8: block A) begins. The propagation phase needs not enter a hierarchical block in every 9

case. If a block is adjacent to the path (see block B in Fig. 8), the work of the propagation phase is already done by recursively calling sensi() with respect to B before. Blocks that are non-adjacent to the path (see Fig. 8 (C )) must always be analyzed by a recursive call of the propagation phase. Therefore we de ne a function propage(H ) to propagate all the values at the ports of hierarchy block H through its internal design. Applying propagate() to a block H may also change the values of some ports of H . If a call of propagate() leads to an inconsistency, the propagation phase at the current level has to stop and sensi() has to return this information to the next higher level. In1

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Figure 9: Use of hierarchy information Reuse of hierarchical information can be provided for dynamic sensitization techniques by path information and/or block information. Hierarchical path information is given with respect to a partial path inside a block. See for example Fig. 9. After analyzing the path In1{G1{B1.I2{ ... {B1.O1{Out1 there is some knowledge about the partial path B1.I2{ ... {B1.O1. This information may be reused, e. g. for analyzing path In2{G1{B1.I2{ ... {B1.O1{Out1. The reuse of path information depends on the delay time of the partial path preceding the partial path of interest, because dierent delay times can cause dierent results. If the delay times of In1{G1{B1.I2 and In2{G1{B1.I2 are dierent, partial path B1.I1{ ... {B1.O1 has to be reanalyzed. Hierarchical block information is given with respect to a block, and consists of a list of path informations. In the example the block information of B1 is given by the list of path informations about all partial paths starting at B1.I1, B1.I2, or B1.I3 and ending at B1.O1 or, B2.O1. The block information can be reused if a partial path inside a block of the same type is analyzed, e.g. for inquiring In3{G2{B2.I2{ ... {B2.O1{Out3 the knowledge about partial path B1.I2{ ... {B1.O1 can be taken. Block information is limited by the same constraints as path information (e.g. the delay times of In1(2){G1{B1.I2 and In3{G2{B2.I2 must be equal), and furthermore the worst-case arrival times of the primary inputs of the inquired block must be the same as of the referred block, e.g. wcat(B 1:I 1) = wcat(B 2:I 1), wcat(B 1:I 2) = wcat(B 2:I 2), and wcat(B 1:I 3) = wcat(B 2:I 3). From this may be claimed that situations where hierarchical information can be reused by a dynamic sensitization method are quite rare. Nevertheless there are some, and if utilized, the runtime of the sensitizing algorithm is improved. An utilization of hierarchical information in our recursive algorithm is obtained by the following concepts. The results delivered by a call of sensi(H; P; val) is stored into a data base. The data base key consists of the following elds: (H; Htype ; P; val; TP (Ij ); wcat(I1); :::; wcat(In)). 10

The result is stored in the following elds: (v(I1); :::; v(In); v(O1); :::; v(On)). (Notation: H : block name, P : path name, val: start value, I1; :::; In: inputs of H , Ij 2 P , Htype : type of H , O1; :::; On: outputs of H .) When executing sensi(), it is rst looked for hierarchical information in the data base, and if it is found, sensi() returns the stored result. Otherwise, the sensitizing algorithm recursively continues. In a similar way the propagation phase can utilize hierarchical information. The result of propage(H ) (\(in)consistent") is stored in the data base maintained by the following key: (Htype ; v(I1); :::; v(In); v(O1); :::; v(On)). (Notation: see above). In contrast to path and block information, this information is delay-independent and can be reused in any case.

6 Experimental Results # combinational cells # ip ops # hierarchy levels length of the longest path # timing paths # sensitizable timing paths (%) # false timing paths (%) no reuse: time for sensitizing [s] no reuse: average time for sensitizing [s] reuse: time for sensitizing [s] reuse: average time for sensitizing [s]

ADR 818 40 4 44ns 6133 644 (10.5) 5489 (89.5) 712.6 0.116 549.7 0.089

Table 1: Results The algorithm was implemented in C running under UNIX. The eciency of the algorithm depends mainly on the calculation of the worst-case arrival times, and on the implementation of the propagation phase. Using our proposals [1], the heuristic algorithm needs linear runtime with respect to the dimension of the circuit to check one path for sensitizability. We used the program to analyze a block (ADR) of a RAM-Disc-Controller. The topologic dates of ADR and the results delivered by our algorithm are presented in table 1. We used a Depth-FirstSearch-algorithm performing exhaustive search to deliver the timing paths. Then we run the sensitizing algorithm on each path. ADR includes several multiplexers, so that we detected a huge number of false paths (89.5%). The algorithm needs 0.116 CPU-seconds (6:5-MIPS machine) to analyze one path, which already is an acceptable trade-o between the computer resource and the time designers waste on false paths. We performed again the same analysis, this time reusing hierarchical information. The analysis time reduced to 77 %. This seems to be not very much progress. But as mentioned before we used an heuristic sensitizing algorithm, where a call of sensi(H; :::) needs linear runtime with 11

respect to the size of H if no information is reused. If information is reused, sensi(H; :::) needs about logarithmic runtime. The gap between linear and logarithmic behavior is quite small. In spite of our heuristic, the runtime of sensi(H; :::) within an exact sensitizing algorithm would be exponential. In this environment the eect of reusing hierarchical information would be more obvious.

7 Conclusion Most existing path sensitizing algorithms require at, combinational designs. We have developed a new method to include hierarchical designs depending as well on sequential circuits as on combinational circuits. We formulated new sensitizing conditions including the special issues of impulse gates. Hierarchical designs are handled by recursive processing steps, reusing hierarchical information. The sensitizing algorithm is implemented as a part of an interactive timing veri er. The experimental results show the algorithm to be applicable for practical use.

References [1] Peter Altenbernd and Jorg Strathaus. False Path Problem: Analyzing Hierarchical Designs of Sequential Circuits. In Proceedings of the IEEE Asia-Paci c Conference on Circuits and Systems, pages 6{11, 1992. [2] J. Benkoski, E. VandenMeersch, L. Claesen, and H. DeMan. Ecient Algorithms for Solving the False Path Problem in Timing Veri cation. In Proceedings of International Conference on Computer Aided Design, pages 44{47, 1987. [3] D. Brand and V. S. Iyengar. Timing Analysis using Functional Relationship. In Proceedings of International Conference on Computer Aided Design, pages 126{129, 1986. [4] R. E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Trans. Comput., C-35(8), 1986. [5] D. H. C. Du, S. H. C. Yen, and S. Ghanta. On the General False Path Problem in Timing Anlysis. In Proceedings of the 26th Design Automation Conference, pages 555{560, 1989. [6] P. Johannes, P. Das, L. Claesen, and H. DeMan. SLOCOP-II: A versatile timing veri cation system for MOSVLSI. In Proceedings of the European Design Automation Conference, pages 518{523, 1990. [7] S. Perremans, L. Claesen, and H. DeMan. Static Timing Analysis of Dynamically Sensitizable Paths. In Proceedings of the 26th Design Automation Conference, pages 568{573, 1989. [8] J. P. Roth. Diagnosis of Automata Failures: A Calculus and a Method. In IBM J. Res. Develop., pages 278{298, 1966. [9] K. Roy and J. A. Abraham. A Novel Approach to Accurate Timing Veri cation Using RTL Descriptions. In Proceedings of the 26th Design Automation Conference, pages 638{641, 1989. 12

[10] J. Strathaus and W. John. Critical Path Analysis for PCB Applications with Respect to Transmission Line Eects. In Proceedings of International Conference on Circuits and Systems, pages 127{131, 1989. [11] E. VandenMeersch, L. Claesen, and H. DeMan. A Timing Veri cation for Synchronous CMOS Logic. In Proceedings of ESSCIRC, pages 205{207, 1986.

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