Fast FPGA Prototyping of a Multipath Fading Channel Emulator via High-Level Design Jeng-Kuang Hwang*, Kuei-Horng Lin, and Jeng-Da Li, Juinn-Horng Deng Department of Communication Engineering Yuan-Ze University, Chung-Li City, Taiwan Email*:
[email protected] Abstract—A baseband multipath fading channel emulator is implemented on Xilinx XtremeDSP FPGA platform through high-level design. Without any RTL coding, fast prototyping of important modules can be done in the form of high-level Simulink models and Xilinx System Generator IP blocks. These modules include the white Gaussian noise generator (WGNG), Doppler filter, direct digital frequency synthesizer (DDFS), multi-rate interpolators, and multipath signal generator. Since all modules are designed in high level, the system parameters and configuration can be easily changed as desired. The FPGA emulator have been tested at a sampling rate of 30 Msps, and all the measured signals are well coincides with the simulation results, thus verifying the correctness of the design. I.
INTRODUCTION
In the past decade, highly configurable hardware platforms have become widely adopted for fast prototyping of the digital communication infrastructure rapidly. While there are many alternatives available for implementing the various baseband functions, FPGA provides many attractive merits in performance, power consumption and re-configurability [1,2]. When implementing an algorithm on FPGA hardware, the traditional approach is usually based on manual RTL-level design of each system module in VHDL or HDL codes. However, this approach suffers from low productivity, poor flexibility, and hardness to maintain. Recently, a rival topdown design flow have become more and more mature, which is based on high-level Simulink block-diagram model using existing highly integrated intellectual property (IP) to develop various system modules. In so doing, the RTL codes can be generated automatically by powerful EDA tools such as Xilinx System Generator. Hence, the designer can focus on architectural and algorithmic issues that are the most distinctive and valuable part in the design. Furthermore, with such a high-level modular design and fast FPGA-based prototyping approach, we can carry out algorithm verification, word-length optimization, and system integration in a more nature way and from the very beginning of the design process. In the paper, we adopt the above mentioned a high-level modular design approach to develop a real-time and low-cost baseband multipath fading channel emulator on the Xilinx XtremeDSP FPGA platform. In wireless design, it is well known that the realistic wireless channels can impose on the The research work was supported by the National Science Council, R.O.C., under the Grant NSC 95-2219-E-155-003
radio signal various channel effects. The most important two effects are multipath propagation characterized by power-delay profile and delay spread, and random signal fading characterized by Doppler spectrum and Doppler spread [3]. The former may induce intersymbol interference, and the later can incur a significant SNR loss, as compared to the AWGN channel case. So a realistic multipath channel fading emulator is of crucial importance in testing and performance evaluation of any wireless system under development. Unfortunately, commercially available channel emulators are often too expensive for ordinary design houses to offer. Thus, a real-time and low-cost channel emulator is highly desired for modeling and simulating the above channel effects. In this continued work [4], a high-level modular design approach is applied to meet the testing need of channel emulation in a most cost-effective way. We not only illustrate the rival design flow, but also provide real-world measurements to prove the correctness and great flexibility of the implemented FPGA hardware. It is shown that the design and implementation process is quick, neat, accurate, and can always stay at high level that obviates any RTL coding. This paper is organized as follows. In Sec.2, the overall emulator structure is briefly described. In Sec. 3 and 4, the algorithms and blocks of those important modules are described individually. In Sec. 5, we present and compare some MATLAB simulation results and corresponding realworld measurement results. In Sec. 6, concluding remarks are made. II.
THE OVERALL CHANNEL EMULATOR STRUCTURE
In [4, ISPACS 2006], the authors have proposed highly efficient structure and associated algorithms for FPGA implementation of multipath fading channel emulator. The small-scale wireless channel is usually modeled as a linear time-varying (LTV) system that produces the baseband received signal samples expressed as follows: P −1
R ( nTs ) = ∑ α i gi ( nTs ) s ( nTs − τ i )
(1)
i =0
where P is the number of paths, {gi(nTs), i=0,1,…,L-1} denotes the L independent fading sequences with unity power and the same sampling rate as the channel input signal s(nTs), {αi, τi} denotes the power-delay profile of the channel.
Moreover, the complex fading sequences are assumed to have Rayleigh or Rician distribution for the envelope fading and the power spectrum density (PSD) like Jakes [3] with a possible spectral line due to LOS component. Fig.1 shows the overall channel model to be implemented in FPGA. S% (nTs − τ 0 ) S% ( nTs )
S% (nTs − τ 1 )
Mulitpath Delay Generator
Fading Generator
R% ( nTs )
S% (nTs − τ P −1 )
g 0 (nTs )
α0
Interpolator 0
α1
Interpolator 1
αP-1
Interpolator P-1
g1 (nTs ) g P −1 (nTs )
Fig.1 The overall structure of the baseband channel emulator
Then the complex white Gaussian random process can be generated as follows:
W (n) = f ( X 1 ( n ) ) g c ( X 2 ( n ) ) + j × f ( X 1 ( n ) ) g s ( X 2 ( n ) ) (3) We can store the functions in (2) in ROM look-up table. Hence, the complexity of overall structure, chip area and hardware resource is reduced. Besides, there is an 4th-accumulator in front of the output of Danger’s WGNG [5] for summing the pseudo random numbers to better approach the ideal Gaussian distribution, but it may cause transient phenomenon. Consequently, we use a 4:1 downsampling device to solve the problem. Before the downsampling, the WGNG sampling rate is set at 12fm, where fm is the maximum Doppler frequency, and after downsampling, the WGNG output sampling rate is 3fm, which satisfies the sampling theorem and avoids aliasing in subsequent Doppler spectrum shaping in terms of Doppler filter. B. Doppler Filter Instead of using an FIR Doppler filter, we adopt an IIR Doppler filter with coefficients given in Table 1. The output PSD is shaped into Jake’s Doppler Spectrum as follows: 2π f m 2 ⎧ if ω ≤ ωm = ⎪ 2 (5) 2 fs S (ω ) = ⎨ ωm − ω
III. HIGH-LEVEL MODULAR DESIGN
Traditional analog fading emulator often used Jakes’ sumof-sinusoid method [3] for fading processes generation. Although it is less complex, it generates correlated fading processes. In this paper, we use the alternative structure shown ⎪ 0 otherwise ⎩ in Fig .2 to give better statistical properties in distribution, To reduce coefficients quantization error, we further convert autocorrelation and cross-correlation. Besides Rayleigh fading, the filter into a lattice-ladder structure, as is shown in Fig.3. Racian fading can also be generated by specifing an incident angle θ and Rician k factor for the LOS component. Hence, we Table 1 The IIR filter coefficients can divide the Rayleigh/Rician fading generator into 3 subsystems. They are white Gaussian noise generator (WGNG), bi i ai Doppler filter, and direct digital frequency synthesizer (DDFS). 0 1 2 3 4
cos(2π f m cos θ (l )t )
κ (l ) κ (l ) + 1
− fm
fm
Σ
1
g I (t )
κ (l ) + 1
Σ
1
κ (l ) + 1 − fm
Σ
fm
1 1.74287599025769 2.33391801449333 1.34276412323384 0.59552189482577
0.71724504566570 1.70502826332690 2.25142875250905 1.51287592873974 0.53630149817269
g (t ) = g I (t ) + jgQ (t )
gQ (t )
κ κ (l ) + 1 sin(2π f m cos θ (l )t ) (l )
Fig .2 The Rayleigh/Rician fading generator
Fig.3 The 4th-order lattice-ladder IIR filter structure
A. White Gaussian Noise Generator The WGNG hardware structure is based on the Box-Muller (BM) algorithm and Danger’s WGNG model [5]. It has to produce two sets of i.i.d U(0,1) distributed random sequences {X1(n), X2(n)} first. Define the following functions: ⎧ f ( x ) = − ln ( x ) ⎪⎪ ⎨ g c ( x ) = 2 cos ( 2π x ) ⎪ ⎪⎩ g s ( x ) = 2 sin ( 2π x )
(2)
C.
Direct Digital Frequency Synthesizer
In order to switch the mode from Rayleigh to Rician fading, a pair of quadarture sinusoid waveforms generated by DDFS is included for simulating the LOS component. The LOS to nLOS power ratio is controlled by the Rician k factor. The DDFS shown in Fig.4 is based on the memory-saving design [6] which can save up to 75% of the ROM LUT size.
signal with fractional delay, where the M+1 fixed FIR filters {Hm(z), m=0,1,…,M} are optimized as in [8,9]. In this paper, we adopt the cubic Farrow structure with M=3.
HM ( z)
HM−1( z)
... μ
Multi-rate Interpolator
Interpolator is used to raised the low sampling rate of the fading process to that of the input/output sampling rate. Here, the sampling rate conversion is done by multi-stage interpolation [7] for reducing hardware complexity. As shown in Fig. 5, the multi-stage interpolator consists of a fixed part and an adjustable part. For the fixed part, we use two cascaded poly-phase FIR interpolators with individual interpolation factors of 2 and 5, respectively. This combination provides good interpolation accuracy and uses minimum number of filter taps. After passing these two stages, the interpolated fading processes become quite smooth with an oversampling ratio of 30. Hence, it allows us to use only simple linear interpolator of appropriate ratio I for the remaining task. Shown in Fig.6 is a linear interpolator with a ratio I=100, where a and b denotes two consecutive low-rate samples to be interpolated, and β is the increment.
Fig .5 The multi-stage interpolation process
b−a 100
H0 ( z)
...
...
Fig .4 The DDFS module
D.
HM−2 ( z)
β=
β
Fig .7 The block diagram of the Farrow Structure for fractional delay generation
IV. SIMULATION AND EXPERIMENTAL RESULTS Following the above a high-level design with the aid of Xilinx System Generator, the whole multipath channel emulator has been successfully implemented on Xilinx XtremeDSP FPGA developmental board which hosts a Virtex4 xc4vsx35 chip. Since the FPGA resource is limited, only two-path channel is realized. The input/output sampling rate is set at 20 MHz. For a demonstrative channel simulation, we set the Doppler frequency fm at only 5Hz to clearly examine the fading channel variation. Jakes fading process is first simulated in MATLAB floating-point program, to which we can compare the fixed-point hardware simulation result produced by Xilinx System Generator. As is shown in Fig .7, it is seen that the two simulated Doppler spectra match each other closely. After the above verification stage, we then downloaded the whole channel emulator to the FPGA board, and applied a testing baseband QPSK signal with raised cosine pulse shaping to the input SMA connectors. The hardware setup is shown in Fig. 8a. Under flat fading environment, the dynamic output I/Q plot with two snapshots in Fig.8 clearly shows the random amplitude and phase variation caused by the time-varying fading. Finally, we test the two-path signal generator according to the setup in Table 2, where the sampling period Ts is 0.05 μs. Hence, the differential path delay is 1.05e-7 sec. As is shown in Fig. 9, the real-world measurement result is still in good coincidence with the Matlab simulation result. Finally, the major hardware parameters are listed in Table 3. Table .2 The parameters of the two path delays
Fig .6 The block diagram of a linear interpolator with ratio I=100.
E.
Multipath Signal Generators with fractional delay
To generate fine-resolution multipath delays, we divide each path delay τi as
τ i = ( Ki + μi )Ts
(8)
where Ki and μi represent the integer part and fractional part of the delay normalized to the input sampling period Ts, respectively. As shown in Fig. 7, the Farrow structure with the interpolation parameter 0
