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Fast Programming/Erasing of Thin-Oxide EEPROMs Roberto Versari, Augusto Pieracci, and Bruno Riccó Abstract—This brief demonstrates that conventional thin-oxide EEPROM cells can be programmed (erased) in the nanosecond time scale with voltages lower than 18 V still featuring data retention times of the order of a few hours after 100K program/erase (P/E) cycles. Our results suggest that thin-oxide nonvolatile (NV) memory devices can be suitable for fast read/write dynamic applications, at least when high cycling endurance is not a primary specification. Index Terms—High-voltage tunneling, programming/erasing speed, read-disturb lifetime, thin-oxide EEPROMs.
Fig. 3. Total time history of RF output power at section output guide.
z
= 5 0 cm of the :
output at 6.7 GHz. The system has mechanical simplicity and circular symmetry for easy machining and assembly as well as a solid anode block for ease cooling in long pulse operation. Such characteristics make the device practical from the view point of cost and flexibility, allowing simple procedures for scaling power and frequency. Design at other frequencies or using a larger number of concentric beams is likely achievable. Finally, it is worth mentioning that the monotron proposed here is shown to be immune to mode competition even operating in the radial high order TM04 ( 04 : ) mode. About the neighboring competing modes TM14 ( 14 : ) and TM24 ( 24 : ), the selected operating TM04 mode resists the onset of competition as the relative eigenfrequency separation j 04 0 m4 j/ 04 is significantly wide, giving 13.0% and 25.5% for m and 2, respectively. This is in sharp contrast with TE0n gyrotrons, in which the azimuthally symmetric TE0n mode suffers from almost unavoidable mode competition with TE2n modes, especially for n in long pulse operation [5]. In the case n , the operating conditions of the TE04 mode overlap with those of the lateral inferior TE24 mode due to a very narrow relative frequency separation (1.1%), which is much smaller than the corresponding mode separation in a TM04 monotron. Gyrotrons can provide higher average power levels at submillimeter wavelengths and are more efficient than the monotron. But the device presented here finds application in spherical tokamaks, where high-power microwave sources in the 5–10 GHz range are required to drive current and heat a high-pressure plasma confined by a low magnetic field [6].
= 11 7915 = 13 3237
= 14 7960
=1
=4
3
REFERENCES [1] J. J. Müller and E. Rostas, “Un générateur à temps de transit utilisant un seul résonateur de volume,” Helv. Phys. Acta, vol. 13, pp. 435–450, Oct. 1940. [2] J. J. Barroso, K. G. Kostov, and I. G. Yovchev, “A proposed 4 GHz, 60 kW transit-time oscillator at 18 kV beam voltage,” IEEE Trans. Plasma Sci., vol. 26, pp. 1520–1525, Oct. 1998. [3] J. J. Barroso and K. G. Kostov, “A 5.7 GHz, 100 kW microwave source based on the monotron concept,” IEEE Trans. Plasma Sci., vol. 27, pp. 580–586, Apr. 1999. [4] V. P. Tarakanov, User’s Manual for Code KARAT. Springfield, VA: Berkeley Research Associates, Inc., 1994. [5] V. L. Granatstein, B. Levush, B. Danly, and R. K. Parker, “A quarter century of gyrotron research and development,” IEEE Trans. Plasma Sci., vol. 25, pp. 1322–1335, Dec. 1997. [6] G. O. Ludwig and ETE team, “The ETE spherical tokamak project,” INPE, São José dos Campos, Brazil, Tech. Rep. 7301-RPQ/699, Aug. 1999.
I. INTRODUCTION Memory devices are becoming increasingly important in the consumer electronic market, where digital standards are nowadays driving the technology evolution [1]. For such applications both nonvolatile (NV) memories and DRAMs are in general required in order to satisfy the opposite requirements of storing the embedded software and of high data transfer rates toward the processor core. In fact, the bandwidth of NV memories is limited by programming and erasing time and is typically in the range of Mbit/s, three orders of magnitude lower than DRAMs data transfer rates [2], [3]. The TP=E essential limitation to the decrease of programming/erasing (P/E) time in NV memories exploiting Fowler–Nordheim (FN) tunneling for both P/E is due to the degradation of the tunnel oxide at the high voltages corresponding to the lower TP=E for a given threshold voltage window VTH . Oxide degradation results in a high leakage current at the voltages typical of memory reading, hence in low charge retention on the floating gate (FG) [4]–[8]. Recently, the tradeoff between TP and read-disturb lifetime tF , (i.e., retention time under read conditions), has been studied on flash memory cells featuring a tunnel oxide thickness TOX nm and FG to control gate (CG) coupling coefficient fc : [9]. The study has shown that after 50K P/E cycles with a programming pulse width of 20 ns the cells still exhibit tF in excess of ten years. However, the high program voltage (>26 V) required to achieve the target VTH in the nanosecond time scale might be unpractical for real memory arrays. In this brief, we explore the dependence of tF on TP=E in conventional EEPROM cells, with the following basic differencies with respect to the work of [9] the following. 1) The EEPROM cells feature TOX : nm and fc : , thus allowing fast P/E operation in the nanosecond time scale with voltages lower than 18 V. 2) The experimental set-up has been modified in order to perform both the program and erase operation in the nanosecond time scale during cycling. In particular, programming and erasing times have the same value TP=E TP TE . Our results show that, with conventional TP=E in the millisecond range, tF values of tens of hours are obtained after 10K P/E cycles, because of the thin tunnel oxide of the cells [5], [6]. However, tF decreases only of a factor of 3 for a six order of magnitude decrease of TP=E . As a result, after 100K P/E cycles with TP=E ns, tF is still > 3 h.
1
06
=8
1
= 65
=
= 0 75
=
20
Manuscript received October 23, 2000. The review of this brief was arranged by Editor G. Groeseneken. The authors are with DEIS, University of Bologna, 40136 Bologna, Italy (e-mail:
[email protected]). Publisher Item Identifier S 0018-9383(01)02380-2.
0018–9383/01$10.00 © 2001 IEEE
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Fig. 1. Schematic representation of the double-poly EEPROM cells of this work.
Fig. 3. Measurement of the high-voltage pulses generated by the HP8160A pulse generator with and without adaptation. T 20 ns and V = 8 V are the nominal pulse width and amplitude values programmed in HP8160A, repsectively. In the case of adaptation the output signal has been multiplied by two for comparison purpose.
=
Fig. 2. Schematic representation of the experimental set-up used for the cycling experiments of this work.
This suggests the possibility to use thin-oxide, tunnel-based NV memories for fast read/write dynamic applications with refresh times significantly longer than those typical of DRAMs, at least when high cycling endurance is not a primary specification. II. DEVICES AND EXPERIMENTS The devices of this brief are conventional double-poly EEPROMs featuring: TOX = 6:5 nm; channel length and width L = 0:5 m and W = 0:9 m, respectively. A select transistor with gate oxide of about 18 nm, L = 0:8 m, and W = 0:9 m allows access to the drain terminal of the cell, as shown in Fig. 1. The tunnel oxide has been grown at T = 900 C in N2 =O2 ambient, and then subjected to nitridation at T = 1000 C. Using the equivalent transistors available on the same wafer, the FG to CG coupling coefficient of the cells has been experimentally determined with the subthreshold slope technique and found to be 0.75 [10]. Both program and erase operations are performed by applying a high-voltage pulse with positive or negative polarity to the CG with the select transistor biased at VST = 5 V and all other terminals grounded, as shown in Fig. 2. The absolute values of programming and erasing voltages (VP and VE , respectively) range from 10 to less than 18 V for TP=E = 30 ms and 20 ns, respectively. Differently from [9], the pulse generator HP8160A is programmed via the HP-IP bus by the semiconductor parameter analyzer HP4156A in order to perform both programming and erasing operations in the nanosecond time scale. To achieve P/E voltages higher than 10 V, the output of HP8160A must not be adapted [11], [12]. As can be seen in Fig. 3, this determines a significant distortion of the P/E pulse at the CG of the cells at the lower TP=E considered in this work, producing a maximum output
Fig. 4. (a) Measured read-disturb characteristics of the EEPROM cells before , where the data retention time t is and after 10K cycles with different T reported as a function of the inverse read-disturb voltage V . (b) Measured t after 10K cycles as a function of T for V = 2:5 V.
voltage higher than expected and oscillations of the pulse base level value. However, since the input capacitance of the oscilloscope is greater than that of the EEPROM cells, the maximum voltage applied to the CG is certainly lower than 18 V also for TP = 20 ns (while the erase operation requires VE 016 V for a nominal TE = 20 ns). Furthermore, the oscillations of the pulse base level value are lower than 3.5 V, hence they are not expected to significantly degrade or affect the state of the cells. For the higher values of TP=E used in this work the effects of gate pulse distortion decrease until they become negligible for TP=E 100 s. During cycling, the threshold voltage VTH of the cells has been measured connecting the CG to a SMU of HP4156A by means of a switch
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This suggests the possibility to use thin-oxide, tunnel-based NV memories for fast read/write dynamic applications with refresh times significantly longer than those typical of DRAMs, at least when high cycling endurance is not a primary specification. From this point of view, of course, the EEPROMs cells used in this brief have the drawback of a large area, particularly compared with DRAMs. However, the essential features of oxide degradation studied in this work are expected to be essentially independent of device structure (as confirmed by preliminary results obtained with Flash cells programmed and erased by tunneling toward and from the device channel), thus suggesting the possibility of innovative applications of competitive NV devices. ACKNOWLEDGMENT Fig. 5. Measured endurance characteristic of the cells during 100K cycles with 20 ns. V and V have not been modified during cycling to nominal T compensate for eventual window closure.
=
also controlled by HP4156A, as shown in Fig. 2. VTH has been defined as the CG bias required to provide a 0.1-A drain current for VDS : V, in order to avoid disturbances due to the measurement itself. We have conventionally considered the erased VTH V, while V. tF has been measured as the time reafter programming VTH quired to achieve a VTH : V starting from the initial VTH in correspondence of the read-disturb voltage (VRD ) applied to the CG during the measurements [7], [13].
= 01
=0
=4 1 =05
=0
III. EXPERIMENTAL RESULTS As a first step, we have selected a set of devices featuring the same virgin read-disturb characteristics, as shown in Fig. 4(a), in order to avoid differences due to the technological process. Then the virgin cells have been stressed with 10K P/E cycles from VTH V to VTH V and with TP=E ranging from 30 ms to approximately 20 ns. As can be seen in Fig. 4(a), because of the relatively thin tunnel oxide of the cells considered in this study [5], [6], tF is significantly reduced even after 10K cycles with conventional TP=E ms. However, as clearly shown in Fig. 4(b), tF decreases only of a factor of 3 for a six order decrease of TP=E , so that tF h can be measured for VRD : V when TP=E ns. Such a retention time is small compared to the ten years data retention of conventional NV memories, but is more than three orders of magnitude greater than typical DRAMs refresh time. These results have been checked also after 100K P/E cycles under the fastest programming condition TP=E ns. In this case, tF decreases from 13 h after 10K cycles to about 3 h after 100K cycles for the same VRD : V, demonstrating a less than proportional dependence of data retention on the number of P/E cycles. Regarding the endurance characteristics of the cells, Fig. 5 shows that the threshold voltage window closure is negligible during the 100K cycles. It has been also found that the drain current and transconductance characteristics of the cells are not degraded after the cycling.
=0
=4
= 30
=25
13
= 20
= 20
= 25
IV. CONCLUSIONS This brief has shown that EEPROM cells with a thin 6.5-nm tunnel oxide and high fc : can be programmed/erased in the nanosecond time scale with absolute voltage values lower than 18 V. The read-disturb lifetime of these cells after 100K fast P/E cycles is in the range of a few hours, which is several orders of magnitude greater than typical DRAMs refresh time.
= 0 75
The authors would like to thank ST-Microelectronics in Agrate-Brianza, Italy, for constant support and for providing the devices used in this work. REFERENCES [1] R. Kramer, “Consumer electronics as silicon engine,” in IEDM Tech. Dig., 1999, pp. 3–7. [2] B. Riccó, G. Torelli, M. Lanzoni, A. Manstretta, H. Maes, D. Montanari, and A. Modelli, “Nonvolatile multilevel memories for digital applications,” Proc. IEEE, pp. 2399–2421, Dec. 1998. [3] T. Watanabe, R. Fujita, K. Yanagisawa, H. Tanaka, K. Ayukawa, M. Soga, Y. Tanaka, Y. Sugie, and Y. Nakagome, “A modular architecture for a 6.4 Gbyte/s 8 Mb DRAM-integrated media chip,” IEEE J. Solid State Circuits, pp. 635–640, May 1997. [4] K. Naruke, S. Taguchi, and M. Wada, “Stress induced leakage current limiting to scale down EEPROM tunnel oxide thickness,” in IEDM Tech. Dig., 1988, pp. 424–427. [5] R. Moazzami and C. Hu, “Stress-induced current in thin silicon dioxide film,” in IEDM Tech. Dig., 1992, pp. 139–141. [6] T. Endoh, K. Shimizu, H. Iizuka, and F. Masuoka, “A new write/erase method to improve the read disturb characteristics based on the decay phenomena of stress leakage current for flash memories,” IEEE Trans. Electron Devices, pp. 98–104, Jan. 1998. [7] Y. King, T. King, and C. Hu, “A long-refresh dynamic/quasinonvolatile memory device with 2 nm tunneling oxide,” IEEE Electron Device Lett., pp. 409–411, Aug. 1999. [8] H. C. Wann and C. Hu, “High-endurance ultra-thin tunnel oxide in MONOS device structure for dynamic memory application,” IEEE Electron Device Lett., pp. 491–493, Nov. 1995. [9] R. Versari, A. Pieracci, D. Morigi, and B. Riccó, “Fast tunneling programming of nonvolatile memories,” IEEE Trans. Electron Devices, pp. 1285–1287, June 2000. [10] W. L. Choi and D. M. Kim, “A new technique for measuring coupling coefficients and 3-D capacitance characterization of floating gate devices,” IEEE Trans. Electron Devices, pp. 2337–2342, Dec. 1994. [11] R. Bellens, P. Heremans, G. Groeseneken, H. E. Maes, and W. Weber, “The influence of the measurement setup on the enhanced AC hot carrier degradation of MOSFETs,” IEEE Trans. Electron Devices, p. 310, Jan. 1990. [12] B. Riccó and A. Pieracci, “Tunneling bursts for negligible SILC degradation,” IEEE Trans. Electron Devices, pp. 1497–1499, July 1999. [13] J. D. Blauwe, J. V. Houdt, D. Wellekens, G. Groeseneken, and H. Maes, “SILC related effects in flash E PROM’s—Part II: Prediction of steady-state SILC-related disturb characterstics,” IEEE Trans. Electron Devices, pp. 1751–1760, Aug. 1998.
