Fault Models and Tests for Multi-Port Memories - Semantic Scholar

Fault Models and Tests for Multi-Port Memories Master Thesis Sad Hamdioui

Section of Computer Architecture and Digital Technology Department of Electrical Engineering Faculty of Information Technology and Systems Delft University of Technology The Netherlands

October 1997

Delft University of Technology Faculty of Information Technology and Systems Department of Electrical Engineering

Type: Master Thesis

Title: Fault Models and Tests for Multi-Port Memories

Date: October 1997

Author: S. Hamdioui

Supervisor: Prof. Dr. Ir. A.J. van de Goor

Number of Pages: 112

Section: Computer Architecture and Digital Technology

Technical Report number: 1-68340-28(1997)11

Abstract: In this report, the eects of simultaneous memory access

Key words: Multi-port memories, memory fault models, march tests,

on the fault modeling for multi-port memories are investigated. New fault models have been de ned. March tests for such faults are presented for two-port memories. The obtained tests are of order O(n2), whereby n is the size of the memory. This makes them less practical for larger multi-port memories. In order to reduce the complexity of the tests, the topology of the memory has to be taken into account. A rst approach based on presumed topologies shows that the time complexity of the tests can be reduced to O(n). test length, test coverage.

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Acknowledgements Being close to graduate as an electrical engineer, which has been my dream for many years, I would take this opportunity to thank the people that helped me. First of all, I would like to thank my supervisor Prof. Dr. Ir. A.J. van de Goor, who gave me the opportunity to do this research, for his support, exibility, help, and feedback. I would also like to thank the members of my committee thesis, namely Prof. Dr. Ir. P.M. Dewilde and Dr. Ir. J.Th. van der Linden. Moreover, I would like to thank all members of "Computer Architecture and Digital Technology" section, who together create a very friendly and exible environment for a successful research. Furthermore, I would like to thank my parents Ahmed and Mimount, who created for me the opportunity to complete my study at the Delft University of Technology, for their support and encouragement. I would also like to thank my aunt Mimount and her husband who without their help I couldn't get to this university.

Sad Hamdioui Delft, The Netherlands

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Summary Memories are an integral part of any computer system. They can be single or multi-port. A single-port memory is one which can only be read or written via a single circuit path, while a multi-port memory is one having multiple ports that are to be used to access memory cells simultaneously and independent of each other. Multi-port memories are widely used, namely in multi-processor systems, in special applications in telecommunication, etc. Testing those memories is getting more important since they are often embedded in very large scale integrated circuits; that means, that the address, data, and read/write circuits can not be directly controlled or observed through the chip's input/output pins. Current microprocessors contain many embedded multi-port memories. From the point of view of economics, it has been shown that with increasing test quality, the total cost of the product is minimized for some test quality. Therefore, ecient tests are needed in order to insure high quality products with reduced cost. Although multi-port memories have been in use for a relatively long time, little has been published about testing them. Tests for single-port memories do not cover all faults of multi-port memories. Therefore, adequate faults models are needed and still remain to be established, as well as a test strategy in terms of which faults can be detected through a test for single-port, versus a test for multiple ports. These fault models have to take into account the eect of simultaneous access to the memory; and their tests have to be practical for real purposes, that means that the test time has to be linear with the memory size, for larger memories. In this thesis, the functional and the electrical models for single- and multi-port memories have been reported. A complete set of fault models for single-port as well as for two-port memories has been described. These faults have been divided (for both types of memories) into memory cell array faults, address decoder faults, and read/write logic faults. The latter faults have been mapped (for both types of memories) onto memory cell array faults The memory cell array faults for single-port memories are analyzed in more detail and classi ed into faults which are strong (i.e., always fully sensitize a fault), and faults which can be weak (i.e., can partially sensitize a fault). As a consequence, a fault can well be sensitized when several weak faults occur simultaneously. This is the case in multi-port memories, since they allow for simultaneous multiple access. Based on additive combined fault eects of weak faults, several new memory cell array fault models have been developed for multi-port memories. Of course, these models take into account the resulting eect from simultaneous access of the memory. In order to establish a set of fault models for address decoder faults in two-port memories, the interference (i.e., shorts) between wires of the two dierent ports has been analyzed. First, iii

iv shorts have been injected in the electrical circuits of the two address decoders; thereafter, functional faults have been derived based on the electrical behavior of the circuits in the presence of shorts. Functional tests to detect memory cell array faults as well as address decoder faults have been presented for two-port memories. The fault models, and their tests have been simpli ed based on a port mix and on a presumed topology of the memory. The test time of the developed tests is of the order O(n2 ) for memory cell array faults and O(n) for address decoder faults; whereby n is the size of the memory. That implies, that the test time of tests, which detect memory cell array faults, is exponentially proportional with the number of ports. This makes the developed tests less practical for larger multi-port memories. In spite of reducing the fault models and tests on the basis of port mix, the test time remains exponentially proportional with the number of ports. To reduce the test time to linear tests, the simpli cation has to be based on layout information, which can be presumed, or better based on industrial data. However, this is hard to get. In this thesis, a presumed topology is used to reduce the complexity of the tests to O(n); i.e., linear with the size of the memory. It should be noted, that the introduced fault models for memory cell array faults in multi-port memories have been based on fault models of a single port memories. These fault models have to be veri ed industrially, such that their validity can be investigated. In addition, the possibility of the existence of other faults which do not have their origin in single port memories, remains to be investigated. This can be done by using Inductive Fault Analysis, which is a systematic procedure to predict the faults in integrated circuits by injecting spot defects in the stimulated geometric representation of the circuit.

Contents Acknowledgements 1 Introduction 1.1 1.2 1.3 1.4

Test importance . . . . . . . . . . Test economics . . . . . . . . . . . Tests and semiconductor memories Outline of the thesis . . . . . . . .

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2.1 Memory models . . . . . . . . . . . . . . . 2.2 Structures of SP memories . . . . . . . . . 2.2.1 Functional model of SP memories . 2.2.2 Electrical model of SP memories . 2.3 Structures of MP memories . . . . . . . . 2.3.1 Functional model of MP memories 2.3.2 Electrical model of MP memories .

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3.1 Functional faults for SP memories . . . . . . . . . . . . 3.1.1 SP memory cell array faults . . . . . . . . . . . 3.1.2 SP address decoder faults . . . . . . . . . . . . . 3.1.3 Faults in the read/write logic . . . . . . . . . . . 3.1.4 Linked faults . . . . . . . . . . . . . . . . . . . . 3.2 Functional faults for two-port memories . . . . . . . . . 3.2.1 2P memory cell array faults . . . . . . . . . . . . 3.2.2 Reasonableness of 2PFs . . . . . . . . . . . . . . 3.2.3 2P memory address decoder faults . . . . . . . . 3.2.4 Faults in read/write logic . . . . . . . . . . . . . 3.2.5 Summary of functional faults in 2P memories . . 3.2.6 Classi cation of functional faults in 2P memories

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2 Structures of memories

3 Functional faults for memories

4 Tests for two-port memories

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4.1 Notation for march tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2 Conditions for detecting 2PFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.2.1 Conditions for detecting 2PF1s . . . . . . . . . . . . . . . . . . . . . . . . 58 v

CONTENTS 4.2.2 Conditions for detecting 2PF2s 4.2.3 Conditions for detecting 2PF3s 4.3 Tests for 2PFs . . . . . . . . . . . . . 4.3.1 Test for the 2PF1 fault class . 4.3.2 Test for the 2PF2 fault class . 4.3.3 Test for the 2PF3 fault class . 4.3.4 Test for all 2PFs . . . . . . . . 4.3.5 Classi cation of 2PF tests . . 4.4 Tests for AF2s . . . . . . . . . . . . . 4.5 Summary of two-port memory tests . .

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Classi cation of 2P memories based on the port mix Simpli cation of 2PFs based on the port mix . . . . Simpli cation of AF2s based on the port mix . . . . Impact of port restrictions on the tests for 2PFs . . 5.4.1 Test for (rw-wo)2P memories . . . . . . . . . 5.4.2 Test for (rw-ro)2P memories . . . . . . . . . 5.4.3 Test for (wo-ro)2P memories . . . . . . . . . 5.5 Impact of port restrictions on the tests for AF2s . . 5.5.1 Test for AF2s in (rw-wo)2P memories . . . . 5.5.2 Test for AF2s in (rw-ro)2P memories . . . . . 5.5.3 Test for AF2s in (wo-ro)2P memories . . . . 5.6 Simpli cation of tests based on the topology . . . . . 5.6.1 Reduction of March 2PF2.1 . . . . . . . . . . 5.6.2 Reduction of March 2PF3 . . . . . . . . . . . 5.6.3 Reduction of March 2PF . . . . . . . . . . . . 5.7 Comparison of tests based on the complexity . . . .

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5 Fault and test simpli cation 5.1 5.2 5.3 5.4

6 Test strategy

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6.1 Test strategy for MCAFs in 2P memories . . . . . . . . 6.1.1 Test strategy for MCAFs in (rw-rw)2P memories 6.1.2 Test strategy for MCAFs in (rw-wo)2P memories 6.1.3 Test strategy for MCAFs in (rw-ro)2P memories 6.1.4 Test strategy for MCAFs in (wo-ro)2P memories 6.2 Test strategy for AFs in 2P memories . . . . . . . . . . 6.2.1 Test strategy for AFs in (rw-rw)2P memories . . 6.2.2 Test strategy for AFs in (rw-wo)2P memories . . 6.2.3 Test strategy for AFs in (rw-ro)2P memories . . 6.2.4 Test strategy for AFs in (wo-ro)2P memories . . 6.3 Test strategy for all faults in 2P memories . . . . . . . . 6.3.1 Test strategy for (rw-rw)2P memories . . . . . . 6.3.2 Test strategy for (rw-wo)2P memories . . . . . . 6.3.3 Test strategy for (rw-ro)2P memories . . . . . . 6.3.4 Test strategy for (wo-ro)2P memories . . . . . .

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CONTENTS

7 Conclusions and recommendations Bibliography Appendix

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96 98 101

Chapter 1

Introduction This chapter introduces some basics about testing and semiconductor memories. Section 1.1 gives the importance of testing logic and its aspects. Section 1.2 covers brie y the economical aspects of testing; while Section 1.3 describes shortly the semiconductor memories and their tests till today. Section 1.4 presents the outline of this thesis.

1.1 Test importance Very large scale integrated (VLSI) circuits are an integral part of any modern electronic system. Such circuits contain from thousands to millions of transistors, diodes and other components such as capacitors and resistors, together with interconnections, within a very small area. They can be divided into two classes: combinational circuits (without memory) and sequential circuits (with memory). The manufacturing of such circuits is a complicated and time-consuming process and defects in them are inevitable. Such defects may be due to several de ciencies in the original silicon and in the manufacturing process. Examples of the former are impurities and dislocations, and examples of the latter are temperature uctuations during the processing, open interconnections, open circuits, short circuits, and extra or missing transistors. The larger the VLSI circuit in terms of area and complexity, the greater the chances of it having a defect. From the point of view of economics, it has been shown that the cost of detecting a faulty component is lowest before the component is packaged and becomes part of a VLSI system. Therefore, testing is a very important aspect of any VLSI manufacturing process. There are two aspects of testing: fault detection and fault diagnosis. With fault detection only the presence of a fault is established, whereas with fault diagnosis the exact location of the fault has to be identi ed. The testing process involves the application of test patterns to the circuit and comparing the response of the circuit with a precomputed expected response. Any discrepancy constitutes an error, the cause of which is said to be a physical fault [Breuder 1976]. Such faults, for digital circuits, can be classi ed as logic or parametric. A logic fault is one which causes the logic function of the circuit elements to be changed to some other function; while a parametric fault alters the magnitude of a circuit parameter causing a change in some factor such as circuit speed, current or voltage level. Logic faults, also called logical faults, which are 2

CHAPTER 1. INTRODUCTION

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used to model physical faults, are very important because they turn the problem of fault analysis into a technology-independent problem. In addition, tests designed for logical faults may be useful for detecting physical faults whose eect on the circuit behavior is not well understood or too complex to be analyzed otherwise. Thus, testing VLSI circuits can be de ned as a process of detection and location of faults that inevitably occur in VLSI circuits. This is usually done by applying a set of signals (test vectors) to the circuit under test and comparing the observed output signals to the set of reference signals. Depending on the test application method, testing VLSI circuits can be classi ed as functional testing and in-circuit testing [van de Goor 1991]. Functional testing is performed via the normal board connectors. It is a very important form of testing, because it allows for the development of eective, short, algorithms without requiring much knowledge of the internals of the device under test. In in-circuit testing a special, board speci c, connector, is used such that all signal lines on the board are accessible. It allows for locating faulty components. As mentioned previously, VLSI circuits can be classi ed into combinational circuits and sequential circuits. Therefore, a distinction can be made between testing each one of the two classes. Testing combinational circuits is much easier, since for each fault, at most one test vector has to be applied; while the detection of a fault in sequential circuits may require rst to bring the circuit into a state in which the fault may be sensitized and observed. For example, in a sequential circuit with a state vector of n bits, this might require 2n input signals (or clock cycles) before the faults will be detected. With the increased complexity of current VLSI circuits, reliability considerations have become increasingly important. Therefore, a test of VLSI circuits must be made manageable; i.e., VLSI circuits must be designed with test considerations in mind. This is called design for testability (DFT).

1.2 Test economics Economic analysis have demonstrated that the introduction of DFT leads to higher quality products at reduced cost, assuming that a high quality product is wanted in the rst place [Dislis 1995]. It can be argued that if you don't want a quality product, than you don't need to test; so no test cost, therefore cheaper! But such a naive attitude to quality neglects other issues, e.g., preceived value by customers and future sales, possible litigation by customers and users through damages caused by product failures, etc. It has also been shown that the cost of test and repair in the component manufacturing phase is lowest as compared to when the component is packaged and enters the working life phase; i.e., when it is in the eld [David 1982]. This is due to the increase in volume and in diculty level of locating the faulty part, and in the increase in repair eort. In addition, a good test approach can reduce the development time and therefore the time to market, as well as the eld maintenance cost. However, test development also takes time and therefore increases the development time. Figure 1.1 shows that with increasing test quality, the cost of test development time increases;


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while the manufacturing test and repair cost decreases, such that the total cost of the product is minimized for some test quality, which may not be the highest test quality. Cost Total cost

Developement and time to to market

Manufacturing and maintenance Test quality

Figure 1.1: In uence of test quality on cost

1.3 Tests and semiconductor memories Semiconductor memories are a key component of any computer system today. They come in many types, based on both MOS and bipolar technologies. In general, bipolar memories exist in lower densities for very fast applications, while MOS memories exist in high densities and with very low power consumption. In addition, the market of bipolar memories is much smaller than that of MOS memories. There is a distinction between dynamic and static memory cells. Dynamic Random Access Memories (DRAMs) have their information stored in a capacitor. They have the highest number of bits per chip, but their disadvantage is that they have to be refreshed at periodic intervals in order not to lose their information. Conversely, Static Random Access Memories (SRAMs), which have their information stored in latches, do not require to be refreshed. However, they take more silicon area per bit than DRAMs. Both types of memories are volatile; i.e., they lose their information when power is turned o. It should be noted that in this report we will restrict ourselves only to SRAMs based on MOS technology. A further distinction can be made within a special class of memories, the so called Read Only Memories (ROMs). These memories, which are non volatile, are set to produce the same output at all times; unless altered to change the data placed within them. ROMs can be programmed by the end user. According to the erasure method, with ultraviolet light or electronically, programmable ROMs are named erasable, programmable ROMs (EPROMs) or electronically, erasable


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ROMs (EEPROMs), respectively. Another distinction can be made between single and multi-port memories. A single-port (SP) cell is one which can only be read or written via a single circuit path. A multi-port (MP) memory is a memory having multiple ports that are to be used to access memory cells simultaneously and independently of each other, subject to certain restrictions. Namely, no cell can be written by more than one port concurrently with inconsistent data values, and no cell can be read and written at the same time. Tests for SP memories have experienced a long development process. Before 1980, tests had very long test times for a given fault coverage (i.e., the number of detected faults divided by the number of total faults); typically of order O(n2 ), where n is the size of the memory. Such tests can be classi ed as the ad-hoc tests because of the absence of fault models and proofs. Tests like the Zero-One test, the GALPAT, and the Walking 1/0 tests belong to this class [Breuder 1976]. The introduction of functional fault models, which are abstract fault models, had the advantage that the fault coverage could be proven while the test time usually was of order O(n). March tests became the dominant type of tests for the introduced functional faults [van de Goor 1991], [Mazumder 1996]. To allow for the establishment of the fault models based on simulated defects in real designs instead of abstract fault models, Inductive Fault Analysis (IFA) was developed [Shen 1985], [Maly 1985]. IFA is a systematic procedure to predict the faults in an integrated circuit by injecting spot defects in the simulated geometric representation of the circuit. In the early 1990's the memories had an impressive increase in size, and as consequence, linear tests became not always acceptable. In addition, the use of embedded memories had made their testability problem very hard because of the lack of the controllability of their inputs and the observability of their outputs. Therefore, a built-in-self-test (BIST) was proposed in order to overcome this problem [Kinoshita 1986], [Mazumder 1989], [van de Goor 1991]. In addition, BIST has the advantage of solving the access problem of embedded memories, and allowing for at-speed testing; i.e., testing at the maximal clock period. MP memories are more complex than SP memories. However, in spite of the growing use of them, limited work on their testability has been published. An ad-hoc test technique with no speci c fault model was described in [Raposa 1988]. Serial test algorithms for an embedded multi-port memory were reported in [Nadeau-Dostie 1990]; however the used fault models were very simplistic and restricted to shorts between ports. For the same fault models (i.e., shorts between ports), a modi ed march tests and their BIST circuitries was proposed in [Matsumuna 1995; Wood 1995; Wu 1997] A new fault model, the so called complex coupling fault, which was also too simplistic, and its test was developed by [Alves 1991]. This test, which has a O(n2 ) test time, can be reduced to O(n) by imposing topological restrictions [Nicolaidis 1995]. It will be clear from the above that tests for MP memories are in the infant stage period, and, in addition, their tests are getting more important since they are often embedded in VLSI circuits. Adequate fault models still remain to be established, and ecient tests still remain to be found.


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1.4 Outline of the thesis Chapter 1 highlights brie y the technological developments in very large scale integrated (VLSI) circuits, from which the increased importance of testing follows. It also introduces some basics about testing and its aspects. In addition, it describes semiconductors memories and their current test developments. Chapter 2 gives a motivation for the use of models for memories. Two of such models, namely functional and electrical models will be described for single-port as well as for multi-port memories. Functional models give functions to be realized in terms of block diagrams, while electrical models give the explicit descriptions of them in terms of transistors, capacitors, resistors, etc. Chapter 3 covers the functional fault models for single-port memories as well as for two-port memories. These faults are divided into memory cell array faults, address decoder faults, and read/write logic faults. Memory cell array faults for single-port memories are analyzed in more detail and divided into strong faults that always fully sensitize a fault, and weak faults that only partially sensitize a fault. The eect that the presence of multiple weak faults, as consequence of multiple accesses, can well sensitize a fault is used to derive memory cell array fault models for multi-port memories. In order to establish a set of fault models for address decoder faults, the interference between dierent port will be analyzed. Chapter 4 introduces tests for the developed fault models of Chapter 3. In order to do this, rst the notation for march tests will be extended such that it is able to specify tests for multi-port memories. Then, the conditions for detecting the faults will be found, and nally used to derive tests. In Chapter 5, the fault models and their tests introduced in Chapter 3 and Chapter 4 respectively will be simpli ed. First the simpli cation will be based on the port mix, and then on the topology. Chapter 6 gives a test strategy (which determines which test has to be used); while Chapter 7 summaries the conclusions and gives some recommendations. It is followed by the bibliography and an appendix; the appendix shows a copy of the paper sent to the \16th IEEE VLSI Test Symposium, Montery, California, 1998".

Chapter 2

Structures of memories This chapter starts with a motivation for the use of models for memories, and shows the existence of models with dierent levels of abstractions. Then the functional and the electrical models of single-port memories will be described in Section 2.2. Finally, the same will be done for multi-port memories in Section 2.3.

2.1 Memory models Modeling is the introduction of a level of abstraction, which simpli es and structures an entity and its environment, in such a way that models describe only the relevant events, properties, and changes that are signi cant for a speci c purpose. Therefore, modeling of memories means the introduction of a level of abstraction, whereby the details which are not relevant are hidden within the model. The most general model of a memory is a box with inputs and outputs; see Figure 2.1. As can be seen from the gure, a memory receives address, control, and data-in values from the exterior via the inputs, and produces data-out values via the outputs. The inputs consist of the controls, N address lines, and B input data lines, whereby B is the word-width of the memory. The outputs consist only of a B ?bit data-word. Addresses Data-in

N B

MEMORY

B

Data-out

Controls

Figure 2.1: General model of a memory The model of Figure 2.1 can be further re ned into two parts, the so called two-dimensional memory model [Oerman 1995]; see Figure 2.2. The two parts of this memory model are: The memory cell array part: this part represents the memory cell array. Every memory cell can store only one bit of information. In addition, there is always exactly one memory cell array in a memory. The memory ports part: this part represents the interface between the external world of 7

CHAPTER 2. STRUCTURES OF MEMORIES

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the memory and the memory cell array. A memory can have P memory ports, whereby P 1.

Memory cell array

Memory ports

B N

B

Data-out

Controls

Data-in

Addresses

Figure 2.2: Two-dimentional memory model Models can be based on dierent levels of abstraction of the system to be modeled. This also applies to memories, see Figure 2.3. The highest level, called behavioral level, speci es only the functions of the system. At this level, which is also referred as the black box model, modeling is done using pseudo codes or graphs. The second lower level is the functional level, and is based on block diagrams. It gives some view of what goes on inside. Therefore, it is also called the gray-box model. The third lower level at which a system can be described is the logical level, where gates and connections present the inside of the boxes of the functional level. This model is not considered for memories since memories do not contain gates. The fourth lower level is the electrical level, it gives an explicit description of functions to be realized in terms of transistors, capacitors, resistors, etc. Therefore, this model is also referred to as the white-box model. The lowest level is the geometrical level; it presents the complete layout of the system, including device geometries, doping levels, etc.

2.2 Structures of SP memories A SP memory is a memory which can only be read or written via a single path (i.e., P = 1). In the following, the functional and electrical models of such memory will be discussed. The geometrical model is rarely reported.


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Increasing level of abstraction

Behavioral model

Functional model

Logical model

Electrical model

Geometrical model

Figure 2.3: Levels of modeling

2.2.1 Functional model of SP memories

A typical SP memory consists of a memory cell array, two address decoders, read/write circuits, data ow and control circuits; see Figure 2.4. The memory chip is connected to other devices through address lines, data lines, and control lines (i.e., read/write line, chip enable line, and power lines). The memory cell array is the most basic part of the memory. It consists of n cells, which are organized as an array of r rows and c columns. The number of rows can be any integer, but the number of columns is restricted: there is always an integer number of memory words in one row (i.e., c mod B = 0). Note that the memory cell array has a capacity of r c bits. The addresses are divided into high- and low-order bits. The high-order bits are connected to the row decoder which selects an appropriate row (Word Line) in the memory cell array, while the low-order bits are connected to the column decoder which selects the required columns (Bit Lines). The number of columns selected is B , which determines how many bits can be accessed during a read or a write operation. To read the desired memory cells, appropriate row and column select lines must be activated. The content of the selected cells are ampli ed by the read circuits, loaded into the data registers and presented on the data-out lines. Conversely, during a write operation, the data on the data-in lines is loaded into the data registers and written into the selected cells through the write circuits. Usually the data-in and data-out lines are combined to form bidirectional data lines, thus reducing the number of pins of the chip.


Row decoder

Row address

Dataword in

10

Memory cell array

Read/Write circuits and data registers

Dataword out

Data flow and control circuity

Column address

N

Column decoder

B

B

Controls

Data-in

Addresses

Data-out

Figure 2.4: Functional model of a SP memory

2.2.2 Electrical model of SP memories

As mentioned already, the electrical model gives an explicit description of a function to be realized in terms of electrical components. That means that the blocks of the functional model will be opened such that the electrical properties will become visible.

Memory cells A static RAM cell is a bistable circuit, being driven into one of two states. After removing the driving stimulus, the circuit retains its state. An SRAM cell can have several con gurations. Figure 2.5 shows the generalized SRAM cell, and three possible con gurations. As can seen in Figure 2.5(a), the SRAM cell consists of two load elements (L1 and L2), two storage elements (M1 and M2), and two pass transistors (P1 and P2). Transistor M1 forms an inverter together with the load element L1. This inverter is cross-coupled with the inverter formed by the transistor M2 and the load element L2; therefore, forming a latch. This latch can be accessed for read and write operations, via the pass transistors P1 and P2.


11 VDD

VDD

R1

L2

L1

P2

P1

M1

R2

P1

M2

P2

M1

M2 VSS

VSS WL

WL BL

BL

BL

(a) Generalized SRAM memory cell

BL

(b) Four transistor cell with resistor load

VDD

VDD

D1

M3

D2

P1

P1

P2

M1

BL

P2

M1

M2

V SS

WL

M4

M2 VSS

WL BL

(c) Six transistor cell with NMOS delpletion load

BL

BL

(d) Six transistor full CMOS cell

Figure 2.5: Generalized SRAM cell, and various con gurations of static RAM cells Data can be written into the cell by driving the lines BL and BL with data with complementary values, and thereafter driving the WL high . The cell will be forced to the state presented on BL and BL, since the two lines are driven with more force than the force with which the cell retains its information. To read data from a cell, generally, rst both lines BL and BL are precharged to a high level, after which the desired WL is driven high. At that time the data in the cell will pull one of the two bit lines low. This dierence signal on the BL and BL lines is ampli ed by the read circuit (see Figure 2.4), and read out through the data register. It should be noted that reading an SRAM cell is a non-destructive process; i.e., after the read operation the logic state of the cell remains the same. The load devices may consist of polysilicon resistors, either enhancement or depletion mode transistors, or PMOS transistors. Figure 2.5(b) shows the SRAM cell with polysilicon load devices. This cell requires less silicon area than the two other con gurations. However, it has a higher leakage current when it is not being accessed, since a small amount of current always

ows through the resistor. When the load element is a PMOS transistor (see Figure 2.5(d)), then the resulting CMOS cell has essentially no current drain through the cell except when it


12

is switching because either the NMOS or the PMOS transistor is always o. The disadvantage of the CMOS cell is that it requires more processing steps because of the presence of NMOS and PMOS transistors. Figure 2.5(c) shows a six-device SRAM cell using depletion mode load transistors. It should be noted that the depletion mode transistor can also be replaced with an enhancement mode transistor, but the depletion load is normally used since it has better switching performance, a higher impedance, and is relatively insensitive to power supply variations [Prince 1991].

Address decoders

Address decoders are used to access particular cells in the memory cell array. In order to minimize the size of the decoders and the length of the word and bit lines, two dimensional addressing schemes are used within the chip, demanding a row decoder for the word lines and column decoder for the bit lines. VDD

V DD

A 0

A 1

A k-1

V SS WL

WL A 0 A

Buffer

A 0 A

1

Buffer

1

A k-1

A k-1

VSS

VSS (a) PMOS-load decoder

(b) CMOS decoder

Figure 2.6: Static row decoders A row decoder is needed to select one row out of the set of rows in the memory array. Figure 2.6 shows two basic static row decoders, namely a PMOS-load decoder [Sasaki 1988] and a CMOS decoder. The inputs of the decoders are the address bits A0 through Ak?1 or their complements, while the output is the word line. When the row decoder selects a word line, all cells along that word line are actived and put their data on the bit lines. Note that the address lines are connected only to the NMOS transistors in a PMOS-load decoder; while they are connected to both PMOS and NMOS transistors in a CMOS decoder. Therefore, the address load capacitance caused by the gates in a PMOS-load decoder is almost half of that in a CMOS decoder. This implies that a smaller delay time can be obtained by using a PMOS-load decoder. The CMOS decoder has the advantage of drawing no static current, but as it requires an equal number of PMOS and NMOS transistors, it occupies a larger area.


13

Dynamic or clocked decoders are also used to decode word lines. Figure 2.7 shows two dynamic row decoders. Generally, such decoders combine compact layout with zero static current consumption; power is dissipated in the selected decoder only during the brief period of an address transition. The decoder of Figure 2.7(b) proposed by [Mazumder 1988] operates as follows: in the precharge phase, the transistor Q1 is turned on to precharge the common line connected to the address decoding transistors. If all the address bits, A0 , ..., Ak?1 are zeros, transistor Q6 drives the WL line to '1'. The signal EN enables the transmission gate such that the decoder selects the word line only after all address lines are stable. VDD

VDD

Clock Precharge

Q 1

Q 3

Q 4

Q 6

WL

EN

Buffer

A 0

WL A

1 EN A 0

A k-1

Precharge

VSS (a) Simple decoder

Ak-1

A 1

Q 5

Q 7

Q 2

V SS (b) Modified CMOS decoder

Figure 2.7: Dynamic row decoders A column decoder selects B bit line(s) (or bit line pairs) out of the set of bit lines (or bit line pairs) of the selected row. Depending on the memory application, dierent column decoders are designed. Figure 2.8(a) shows a tree decoder, which is desirable for single endeded memories; i.e., memories which use only a single bit line for read and write operations. This circuit has the advantage of being simple, however it operates slowly. Figure 2.8(b) shows another column decoder [Minato 1982], which is based on the PMOS-load decoder of Figure 2.6 . The output of the decoder goes to an inverter, where the output signal is ampli ed, after which it moves on to the column switch MOS transistors. This circuit has the advantage of being compact.

Read/Write circuitry Once a particular single or pair of bit lines have been selected, depending on the SP memory cell structure, circuitry is required to write or to read the cells. Typical write circuits are shown in Figure 2.9. Circuit (a) consists of a pair of inverters and a pass gate with a write control input


14 VDD

Data Select column A2 A2

A0

BL

BL

A1 A

A1

1 Read/Write circuit

A0 A 0

A k-1 BL8 BL7

BL6 BL5

BL4 BL3

V SS

BL2 BL1

(b) Decoder based on the PMOS load

(a) Tree decoder

Figure 2.8: Column decoders signal; while circuit (b) consists of a pair of NAND gates. The to be written data on `data in' line is presented on BL and BL. Data in

Data in Write

Write BL (a) Circuit based on inverters

BL

BL BL (b) Circuit based on NAND gates

Figure 2.9: Memory write circuitries The read circuitry is more complex than the write circuitry and depends on the type of the memory cells to be read, namely single ended or dierential. In addition, it can be based on a voltage mode or a current mode signal transporting technique. Figure 2.10 shows two voltage mode sense ampli es, namely a single ended PMOS dierential sense ampli er, and a doubleended PMOS cross-coupled ampli er [Sasaki 1989]. In circuit (a), when the data on BL is '1', the transistor M 1 turns on, and the transistor Q2 drives the Out line to '1'; while when the data on BL is '0', transistor M 2 turns on, and drives the Out line to '0'. In circuit (b), the voltages of the Out and Out lines control the gates of the PMOS transistors Q1 and Q2 such that the output voltage transitions are accelerated. Current mode sense ampli ers operate generally faster than voltage mode ones. Figure 2.11 shows two current mode sense ampli es: a double-ended current-mirror ampli er [Sasaki 1988] and a hybrid current sense ampli er [Chee 1992]. The double-ended current-mirror ampli er has been widely used because of its fast sense speed, large voltage gain, and good output voltage stability.


15 VDD

VDD

Q1

Q2

Q1 Out

BL

M1

Out

BL

BL

M2

Q2

Out

BL

M2

M1

Column Switch

Column Switch

V SS

VSS

(a) Single-ended sense amplifier

(b) double-ended sense amplifier

Figure 2.10: Voltage mode sense ampli ers BL

BL

BL

BL VDD

VDD

VDD

Out

Out

Clock VDD Column switch Out

Out V SS (a) Double-ended current mirror amplifier

VSS (b) Hybrid current sense amplifier

Figure 2.11: Current mode sense ampli ers

2.3 Structures of MP memories MP memories are memories having multiple ports (i.e., P 2) which are used to access memory cells simultaneously and independent of each other. In the following the functional and the electrical models of such memories will be discussed.

2.3.1 Functional model of MP memories

To transform the functional model of a SP memory into a functional model of a MP memory, ports are added by adding address lines, data lines, chip enable lines and decoders for each port (see Figure 2.12). Furthermore, each port may have the capability to be a read-only port (Pro), a write-only port (Pwo), or a read-write port (Prw). A read-only port has only the capability of reading a memory word; a write-only port has only the capability of writing a memory word; while a read-write port has both capabilities. The total number of ports is P = Pro+Pwo+Prw.


16

A MP memory consists of a common memory cell array, two address decoders per port, P (number of ports) of read and/or write circuits, P data ow and control circuits, and multiple write circuits. The multi-port memory is connected to the outside world through multiple address lines, multiple data lines, multiple read/write lines, multiple chip enables lines and power lines.

Row address

Row

decoder 1 Row

decoder 2

Memory cell array

Row

decoder P

Column address

Column decoder 1

B

B


Column address

Column decoder 2

B

N

Dataword out

N


Dataword in Read/Write circuits and data registers

Dataword out


Column address


Dataword out


Column decoder P

B

N Data-out

Controls Data-in

Data-out

Controls Data-in

Data-out

Controls Data-in

Addresses P

Addresses 2 Addresses 1

Figure 2.12: Functional model of MP memory The MP memory operations are done in a similar way as those of the SP memory, except that now multiple ports control up to P simultaneous operations to one or more words. However, various bizarre interactions can occur as a result of the simultaneous multi-port operations; i.e., a word may be read and written at the same time, a word may be written by more than one port concurrently such that inconsistent data values may result. Port priority-style may be used [Forsel 1994]: several ports can simultaneously access the memory to write dierent data words to the same cells, but only the port with the highest priority succeeds.

2.3.2 Electrical model of MP memories

Describing of the electrical model for MP memories will be done in the same way as is done for SP memories; i.e., the blocks of the functional model of Figure 2.12 will be opened such that


17

the electrical properties become visible. A MP memory consists of P duplicated ports and a common memory cell array. The circuits of each port in the memory port part for MP memory can be the same as these of SP memory. That means that the address decoders and sense ampli ers discussed in Section 2.2.2 can also be used for MP memories. However, the memory cell array has to be modi ed in order to support multiple access. In the following, dierent MP memory cell structures will be described. In addition, two sense ampli ers, special for MP memories, will be discussed.

MP memory cell structures

Depending on the type of the ports the MP memory cells consist of, they can be classi ed into:

cells having a shared read/write ports: all ports of these cells are of the type Prw; that means that each port can be used to read or to write a cell. Moreover, with these cells the same bit line (or bit line pair) is used for reading or writing data. cells having separate read and write ports: all ports of these cells are of the types Pro or Pwo. The read and write ports have separate paths; i.e., some bit lines are only used for reading data, and some bit lines are only used for writing data. cells having mixed read and write ports: these cells can have of Prw ports as well as Pro ports or Pwo ports. The operation can be done via a single path as well as via separate paths; i.e., some bit lines are only used for reading or only for writing, and some bit lines are used for both reading and writing.

In the following, each class will discussed separately:

Shared read/write ports cell Three shared read/write ports cells with two Prw are shown in Figure 2.13. Figure 2.13(a) shows a dierential access MP cell [Kadota 1982]. This cell includes the general form for parallel expansion of independent dierential ports. Each port has bit lines BL and BL such that a dierential sense ampli er can be used. In addition, for each port two pass transistors are added to the basic four-transistors memory cell. Because of the complex word and bit line interconnections and the two extra pass transistors for each port, this cell requires more area. However, its performance is better than that of a single-ended cell. The circuit of Figure 2.13(b) shows a single-ended MP cell [Sherburne 1982]. In this case, for each read/write port only one pass transistor is added to the basic four-transistor cell. Therefore, the area of the memory chip is minimized. However, its performance is lower than that of a cell with dierential access cell, since dierential sense ampli ers can not be used. Figure 2.13(c) shows a twin-port cell [O'Cnnor 1987] which uses complementary access devices. In addition, the symmetric port structure, that matches the cell symmetry, allows for an eectively use of the CMOS cell since each port has the potential of accessing a cell without interference from activities at the other port, even if addressing the same cell. The read operation is based on the complementary precharging , i.e. bit line BLNH is precharged high and the


18

bit line BLPL is precharged low. If the port 1 (P-channel pass transistor) is read and the stored data is '1', device M 6 will conduct, charging the bit line BLPL from the VSS to a positive level. But if the stored data is '0', device M 6 will not conduct, as the gate, drain and source are all at VSS (passive reading). The read operation by port 2 is done similar as by port 1. Note that the circuit of Figure 2.13(c) can be conceptually extended in such way that it will be dierential. VDD

M3

M4 M8

M6 M5

M7 M2

M1 VSS WL1 WL2

BL1 BL2

BL1 BL2 (a) Differential acces MP cell

VDD

M3

WL P

VDD

M4

M6 M5 M1

M3

M4

M1

M2

M6 M5

M2 VSS

WL1 WL2

VSS WL N BL1 BL2

BL BL PL NH (b) Single-ended MP cell

(c) Twin-port MP cell

Figure 2.13: Common read/write MP memory cells with Prw=2

Separate read and write ports cell Figure 2.14 shows two implementations of separate read and write MP cells. The circuit of Figure 2.14(a) [SCSC 1988] shows a four port memory cell, with two Pro and two Pwo. A single bit line is used for reading data, and another single bit line is used for writing data. Note that local to the cell the write data is inverted. Usually this cell has a separate read and write ports; i.e., no read/write port. It has the best electrical electrical characteristics, since the addition of transistors M 7 and M 8 allows for a read operation to have a very small load on the cell. However, it occupies a large area.


19

Figure 2.14(b) [Landsberg 1993] gives another implementation of a MP cell with separate read and write ports. This circuit has a four ports: two Pro and two Pwo. A single bit line scheme is used for both read and write operations. The circuit that drives the bit line during the read operation, i.e. the inverter formed by the transistors M 7 and M 8, is unidirectional. Regardless of the bit line capacitance or the number of the ports enabled, the voltage change on N due to the capacitive coupling with a bit line, cannot switch the memory cell. VDD

M3

M4

M5 M10 M6

M8 M1

M9

M2 M7 VSS

WWL1 WWL2 RWL1 RWL2 RBL2 RBL1

WBL1 WBL2

(a) Circuit using extra transistor per Pro to reduce the load on the cell VDD

M3

M4

M8 M10

M5 N M9

M6 M1

M2

M7

VSS WWL1 WWL2 RWL1 RWL2 WBL1 WBL2

RBL2 RBL1

(b) Circuit using an invertor (M8 and M7) to reduce the load on the cell

Figure 2.14: Separate read and write MP memory cells with Pro=2, and Pwo=2

Mixed read and write ports cell Two dierent implementations of mixed ports MP cells are shown in Figure 2.15. The circuit of Figure 2.15(a) consists of a two port MP cell with two Pro and a single Prw [Sherburne 1984]. Each port has a single bit line for reading data. Therefore, single-ended sense ampli ers are needed. The write operation is done by driving both word lines WL1 and WL2 high, and


20

putting DATA and DATA on the bit lines BL1 and BL2. Note that this cell combines the read scheme of Figure 2.13(a) for bit line count reduction, and the write scheme of Figure 2.13(c) for a fast write. Another implementation of such 2P memory cell, is given in Figure 2.15(b) [Wang 1996]. This lower power circuit consists of a Prw which is based on voltage mode access (bit lines BL1 and BL1), and a Pro which is based on current mode access (bit line BL2). VDD

M3

VDD

M4

M5

M5

M3

M4

M6

M7 M1

M8

M2

M2

M1

VSS

M7

VSS WL2

WL1

BL1

BL2

(a) Circuit combining a single and a differential access

WL1 WL2 BL1

BL1 BL2 (b) Circuit combining a voltage and a current mode access

Figure 2.15: Mixed ports MP memory cells

Sense ampli ers for MP memories In this subsection, two sense ampli ers which are especially designed for MP memories will be discussed. The rst one is a voltage mode sense ampli er based on a dummy cell [Shinagawa 1991], and the second one is a current mode sense ampli er based on current direction sensing [Izimikawa 1996]. Figure 2.16 shows the voltage mode sense ampli er. This circuit uses a dummy cell to generate a reference voltage for a dierential sense ampli er in order to achieve high speed sensing for single-ended MP memories. When the internal clock goes low, the read bit line RBL and dummy bit line DBL are precharged. When the clock goes high, the dummy cell and the MP memory cell are simultaneously selected. the dierential signals are fed to the pre-ampli er, that quickly shift these dierential signals to the level which causes the main ampli er to operate most sensively. Finally the shifted signals are sensed by the dierential ampli er. Figure 2.17 shows the current mode sense ampli er based on current direction sensing. It reduces the access time of a single-ended MP memory cell without the need for a reference voltage. The voltage at the current direction sense circuit's input node referred to as INT, is maintained at an intermediate voltage level. When the input is '0', the current will be pulled from the INT; while when it is '1', the current will be pushed to the INT. The current direction sense circuit reacts to these varying stimuli by producing respectively dierent dierential outputs to the second ampli er, which in turn ampli es these respective voltage dierentials to the CMOS level.


21 V DD

Clock WL Dummy cell RBL DBL VSS

Column selector

Pre-Amplifier

Main-Amplifier

Out

Figure 2.16: Voltage mode sense ampli er based on dummy cell VDD

VDD

Out

V1 V2 INT

Column select

V SS

Current direction sense circuit

VSS

Second amplifier

Figure 2.17: Current mode sense ampli er based on current direction sensing

Chapter 3

Functional faults for memories This chapter starts with giving a complete set of functional fault models for SP memories; they are divided into memory cell array faults, address decoder faults, and read/write logic faults. Thereafter, functional faults for 2P memories will be discussed; they also will be divided into memory cell array faults, address decoder faults, and read/write logic faults. Memory cell array faults for SP memories will be analyzed in more detail, and will be classi ed into strong faults and weak faults. Weak faults will be used in Section 3.2 to derive memory cell array faults for 2P memories. To derive faults for address decoders in 2P memories, the shorts between two dierent ports will be analyzed.

3.1 Functional faults for SP memories For functional testing, the model of Figure 2.4 can be simpli ed, without loss of information, to three blocks: the memory cell array, the address decoder, and the read/write logic [Thatte 1977; Nair 1978]; see Figure 3.1. Therefore, functional faults in SP memories can be divided into: memory cell array faults (MCAFs), address decoder faults (AFs), and read/write logic faults. Figure 3.2 shows the way SP memory faults can be divided: SP -MCAFs (short noted as SPFs) consist of faults involving a single cell , faults involving two cells, and faults involving k cells; while SP -AFs consist of no access faults and multiple access faults.

3.1.1 SP memory cell array faults

To simplify the description of MCAFs, the following notation will be used: 0 denotes that a cell is in logical state 0 1 denotes that a cell is in logical state 1 x denotes that a cell is in logical state x, where x 2 f0; 1g " denotes 0 to 1 transition # denotes 1 to 0 transition l denotes an inverse transition; i.e., an " or a # transition r0 describes a read operation from a cell with expected value 0 r1 describes a read operation from a cell with expected value 1 22

CHAPTER 3. FUNCTIONAL FAULTS FOR MEMORIES

23

Addresses Address decoder Memory cell array Read/write logic

Data

Figure 3.1: Reduced functional model for SP memory SP memory faults

Address decoder faults ( AFs)

No access faults

Read/write logic faults

Memory cell array faults (MCAFs)

Multiple access faults

Faults involving a single cell

Faults involving two cells

Faults involving k cells

Figure 3.2: Classi cation of SP memory faults

w0 describes a write 0 operation to a cell w1 describes a write 1 operation to a cell 8 denotes any operation; 8 2 f"; #; l; w0; w1; r 0; r 1g < : : : > denotes a particular fault; \: : :" describes the fault < S=F > (of < S=F >v ) denotes a fault in a single cell Cv S describes the condition for sensitizing the fault; S 2 f0; 1; "; #; l; w0; w1; r0; r1g ST means that the eect of sensitizing the fault appears after a time T F describes the value of the faulty cell; F 2 f0; 1; "; #; lg < S1; S2 ; :::; Sm?1 ; F > (or < S1 ; S2 ; :::; Sm?1 ; F >a1 ;a2 ;:::;am?1 ;v ) denotes a fault involving m cells S1 ; S2 ; :::; Sm?1 describe the condition for sensitizing the fault; i.e., the operations to be applied to cells Ca1 up to and including Cam?1 such that the fault will be sensitized in Cv Si 2 f0; 1; "; #; l; w0; w1; r0; r1g for 1 i m ? 1 In addition, in this report , the following terms will be used: fault type: describes an abstract functional fault model such as stuck-at fault (SAF ). fault subtype: denotes one of the ways a fault type can manifest itself such as stuck-at '0' (SA0) or stuck-at '1' (SA1).


24

fault class: denotes a set of fault types which involve the same number of cells. fault subclass: denotes a subset of a fault class consisting of fault types with the same property. fault: denotes either a fault type or subtype. SP memory cell array faults (SP -MCAFs) can be divided into the following fault classes: the fault class involving a single cell (noted as SPF 1s), the fault class involving two cells (SPF 2s), and the fault class involving k cells (SPFks); see Figure 3.3. The fault types of SPF 1 have the property that the cell used for sensitizing the fault is the same cell as where the fault will appear. The types of SPF 2, have the property that the application of a single operation in a cell ca has as consequence that a fault will be sensitized in another cell cv ; while the types of SPFk, have the property that the fault is sensitized in a cell cv if the other k ? 1 cells (i.e., c1 , c2 , ..., ck?2 , and ca ) are in certain state, or if the k ? 2 cells are in certain state and a single operation is applied to a cell ca .

SP-MCAFs

Faults involving a single cell (SPF1s)

Faults involving two cells (SPF2s)

Ca

Cv

Cv

Faults involving k cells (SPFks)

C k-2

Cv

C2 C1

Ca

a 1 2 k-2

Figure 3.3: SP memory cell array faults

SPFs involving a single cell: SPF1s Single cell faults are restricted to a single cell of the memory cell array. This class consists of the following fault types: Stuck-at fault (SAF): the logic value of a stuck-at cell or line is always 0 (SA0 fault) or 1 (SA1 fault). It is always in state 0 or in state 1, and cannot be changed to the opposite state. Figure 3.4(a) shows the state diagram for the SA0 fault, while Figure 3.4(b) shows the state diagram for the SA1 fault. The notation for SAx fault is < 8=x >, x 2 f0; 1g. The fault type SAF has two subtypes; namely SA0 and SA1. Stuck-open fault (SOF): a stuck-open fault means that a cell cannot be accessed, e.g. due to an open WL or a WL connected to Vss [Dekker 1990]. When the read operation is performed on a cell, the dierential sense ampli er has to sense a voltage dierence between the bit lines of that cell. In the case of a SOF , the bit lines will have the same voltage level; consequently


w0

w0

w1

S0

25

w1

S1 (b) SA1 fault

(a) SA0 fault

Figure 3.4: State diagrams for SAF the output value produced by the sense ampli er depends on its implementation. If it is purely combinational, or if it has only a single input, a SOF will always produce a xed output value and therefore appears as a SAF . But if the sense ampli er is based on a latch, it will produce the value of the last read operation. The notation for a SOF is < 8=O >, whereby O can be a 0, a 1, a random value, a pessimistic value (which is the expected value), or the value of the last read operation, depending on the memory technology. Transition fault (TF): a cell which fails to undergo a 0 ! 1 transition when it is written, is said to contain an up transition fault; similar, a down transition fault is the impossibility of making a 1 ! 0 transition. This can be due to a defect in a polysilicon layer covering a diusion region which may result in an extra parasitic pass transistor, to open bit line, etc. [Dekker 1987]. The notation for the up TF is and the TFs. The state diagrams of the two subtypes are given in Figure 3.5. w0 w1

w0 S0

w0

S1

(a) < /0> transition fault

w1

w0 S0

w1

S1

w1

(b) < /1> transition fault

Figure 3.5: State diagrams for TF Data retention fault (DRF): a cell fails to retain its logic value after some period of time. A DRF may be caused by a broken (open) pull-up device within an SRAM cell [Dekker 1988 and 1990]. Leakage currents then will cause the node with the broken pull-up device to loose its charge, causing a loss of information if a logic value was stored in the cell requiring a high voltage at the open node. The fault type DRF has two subtypes: < 1T = #> and < 0T = ">; where T denotes the amount of time required for sensitizing the fault. When both subtypes are present in a single cell, then this cell behaves as if it contains a SOF [van de Goor 1993]. Read disturb fault (RDF): [Adams 1996] reading an SRAM memory cell causes its true and false nodes to be connected to the BL and BL lines, respectively, via the pass transistors. The consequence of this is that the internal node with the low voltage is raised, because the pass transistor and the on-transistor form a resistive voltage divider. In case the on-transistor's resistivity is too high due to some defect, the cell may ip when being read. The RDF fault type consists of two subtypes: < r0= "> and < r1= #>. A test for RDFs preferably has to perform two reads in succession on each cell, in both states.


26

SPFs involving two cells: SPF2s The class of memory cell array faults involving two cells consist of coupling faults (CFs); one cell is called the aggressor cell (ca ) and the other cell is called the victim cell (cv ). The a-cell and v-cell may be located anywhere in the memory cell array. An operation applied to the a-cell, or alternatively, the state of the a-cell may sensitize the fault in the v-cell. The following types of CFs have been identi ed. Inversion coupling fault (CFin ): an " or a # transition write operation in the a-cell causes an inversion in the v-cell. This results in two CFin subtypes: a;v , and a;v . State coupling fault (CFst ): the v-cell is forced to a certain value x only if the a-cell is in a given state y; e.g., a cell node is connected to a bit line [Dekker 1988]. The CFst has four subtypes: < 0; 0 >a;v , < 0; 1 >a;v , < 1; 0 >a;v and < 1; 1 >a;v . Disturb coupling fault (CFds ): the v-cell is disturbed; e.g, makes an " or a # transition, due to a read or a write operation applied to the a-cell [de Jonge 1976], [Nadeau-Dostie 1990]. The CFds has eight subtypes: < r0; #>a;v , < r0; ">a;v , < r1; #>a;v , < r1; ">a;v , < w0; #>a;v , < w0; ">a;v , < w1; #>a;v and < w1; ">a;v . Note that for SRAMs read disturb faults are unlikely to occur; because after the precharge operation, a voltage dierence between the bit lines BL and BL of typically on the order of 100 mV is sucient for the sense ampli er. Hence the BL or BL lines barely make a down transition during a read operation. Therefore, for SRAMs, the CFds fault model, which assumes disturbs by read as well as by write operations, can be simpli ed to disturb by write operations only: CFds -w < x; y >a;v ; x 2 fw0; w1g and y 2 f"; #g. The write-disturb, CFds ? w, fault type has four subtypes: < w0; ">, < w0; #>, < w1; "> and < w1; #>. For DRAMs, due to the write-back operation, also read operations can cause disturb faults; hence, the CFds fault type applies.

SPFs involving k cells: SPFks

The class of memory cell array faults involving k cells, which is referred to as k-coupling faults (noted as k-CFs), can be considered to consist of:

A single cell fault, whereby the fault will be sensitized only if the other k ? 1 cells are in certain state; i.e., contain a certain data pattern. Or


27

A coupling fault, whereby the CF will be sensitized only if the other k ? 2 cells (not involved in the CF ) contain a certain data pattern.

A k-CF is also called a Pattern Sensitive Fault (PSF). Tests for PSF s are very complicated if no restriction is placed on the location of the k cells [Nair 1978; van de Goor 1991]. One constrained PSF is the fault subclass Neighborhood Pattern Sensitive Fault (NPSF) whereby the victim cell (in this case also called the base cell) has a k ? 1 physical neighbors (also called the deleted neighborhood). The number of cells involved in the NPSF is usually assumed to be 5 (referred to as the Type-1 neighborhood) or 9 (referred to as the Type-2 neighborhood). The fault subclass NPSF can be divided into four fault types. Active NPSF (ANPSF): [Suk 1980] the base cell changes its contents due to a change in the deleted neighborhood pattern. This change consists of a transition in one deleted neighborhood cell (aggressor cell), while the k ? 2 remaining deleted neighborhood cells (also called the enabling cells) contain a certain pattern (also called the enabling pattern). The ANPSF can be considered a conditional CFid ; it is also called a Dynamic NPSF [Saluja 1985]. Passive NPSF (PNPSF): [Suk 1980] the base cell cannot change its contents; e.g., cannot make a transition, if the k ? 1 deleted neighborhood cells have some enabling pattern. This fault can be considered a conditional TF . Static NPSF (SNPSF): [Saluja 1985] the base cell is forced to a certain state if the deleted neighborhood cells have some enabling pattern. This fault can be considered a conditional CFst . Disturb NPSF (DNPSF): [Tlili 1997] the base cell makes an up or a down transition due to a read or a write operation applied to one of the deleted neighborhood cells, while the remaining k ? 2 deleted neighborhood cells have some enabling pattern. This fault can be considered a conditional CFds .

3.1.2 SP address decoder faults

Single port address decoder faults, SP -AFs, (abbreviated as AFs) concern faults in the address decoder. They can be divided into [van de Goor 1990] (see Figure 3.6):

No access faults: They consist of the following two faults:

{ Fault 1: no cell fault (denoted as AFnc): with a certain address no cell is accessed. { Fault 2: no address fault (denoted as AFna ): there is no address with which a par-

ticular cell can be accessed. Multiple access faults: They consist of:

{ Fault 3: multiple cells fault (denoted as AFmc ): with a certain address, multiple cells

are accessed simultaneously. { Fault 4: multiple addresses fault (denoted as AFma ): a certain cell can be accessed with multiple addresses.


28

SP address decoder faults (SP-AFs)

No access faults

Ax


Cx

A

Cy

Ay

Cx A

Fault AF nc

y

Fault AF mc

Fault AF na

Cx

x

Fault AF ma

Figure 3.6: SP address decoder faults Because there are as many cells as addresses, none of the above faults can stand alone. They can only occur in one of the following combinations; see Figure 3.7:

Fault A: AFnc + AFna , denoted as AFnca (nca: no cell and no address); i.e., a combination of a no cell fault and a no address fault. Fault B: AFnc + AFmc , denoted as AFnmc ; i.e., a combination of a no cell fault and a multiple cells fault. Fault C: AFna + AFma , denoted as AFnma ; i.e., a combination of a no address fault and a multiple addresses fault. Fault D: AFmc + AFma , denoted as AFmca ; i.e., a combination of a multiple cell fault and a multiple addresses fault. Ax

Fault AF nca

Cx A x

Cx

Ax

Cx

Ax

Cx

Ay

Cy

Ay

Cy

Ay

Cy

Fault AF nmc

Fault AF nma

Fault AF mca

Figure 3.7: Combinations of SP address decoder faults

Notation of SP-AFs To describe AFs, the following notation will be used:

< ::: > denotes a particular address fault; \..." describes the fault. < S=F > denotes a fault involving a single address. < S ; F > denotes a fault involving two dierent addresses. S describes the condition for sensitizing the fault; i.e., which address has to be selected in order to sensitize the fault. The capital letters of the alphabet (i.e., A through Z ) denote memory addresses. Thus S 2 fA; B; :::; Z g.


29

F describes the fault eect; e.g., a cell which is erroneously accessed or not accessed. The lower case letters of the alphabet (i.e., a through z ) denote memory cells when they are accessed and their inversions (i.e., a through z ) denote memory cells when they are not accessed. Thus F 2 fa; b; :::; zg S fa; b; :::; z g. When the sensitizing operation S has multiple fault eects; e.g., two fault eects, then the fault will be noted as < S ; F1 ; F2 >. When the fault is a combination of two faults (linked faults), then it will be given as follows:

< ::: > # < ::: >.

Based on the above introduced notation, the faults of Figure 3.7 are represented as follows:

AFnca : < X=x >. Address X is selected, however the cell Cx is not accessed. AFnmc : < X=x > # < Y ; x >. If address X is selected, then Cx is not accessed; however the selection of address Y will erroneously access Cx (and also will correctly access cell Cy . AFnma : < Y ; x; y >. When address Y is selected, then the cell Cy is not accessed; in addition, cell Cx will erroneously be accessed. AFmca : < Y ; x >. When address Y is selected then not only cell Cy will be accessed, but also cell Cx will erroneously be accessed.

3.1.3 Faults in the read/write logic

The Read/Write logic passes the data from the I/O pins to the memory array and visa versa. Faults occurring in the read/write logic can be mapped onto faults in the memory cell array. A proof of the correctness of this simpli cation is given in [Nair 1978; Thatte 1977; van de Goor 1991].

3.1.4 Linked faults

Depending on the way faults manifest themselves, faults can be classi ed as simple faults and linked faults. 1. Simple faults Simple faults are faults which do not in uence the behavior of other faults. They can be classi ed as address decoder faults and as memory cell array faults. The latter faults can consist of single cell faults, or of faults between memory cells. 2. Linked faults Linked faults are faults which in uence the behavior of other faults such that masking may occur [Papachistou 1985; van de Goor 1991]. They involve two or more simple faults which are sensitized sequentially in the time. Such faults make memory tests more complex because of the possibility of masking. The notation used for linked faults is: < fault1 > # < fault2 > #:::# < faultm >; this shows m linked faults, whereby the symbol '#' denotes that the faults are linked; i.e., sensitized sequentially in the time. Figure 3.8 (a) shows two CFid s, which can mask each other. Both CFid s must have the same victim cell,


30

otherwise they are not linked. Figure 3.8 (b) shows the TF a;v (i.e., a;v ) have an additive eect, and the combined fault eect can sensitize the 2PF 2 denoted as: a;a;v . In the case of w1PF 2a;v &w1PF 1v , the w1PF 1 has to be present in the victim cell of the w1PF 2. For example, the wTF a;v (i.e., a;v ) have an additive eect, and the combined fault eect can sensitize the 2PF 2 denoted as: a;v . 2PF2 s

w1PF2&w1PF1

w1PF2&w1PF2

A

Ca

B

A

Cv

B

A

Ca

B

A

Cv

B

Figure 3.13: 2PF2 faults; A and B denote the two ports of a cell Table 3.2. shows a taxonomy of the possible fault types of the w1PF 2a;v &w1PF 1v . It consists of six possible fault types. The other subclass, namely, w1PF 2a;v &w1PF 2a;v consists also of six possible fault types; (see Table 3.3). In total, 2PF 2s consist of 12 possible fault types. Table 3.2: Overview of possible 2PF2s: w1PF 2a;v &w1PF 1v s

wCFid wCFst wCFds wTF wCFid &wTF CFst&wTF wCFds &wTF wRDF wCFid &wRDF wCFst &wRDF wCFds &wRDF

2PFs involving three cells: 2PF3s

This class of 2PFs is based on a combination of two weak CFs, which have a common victim cell and dierent aggressor cells; i.e., wCFa1 ;v &CFa2 ;v , see Figure 3.14. For example the wCFid a1 ;a2 ;v .


35

2PF3: w1PF2&w1PF2

A

C a1

B

A

Cv

B

A

C a2

B

Figure 3.14: 2PF3 fault; A and B denote the two ports of a cell A taxonomy of all possible 2PF 3s is listed in Table 3.3. By inspecting the table, it will be clear that it is symmetric; therefore several entries represent duplicate fault types. There are only six possible fault types of 2PF 3s. Table 3.3: Overview of all possible 2PF3s; i.e., wSPF 2a1 ;v &wSPF 2a2 ;v s

wCFid wCFst wCFds

wCFid wCFst wCFds wCFid &wCFid wCFid &wCFst wCFid &wCFds wCFst&wCFid wCFst &wCFst wCFst &wCFds wCFds &wCFid wCFds &wCFst wCFds &wCFds

2PFs involving k cells: 2PFks

2PFks can be divided into 2PFks based on w1PFks (i.e., wNPSFs), and 2PFks based on a combination of a w1PF 1 and a wNPSF . Figure 3.15 shows this division. The rst subclass, i.e., wNPSF &wNPSF will be referred to as 2P-NPSF. In the following, the two subclasses of 2PFks will be discussed separately. 2PFks

wNPSF&wNPSF (2P-NPSF)

wNPSF&w1PF1

Cj

Cj

Ci Cv

C k-1

Ci Cv

C2

C k-1

C1

Figure 3.15: 2PFk faults

C2 C1


36

The 2PFk: 2P-NPSFs

ANPSFs, PNPSFs, SNPSFs, and DNPSFs can occur both in 1P memories and 2P

memories. However, the presence of two ports and the ability to have two simultaneous operations in a 2P memory can provoke other types of neighborhood pattern sensitive faults. Since 2P memories allow for two simultaneous operations, two wNPSFs can occur at the same time, and with the same base cell. Their combined fault eect can sensitize a fault if their fault eects are additive. A taxonomy of all possible 2P -NPSFs is given in Table 3.4. There are only 10 possible 2P -NPSF types, because the table is symmetric. Table 3.4: Overview of all possible 2P-NPSFs

wANPSF wPNPSF wSNPSF wDNPSF

wANPSF wPNPSF wSNPSF wDNPSF wANPSF &wANPSF wANPSF &wPNPSF wANPSF &wSNPSF wANPSF &wDNPSF wPNPSF &wANPSF wPNPSF &wPNPSF wPNPSF &wSNPSF wPNPSF &wDNPSF wSNPSF &wANPSF wSNPSF &wPNPSF wSNPSF &wSNPSF wSNPSF &wDNPSF wDNPSF &wANPSF wDNPSF &wPNPSF wDNPSF &wSNPSF wDNPSF &wDNPSF

The 2PFk: wNP1F&w1PF1

This 2PFk is based on a combination of w1PF 1s (i.e., wRDF and wTF ), and wNPSF (i.e., wANPSF , wPNPSF , wSNPSF , and wDNPSF ). It should be noted that this fault makes only sense if the w1PF 1 is present in the base cell of the wNPSF . A taxonomy of all possible wNPSF &w1PF 1 fault types is given in Table 3.5. There are eight possible fault types of wNPSF &wSPF 1 subclass. Table 3.5: Overview of possible 2PFks: wNPSF&w1PF1 faults

wANPSF wPNPSF wSNPSF wDNPSF wTF wTF &wANPSF wTF &wPNPSF wTF &wSNPSF wTF &wDNPSF wRDF wRDF &wANPSF wRDF &wPNPSF wRDF &wSNPSF wRDF &wDNPSF

2PFs involving k + 1 cells: 2PF(k + 1)s

This class is based on a combination of a wCF (i.e., w1PF 2) and a wNPSF . Of course, the victim cell of the wCF has to be the same as the base cell of the wNPSF ; see Figure 3.16. Table 3.6 lists the possible 2PF (k + 1) types. By inspecting the table, it is clear that this class consists of 12 possible fault types.

3.2.2 Reasonableness of 2PFs

New 2P memory cell array fault models, which have been derived from the classical fault models for 1P memories, have already been introduced. The reasonableness of these fault models has to


37

2PF(k+1): w1PF2&wNPSF

Cj

Ci Cv

C k-1

Ca C2

C1

Figure 3.16: 2PF(k+1) fault Table 3.6: Overview of all possible 2PF(k+1), i.e., wNPSF&w1PF2 faults

wCFid wANPSF wANPSF &wCFid wPNPSF wPNPSF &wCFid wSNPSF wSNPSF &wCFid wDNPSF wDNPSF &wCFid

wCFst wANPSF &wCFst wPNPSF &wCFst wSNPSF &wCFst wDNPSF &wCFst

wCFds wANPSF &wCFds wPNPSF &wCFds wSNPSF &wCFds wDNPSF &wCFds

be investigated. Faults which are not considered realistic in the view of the way MP memories are implemented have to be eliminated; Figure 3.21 shows the result of this elimination process. It should be noted that the 1P memory faults which are used to compose the 2PFs are weak faults; they cannot be detected with tests for 1P memories. However, the additive, combined eect of two weak 1P memory faults forming the 2PF , may be sucient to sensitize a fault. The investigation of the reasonableness will be done for each of the types of the ve classes of the 2PFs. To simplify the discussion of the reasonableness of the introduced 2PFs, the following lemma will be introduced:

Lemma 1:

If no operation (i.e., write or read) is needed to partly sensitize a wF , then the 2PF : wF &w1PFi , whereby w1PFi 2 fw1PF 1; w1PF 2; w1PFkg, is not a realistic 2PF . This applies to wCFst and wSNPSF .

Proof:

If a wF does not require any sensitizing operation, then it partially sensitizes a fault in the v-cell irrespective of the number of ports in the memory. The presence of a w1PFi (which may require an operation) at the same time can also partially sensitize a fault in the same cell. If the wF &w1PFi fully sensitizes a fault, then it has to be considered a single port fault model because the fault requires at most only a single operation. In addition, it can be detected with 1P memory tests for linked faults like those proposed in [van de Goor 1996].


38

Reasonableness of 2PF1s For each of the fault types of Table 3.1, an explanation will be given for the fault at the electrical level of the memory. When no explanation can be given, the fault will not considered to be realistic. 1. The 2PF 1: wTF &wTF This fault type makes only sense if the 2P memory allows for two write operations to a single cell, with consistent data values; hence, in order to sensitize a wTF &wTF fault, two simultaneously transition write operations have to be applied to the same cell. If this is the case, then the following explanation can be given: a weak TF can be caused by a parasitic transistor between a cell's node and a pass transistor [Dekker 1988], which partially prevents a cell from being set or reset. A weak TF with the same fault eect on the other port may reduce the resistance to the cell's node. This is because when the sensitizing write operations are applied in parallel to both ports, the two parasitic transistors act in parallel, thereby reducing the resistivity of the path to the cell's node. Hence the combined eect is less than the individual weak TFs. Therefore the 2PF 1: wTF &wTF is not a realistic fault type. 2. The 2PF 1: wTF &wRDF MP memories are subjected to certain restrictions; namely, no cell can be written by more than one port concurrently with inconsistent data values, and no cell can be read and written at the same time. To sensitize the wTF &wRDF fault, a single cell has to be read and written simultaneously. Since this is not allowed in 2P memories, the 2PF 1: wTF &wRDF is not a realistic fault type. 3. The 2PF 1: wRDF &wRDF A RDF occurs when the resistive value of the on-transistor is too high, such that the voltage of the on-node is raised excessively when the cell is being read. When a single cell is read via two ports at the same time, an additive eect of two weak RDFs may sensitize a fault. Hence 2PF 1: wRDF &wRDF is a realistic fault type. It should be noted that only wRDFs which are realistic, and have a cumulative (i.e., additive) eect, have to be considered; for example, the wRDF &wRDF : < r0= ">v & < r0= ">v and the wRDF &wRDF < r1= #>v & < r1= #>v have to be considered, but not the wRDF &wRDF : < r0= ">v & < r1= #>v . The 2PF 1, which conceptually consists of three possible fault types, only consist of one realistic fault type; namely wRDF &wRDF . In addition, only subtypes of wRDF &wRDF which have an additive eect are considered realistic. Therefore, the class of 2PF 1s consists of only the fault type wRDF &wRDF with two subtypes, namely < r0= ">v & < r0= ">v and < r1= #>v & < r1= #>v .

Reasonableness of 2PF2s

The class of 2PF 2s consists of 12 possible fault types; six faults belong to the wSPF 2a;v &wSPF 1v subclass, and the other six belong to the wSPF 2a;v &wSPF 2a;v subclass. The reasonableness of types of each subclass will be discussed separately.


39

Reasonableness of the 2PF2: w1PF2&w1PF1

The w1PF 2a;v &w1PF 1v s consist of six possible fault types; three are based on the combination of a wCF (i.e., wCFid , wCFst and wCFds ) and a wTF , and the other three are based on a combination of a wCFs and a wRDF . 1. The 2PF 2: wCF &wTF A wTF can be caused by a parasitic transistor between a cell's node and a pass transistor, which partially prevents a cell from being set or reset. This eect can be compounded by the simultaneous presence of a CFid or CFds . Therefore, the two fault types wCFid &wTF and wCFds &wTF are realistic. On the other hand, the fault wCFst &wTF requires only a single operation. According to Lemma 1, it is not a realistic 2PF . We can conclude that the 2PF2s: wCFid &wTF and wCFds &wTF are realistic, and wCFst &wTF is not. 2. The 2PF 2: wCF &wRDF A wRDF occurs when the resistive value of the on-transistor is too high, such that the voltage of the on-node is raised excessively when the cell is being read. A wCFid causes its victim cell to take on a xed value; this means that it either raises the potential of the on-node or lowers the potential of the o-node. The presence of a wRDF and a wCFid at the same time, may be such that their combined fault eect is additive, thereby sensitizing a fault. Hence this is a realistic fault type for 2P memories. Similar arguments hold for the 2PF 2: wCFds &wRDF ; hence this also a realistic fault type. The fault wCFst &wRDF requires only a single operation, and according to Lemma 1, it is not a realistic fault type for 2P memories. We state that the 2PF2s: wCFid &wRDF and wCFds &wRDF are realistic fault types, and wCFid &wRDF is not. It can be concluded from the above, that all six fault types of the subclass w1PF 2&w1PF 1 are realistic, except the two fault types wCFst &wTF and wCFst &wRDF . The fact that only additive eects are considered, will reduce the faults of this subclass to the following: < S ; #>a;v & a;v & v , < S ; #>a;v & < r1= #>v , and < S ; ">a;v & < r0= ">v ; whereby S 2 f"; #; w0; w1g. It is clear that this subclass consists of 16 fault subtypes.

Reasonableness of w1PF2&w1PF2

This subclass of 2PF 2 fault types is based on a combination of two wCFs with same aggressor cell, and with the same victim cell. Only faults which can be sensitized by two simultaneous write operations to a single cell, with the same data values, or by two simultaneous read operations of a single cell, will be considered realistic. 1. The 2PF 2s: wCFid &wCFid , wCFid &wCFds and wCFds &wCFds These fault types can only occur if the memory allows two simultaneous write operations into a single cell. If this is the case, then the wCFid &wCFid has to be considered realistic, since the two wCFid s can have the same sensitizing operation and the same fault eect; e.g., a;v & a;v . A similar explanation can


40

be given for wCFid &wCFds and wCFds &wCFds , whereby only write CFds s are considered for MP SRAMs. Therefore the 2PF 2s: wCFid & wCFid , wCFid &wCFds and wCFds &wCFds are realistic fault types only for 2P memories, which allows for two simultaneously write operations into a single cell. It should be noted that by sensitizing such faults, the written data have to be the same, otherwise, the fault is not considered realistic. For example the fault a;v & < w0; ">a;v is not a realistic fault. 2. The 2PF 2s: wCFst &wCFid , wCFst &wCFst , and wCFst &wCFds These fault types require at most a single operation, because for sensitizing the wCFst no operation is needed. A wCFst requires only that the the contents of the aggressor cell has to be in certain state, irrespective of the number of ports. According to Lemma 1, the fault types wCFst &wCFid , wCFst &wCFst , and wCFst &wCFds are not realistic for 2P memories. It can be stated from the above, that the only three of the six fault types of the w1PF 2& w1PF 2 subclass are realistic, namely wCFid &wCFid , wCFid &wCFds and wCFds &wCFds . The fact that only additive fault eect will reduce the faults of this subclass to the following: < S ; #>a;v & < S ; #>a;v , and < S ; ">a;v & < S ; ">a;v ; whereby S 2 f"; #; w0; w1g. Note that the fault a;v & a1 ;v & < S2 ; ">a2 ;v ; whereby Si 2 f"; #; w0; w1g and i = 1 or i = 2.


41

Reasonableness of 2PFks

2PFks consist of 2P -NPSFs and wNPSF &wSPF 1s. The reasonableness of the two subclasses will be discussed in the following.

Reasonableness of 2P-NPSFs

2P -NPSFs are based on wNPSFs. This fault class makes only sense if the two combined wNPSFs have the same base cell. It consists of 10 possible fault types; see Table 3.4. In the following, the reasonableness of each fault type will be discussed. 1. The 2P -NPSFs: wANPSF &wANPSF , wANPSF &wDNPSF , and wDNPSF &wDNPSF The wANPSFs and the wDNPSFs may be caused by resistive or capacitive coupling, or leakage currents from neighborhood cells. A more subtle fault, however, would cause degradation in the integrity of the stored data in the base cell due to a single operation (write or read) in a deleted neighborhood cells, but such degradation is not strong enough to modify the state of the victim cell. Two simultaneous such operations in two-deleted neighborhood cells, however, would have a stronger eect on the victim cell resulting in a larger degradation of the stored data in the victim cell and may be changing its value. Therefore the three 2P -NPSF types, i.e., wANPSF &wANPSF , wANPSF &wDNPSF , and wDNPSF &wDNPSF are realistic fault for 2P memories. 2. The 2P -NPSFs: wPNPSF &wANPSF and wPNPSF &wDNPSF The wPNPSF partially prevents a victim cell from being set or reset, if the deleted neighborhood cells have some enabling value. This eect can be compounded by the presence of a wANPSF or a wDNPSF . Therefore the two 2P -NPSF types: wPNPSF &wANPSF and wPNPSF &wDNPSF are realistic fault. 3. The 2P -NPSF : wPNPSF &wPNPSF This fault type can only occur if the 2P memory allows for two simultaneous write operations to a single cell; hence, in order to sensitize a wPNPSF &wPNPSF fault, two simultaneously transition write operations have to be applied to the same cell (i.e., the base cell). A wPNPSF is generally caused by resistive or capacitive coupling, or leakage currents from neighborhood cells, and it partially prevents the victim cell to make a transition , if the deleted neighborhood cells have some enabling value. The presence of two wPNPSFs can have an additive eect, such that a fault may be sensitized. Hence, the 2P -NPSF type: wPNPSF &wPNPSF is a realistic fault for memories which allow for two simultaneous write operations to a single cell. 4. The 2P -NPSFs: wSNPSF &wNPSF , whereby wNPSF 2 fwANPSF; wPNPSF;

wSNPSF; wDNPSF g

These fault types require at most a single operation, since to sensitize a wSNPSF no read or write operation is needed. The wSNPSF requires that the deleted neighborhood cells have some enabling value, irrespective the number of ports. According


42

to Lemma 1, the 2P -NPSF types: wSNPSF &wSNPSF , wSNPSF &wANPSF , wSNPSF &wPNPSF , and wSNPSF &wDNPSF are not realistic fault.

Reasonableness of wNPSF&w1PF1 faults

This subclass is based on a combination of a w1PF 1 and a wNPSF . The w1PF 1 has to be present in the base cell of the wNPSF . 1. The 2PFk: wTF &wANPSF , wTF &wDNPSF , wRDF &wANPSF , and wRDF &wDNPSF A wTF can be caused by a parasitic transistor between a cell's node and a pass transistor, which partially prevents a cell from being set or reset, while a wRDF occurs when the resistive value of the on-transistor is too high, such that the voltage of the on-node is raised excessively when the cell is being read. These eects can be compounded by the presence of a wANPSF or a wDNPSF (which cause their base cell to take on a xed value) if their base cell is the cell where the wTF (or wRDF ) is present. Hence the 2PFks: wTF &wANPSF , wTF &wDNPSF , wRDF &wANPSF , and wRDF &wDNPSF are realistic fault types. 2. The 2PFk: wTF &wPNPSF This fault type occurs only if the 2P memory allows for two simultaneous write operations to a single cell. A wTF partially prevents a cell from being set or reset. A wPNPSF , which is generally caused by resistive or capacitive coupling, or leakage current, also partially prevents the victim cell to make a transition , if the deleted neighborhood cells have some enabling value. The combined fault eect of wTF and wPNPSF may be additive, such that a fault is sensitized. Therefore, the 2PFk: wTF &wPNPSF is a realistic fault type. 3. The 2PFk: wRDF &wPNPSF MP memories are subjected to certain restrictions; namely, no cell can be written by more than one port concurrently with inconsistent data values, and no cell can be read and written at the same time. To sensitize the wRDF &wPNPSF fault in SRAMs, a single cell has to be read and written simultaneously. Since this is not allowed in 2P memories, the 2PFk: wRDF &wPNPSF is not a realistic fault type. 4. The 2PFks: wSNPSF &wTF and wSNPSF &wRDF These fault types require only a single operation, since to sensitize a wSNPSF no read or write operation is needed. The wSNPSF requires that the deleted neighborhood cells have some enabling value, irrespective the number of ports. According to Lemma 1, the 2P -NPSFs: wSNPSF &wTF , and wSNPSF &wRDF are not realistic fault types.

Reasonableness of 2PF(k + 1)s

2PF (k + 1)s are based on wCF and wNPSF , i.e, wCF &wNPSF ; whereby the victim cell of the wCF and the base cell of the wNPSF are the same. The reasonableness of each fault type


43

of the Table 3.6 will be discussed in the following. 1. The 2PF(k + 1)s: wANPSF &wCFid , wANPSF &wCFds , wDNPSF &wCFid , and wDNPSF &wCFds wANPSFs and wDNPSFs may be caused by resistive or capacitive coupling, or by leakage currents from neighborhood cells. A more subtle fault, however, would cause degradation in the integrity of the stored data in the base cell due to a single operation (write or read) in a deleted neighborhood cells, but such degradation is not strong enough to modify the state of the victim cell. The presence of a wCFid , or a wCFds at the same time, however, can be combined with a wNPSF , and would have a stronger effect on the victim cell resulting in a larger degradation of the stored data in the victim cell. Therefore, may be changing its value. Hence The 2PF (k + 1)s: wANPSF &wCFid , wANPSF &wCFds , wDNPSF &wCFid , and wDNPSF &wCFds are realistic fault types. 2. The 2PF(k + 1)s: wPNPSF &wCFid and wPNPSF &wCFds A wPNPSF , which is generally caused by resistive or capacitive coupling, or by leakage current, partially prevents the base cell to make a transition , if deleted neighborhood cells have some enabling value. This eect can be compounded by the presence of a wCFid or a wCFds (which cause their victim cell to take on a xed value) if their victim cell is the same as the base cell of the wPNPSF . Therefore, the 2PF(k + 1)s:wPNPSF &wCFid and wPNPSF &wCFds are realistic fault types. 3. The 2PF(k + 1)s: wSNPSF &wCF and wNPSF &wCFst This types require at most a single operation, since to sensitize a wSNPSF or a wCFst , no read or write operation is needed. According to Lemma 1, the 2PF(k+1)s: wSNPSF &wCF and wNPSF &wCFds are not realistic fault types.

3.2.3 2P memory address decoder faults

According to the 2P memory model, which is a subclass of the MP memory model, each port has its own row decoder and column decoder. For a fault-free decoder operation, each address in the address space should access one and only one memory cell, which is not accessed by any other address. In addition, each cell should be uniquely accessed by the same address from either port. Faults in address decoders for 2P memories can be divided into two classes: AFs involving a single port (noted as AF 1s), and AFs involving two ports (noted as AF 2s). AF 1s are AFs that occur in a 1P memory. AF 1s are classi ed into no access faults and multiple access faults; while AF 2s consist of AFs based on port interference; see Figure 3.17.

2P-AF involving a single port: AF1s

This class of 2P -AFs consists a 1P memory address decoder faults. This is evident, since all AFs which can occur in a SP memory, can also occur in a 2P memory. SP -AFs are divided into no access faults, and multiple access faults; they are discussed in Section 3.1.2.


44

2P address decoder faults ( 2P-AFs)

AF involving a single port AF1

No access fault

AF involving two ports AF2


Port interference faults

Figure 3.17: Classi cation of address decoder faults in 2P memory

2P-AFs involving two ports: AF2s

This fault class is based on the interference between the two dierent ports; that means shorts (i.e., bridging faults) between wires of the two dierent ports (Opens cannot cause port interference; they belong to the class AF1). In order to establish a set of fault models for the class of AF2s, shorts will be injected in the electrical circuits of the two address decoders; thereafter, functional faults will be derived, based on the shorts at the electrical level. Figure 3.18(a) shows two simple, fault free, address decoder circuits; one for the port 1 and one for the port 2. The decoders as well as their inputs are independent; i.e., they can access two dierent locations (or the same location) at any given time. Figure 3.18(b) and (c) give equivalent circuits with three injected shorts: (1) a short between the two outputs lines of the two decoders (SOO), (2) a short between an internal line of one decoder and the output line of the second decoder (SIO), and (3) a short between two internal lines of the two decoders (SII). A0 A1 A2 A3

Row X

A4 A5 A6 A7

A0 A1 A2 A3 A4 A5 A6 A7

Row X

A0 A1 A2 A3

Row X

A4 A5 A6 A7

I1

I1

Addres decoder Port 1 SII B0 B1 B2 B3

Row Y

B4 B5 B6 B7

B0 B1 B2 B3 B4 B5 B6 B7

SIO

SOO

SII B0 B1 B2 B3

I2

Row Y

SIO

SOO

I2

B4 B5 B6 B7

Row Y

Address decoder Port 2

(a) Fault free address decoders

(b) Address decoders without inversion, and with three shorts

(c) Address decoders with inversion, and with three shorts

Figure 3.18: Simple address decoders for 2P memories To simplify the description of AF2s, the following notation will be used:


45

A1X (A2X ) denotes that row (column) line X is selected via port 1 (2) by an address. In the fault free case A1X has to access some cell Cx via port 1. Cx1 denotes that the cell Cx in row (column) X is accessed via port 1. The cell Cx can be

in any column (row). A1 denotes that no row (column) is selected via port 1. C1 denotes that no cell is accessed via port 1. A1X : A2Y denotes that the two rows (columns), X via the port 1 and Y via the port 2, are selected simultaneously. Cx1 : Cy2 denotes that the two cells, Cx via port 1 and Cy via port 2, are accessed simultaneously. 1 denotes that row (column) X is not selected via port 1; however port 1 may well be AX used to select any row (column) W 6= X or no row (column); i.e., AX1 means: A1W , with W 6= X , or A1 . In the remainder of this section we will focus on the row address decoders; the same applies to column address decoders.

Electrical behavior of the defective circuit In the following the electrical behavior of the circuits will be discussed in the presence of each of the shorts shown in Figure 3.18; an overview is given in Table 1.

SOO: Short between the output lines

The presence of the short SOO in the address decoders (see Figure 3.18(b) and (c)) may cause a fault; depending on the logic value of the output lines, two cases can be distinguished:

A. Fault absent. This is the case when the two output lines have the same logic value (high

or low); i.e., (1) the two rows, X via the port 1 and Y via the port 2, are selected simultaneously (i.e., A1X : A2Y ), or (2) are both not selected (i.e., A1W : A2Z ; W 6= X and Z 6= Y ; A1W denotes that port 1 intends to select row W, rather than X, which means that the decoder for row X is not used). Note that row X and row Y can access the same cell; the decoder circuits then behave as if no short is present. In short, the two cases can be described as: 1. If A1X : A2Y then Cx1 : Cy2 2. If A1W : A2Z ; W 6= X and Z 6= Y then Cw1 : Cz2

B. Fault present. This is the case when the two output lines have opposite logic values; i.e.,

only row X or row Y is selected (i.e., A1X : AY2 or AX1 : A2Y ); see Figure 3.18(b) and (c). Assume the case A1X : AY2 , then depending on the value of the resistance of the bridge, four sub-cases can be distinguished [Renovell 1995, 1996]. Note that port 2 can be used to select row Z 6= Y , or no row. 1. Both output lines have a high logic value. That means that the selection of row X (i.e., A1X ) has as consequence an erroneously selection of row Y (i.e., A2Y ); whereby Y can access any cell, which may be the cell Cx . If A1X : AY2 then Cx1 : Cy2


46

2. Both output lines will have a low logic value. That means that A1X has as consequence that no cell will be accessed; i.e., If A1X : AY2 then C1 : C2 3. The output line corresponding to row X has a high logic value and the output line corresponding to row Y has a low logic value. The circuits behave as if the fault is absent. 4. The output line corresponding to row X has a low logic value and the output line corresponding to row Y has a high logic value. In this sub-case the A1X has as consequence C1 since row X becomes low. In addition, the cell Cy2 will be accessed since row Y becomes high. If A1X : AY2 then C1 : Cy2

SIO: Short between an internal and an output line

A similar way as used for the short SOO will be followed in order to analyze the electrical behavior of the address decoders in the presence of the short SIO. We will assume that the driver of the output line of the address decoder (i.e., row or column) is stronger than the driver of any internal line. Two cases are distinguished: fault absent and fault present.

A. Fault absent. The output line and the internal line have the same logic values. Depending on the type of address decoder circuits, without or with inversion (see Figure 3.18(b) and (c)), this will require the simultaneous selection of row X and row Y, or the selection of only one of them; see below. Without inversion: This requires that the two rows have to be selected simultaneously (see Figure 3.18(b)): row X via port 1 and some other row with I 2 = 1 (i.e., B0 through B3 = 1) via port 2; for the latter, row Y may be selected. Alternatively both rows are not selected. That is: If A1X : A2Y then Cx1 : Cy2 If A1W : A2Z , W 6= X and Z 6= Y , then Cw1 : Cz2 With inversion: The output line (i.e., row X) and the internal line (i.e., I2; for which address Y will be chosen) have the same logic value, which means that at most one of the two rows, X or Y, is selected; see Figure 3.18(c). That is: If A1X : A2Z , Z 6= Y , then Cx1 : Cz2 ; row X selected. If A1W : A2Y , W 6= X , then Cw1 : Cy2 ; row Y selected. This can be rewritten in a more compact form as follows: If A1W : A2Z , W 6= X or Z 6= Y , then Cw1 : Cz2

B. Fault present. This is the case when the output line and the internal line of the address

decoders have opposite logic values. By using the assumption that the output line driver is stronger than the internal line driver, two sub-cases can be distinguished; the two sub-cases will be discussed for each decoder type (i.e., without and with inversion). Without inversion; see Figure 3.18(b). The two sub-cases are the following: 1. The output line has a high logic value; the fault present case now requires that the internal line has a low logic value. This sub-case occurs when row X is selected (i.e.,A1X ) and


47

I 2 = 0. The presence of the short SIO will drive the internal line I2 to a high logic value. If a row Z via port 2 is selected (i.e., A2Z ); and A2Z requires the inputs B4 through B7 to be high, then A2Y ; i.e., row Y will be selected. Note that this has as consequence that three

cells may be accessed simultaneously. That is: If A1X : A2Z , Z 6= Y , then Cx1 : Cz2 : Cy2 2. The output line has a low logic value; the fault present case now requires the internal line has a high logic value. This occurs when AX1 and I 2 = 1. In this sub-case row Y can not be selected since the output line forces the internal line to low logic value. That is: If AX1 : A2Y then C1 : C2 With inversion; see Figure 3.18(c). The two sub-cases are described below. 1. The output line has a high logic value; the fault present case now requires the internal line has a low logic value. This sub-case occurs when the rows X and Y are selected simultaneously. Since the short SIO will drive the internal line to a high value, row Y will not be selected. That is: If A1X : A2Y then Cx2 : C2

2. The output line has a low logic value; the fault present case now requires the internal line has a high logic value. This occurs when both rows X and Y are not selected. If a row Z (Z 6= Y ) is selected via port 2 (A2Z ) and A2Z requires the inputs B4 through B7 to be low, then row Y will be selected erroneously. This is because the short SIO forces the internal line I2 to a low value. Note that port 1 may be used to select any row dierent from X. That is: If AX1 : A2Z , Z 6= Y , then C1 : Cz2 : Cy2

SII: Short between two internal lines

In a similar way as with the presence of the shorts SOO and SIO, the electrical behavior of the decoders in the presence of the short SII will be classi ed in the fault absent and the fault present cases.

A. Fault absent. This the case when the internal lines have the same logic values. That means,

for both types of the decoders, that the two rows X and Y are selected simultaneously, or both are not selected; see Figure 3.18(b) and (c). That is: If A1X : A2Y then Cx1 : Cy2 If A1W : A2Z , W 6= X and Z 6= Y , then Cw1 : Cz2

B. Fault present. This is the case when the two internal lines have opposite logic values.

Depending on the value of the resistance of the bridge, four sub-cases can be distinguished for decoders with- as well as for decoders without inversion. Without inversion: The two internal lines have dierent values only when one of the two input groups, A4 through A7 or B0 through B3 , is high; see Figure 3.18(b). Assume that A1X : AY2 , i.e., row X is selected and row Y is not selected (this requires that I 1 = 1 and I 2 = 0), then the following four cases can take place:


48

1. I 1 = 1 and I 2 = 1. Both internal lines have a high logic value. That means that A1X will force the the internal line I2 to be high. If A1X : A2Z , whereby the row Z requires the inputs B4 through B7 to be high, then row Y will be selected erroneously; i.e., A2Y , see Figure 3.18(b). Note that the simultaneous selection of two rows (X and Z) has as consequence that a third row will be selected. That is: If A1X : A2Z , Z 6= Y , then Cx1 : Cz2 : Cy2 2. I 1 = 0 and I 2 = 0. Both internal lines have a low logic value. Row X will be not selected since the line I1 is forced to a low logic value; see Figure 3.18(b). If A1X : AY2 then C1 : C2 3. I 1 = 1 and I 2 = 0. The internal line I1 has a high logic value and I2 has a low logic value; see Figure 3.18(b). This has no consequence since the circuits behave as if no short is present. 4. I 1 = 0 and I 2 = 1. The internal line I1 has a low logic value and I2 has a high logic value (Note that the 'good case' assumed I1 to be high and I2 to be low). Row X will be not selected, since the internal line I1 is forced to a low logic value. If A1X : AY2 then C1 : C2 With inversion: The two internal lines have dierent values when only one of the two input groups, A4 through A7 or B0 through B3 , is low (i.e., I 1 = 1 and I 2 = 0, or I 1 = 0 and I 2 = 1; see Figure 3.18(c)). Assume A1X : AY2 ; i.e., row X is selected and row Y is not selected (This requires that I 1 = 0 and I 2 = 1), then the following four cases can take place.

1. I 1 = 0 and I 2 = 0. Both internal lines have a low logic value. That means that the internal line I1 will force the the internal line I2 to be low. If A1X : A2Z , whereby the row Z requires the inputs B4 through B7 to be low, then row Y will be selected erroneously; i.e., A2Y , see Figure 3.18(c). Note that the simultaneous selection of two rows (X and Z) has as consequence that a third row will be selected. That is: If A1X : A2Z , Z 6= Y , then Cx1 : Cz2 : Cy2 2. I 1 = 1 and I 2 = 1. Both internal lines have a high logic value. Row X will be not selected since the line I1 is forced to high logic value; see Figure 3.18(c). If A1X : AY2 then C1 : C2 3. I 1 = 0 and I 2 = 1. The internal line I1 has a low logic value and I2 has a high logic value; see Figure 3.18(c). This has no consequence since the circuits behave as if no short is present. 4. I 1 = 1 and I 2 = 0. The internal line I1 has a high logic value and I2 has a low logic value. Row X will not be selected, since the internal line I1 is forced to a high logic value. If A1X : AY2 then C1 : C2


49

It will be clear from the above that both types of decoders have the same behavior in the presence of the short SII. Table 3.7 summarizes all faults discussed above; it lists the faults caused by each short for both types of decoders. For each fault a number is given. Note that Short SOO as well as Short SII cause the same faults in both types of the decoders; and that Fault SOO.2 and Fault SII.2 are the same, as well as Fault SIO.A.1 and Fault SII.1. That means that the faults caused by Short SII are covered by faults of shorts SOO and SIO. Therefore, and from now on, we will focus only on the faults caused by shorts SOO and SIO. In addition, it should be noted that each of faults of Table 1 occurs in two forms; e.g., for Fault SOO.1, the fault \If A1X : AY2 then Cx1 : Cy2 ", or the fault \If AX1 : A2Y then Cx1 : Cy2 " can occur. Table 3.7: The faults in the presence of the three shorts Short

Fault If A1X : A2Y then Cx1 : Cy2 SOO If A1X : A2Y then C1 : C2 If A1X : A2Y then C1 : Cy2 Without If A1X : A2Z , Z 6= Y; then Cx1 : Cz2 : Cy2 SIO inversion If A1X : A2Y then C1 : C2 With If A1X : A2Y then Cx2 : C2 inversion If A1X : A2Z , Z 6= Y , then C1 : Cz2 : Cy2 SII If A1X : A2Z , Z 6= Y , then Cx1 : Cz2 : Cy2 If A1X : A2Y then C1 : C2

Number Fault SOO.1 Fault SOO.2 Fault SOO.3 Fault SIO.A.1 Fault SIO.A.2 Fault SIO.B.1 Fault SIO.B.2 Fault SII.1 Fault SII.2

Detection property dAF 2 sAF 2 sAF 2 dAF 2 sAF 2 dAF 2 sAF 2 equivalent with SIO.A.1 equivalent with SOO.2

By inspecting AF2 faults shown in Table 3.7, it will be clear that they can be divided into two fault subclasses: (1) the fault subclass that involves only the use of a single port in order to be detected (abbreviated as sAF 2s), and (2) the fault subclass that involves the use of both ports in order to be detected (abbreviated as dAF 2s). The AF 2s involving a single port in order to be detected, sAF 2s, consist of the faults SOO.2, SOO.3, SIO.A.2 and SIO.B.2; see Table 1. They have the properties that: (1) the cell that the selected row intends to access (e.g., Cx ) will be not accessed successfully (Fault SOO.2, Fault SOO.3 and Fault SIO.A.2), or (2) multiple cells will be accessed via the same port (Fault SIO.B.2). Therefore, the faults SOO.2, SOO.3 and SIO.A.2 are equivalent with Fault A and Fault SIO.B.2 is equivalent with Fault D (see Figure 3); that means that sAF 2s are a subset of AF1s, and any test which detects Fault A and Fault D, also detects faults SOO.2, SOO.3 SIO.A.2 and SIO.B.2. Note that the test has to be performed in such way that when applied via one port, all rows via the other port have to be not selected since the sensitization of sAF 2s require that only one port has to be active at time. The above AFs, which will be detected by tests for AF1s, will be not considered from here on. The AF 2s involving the use of both ports in order to be detected, dAF 2s, consist of the faults SOO.1, SIO.A.1 and SIO.B.1; see Table 3.7. The fault SOO.1 requires the use of the two ports since the selection of a row via the rst port (e.g., A1X ) has as consequence that row Y


50

via the other port (e.g., A2Y ) will be selected; while the faults SIO.A.1 and SIO.B.1 require the simultaneous use of the two ports for their sensitization. To detect these faults new tests are needed. In the rest of this thesis we will focus only on testing AF 2s involving the use of two ports simultaneously; see Table 4.1. The third column of this table gives names for the three AF2s; it consists :

AFcwc : conditional wrong cell fault. This is Fault SOO.1: A1X : AY2 then Cx1 : Cy2 . That is: a cell is wrong accessed (e.g., Cy ) if another cell (e.g., cell Cx ) is addressed. AFcmc : conditional multiple cells fault. This is Fault SIO.A.1: If A1X : A2Z , Z 6= Y; then Cx1 : Cz2 : Cy2. That is: multiple cells are accessed if the two rows (columns) (e.g., X and

Z) are selected simultaneously. AFcnc : conditional no cell fault. This is Fault SIO.B.1: If A1X : A2Y then Cx2 : C2 . That is row (column) Y fails to access a cell Cy if row (column) X is selected at the same time. Table 3.8: The reduced set of AF2s Fault If A1X : AY2 then Cx1 : Cy2 If A1X : A2Z , Z 6= Y; then Cx1 : Cz2 : Cy2 If A1X : A2Y then Cx2 : C2

Name

AFcwc AFcmc AFcnc

Notation of AF2s

The notation of AF 1s is introduced in Section 3.1.2. This notation will be extended, such that it also can cover AF 2s, as follows:

< S1 : S2 ; F > denotes an AF2 faults

S1 (and S2 ) describes the condition to sensitize the fault (i.e., the selection, or not, of a

row (column)). \:" denotes the fact that the operations are applied simultaneously. F denotes the faulty behavior (the behavior after the sensitizing condition).

The capital letters of alphabet denote the memory address, while the lower case letters denote memory cells. In addition, ports to which each operation is applied are speci ed implicitly as follows: the rst operation is applied to port 1 (P1) and the second operation is applied to P2. The port numbers can also speci ed explicitly by super-scripting the selected row (column), and the accessed cell; e.g., X 1 denotes that the row X is selected via P1, and x1 denotes that the cell x is accessed via P1. Using the above notation, the faults of Table 4.1 can be represented as follows:


51

Fault AFcwc: < X : Y ; y2 > Fault AFcmc : < X : Z ; y2 > Fault AFcnc: < X : Y ; y2 >.

3.2.4 Faults in read/write logic

2P memories have two duplicated read/write circuits. Such circuits pass the data from the input/output pins to the memory cell array and visa versa. Faults occurring in these circuits can require no, one, or two sensitizing operations. Faults which require no or one sensitizing operation are the same faults which can occur in the read/write logic of SP memories. These faults are mapped onto faults in the memory cell array [Nair 1978], [van de Goor 1991]. However, for the NPSFs this can not be proven in general [van de Goor 1991]. Faults which require two operations (i.e., faults based on weak faults) can also mapped onto faults in the memory cell array. The data input lines or the data output lines may have a weak capacitive or resistive coupling between them. An algorithm that detects wCF &wCF faults in the memory cell array will also detects wCF &wCF faults in the read/write logic. This is because wCF &wCF in the read/write logic appears as a large group of wCF &wCF faults in the memory cell array. However, faults based on wNPSFs can not in general mapped onto the faults in the memory cell array. Similar arguments can be given as by NPSFs in read/write logic in SP memories.

3.2.5 Summary of functional faults in 2P memories

New memory cell array faults, and address decoder faults for 2P memories have been introduced together with their reasonableness. In this section, a summary of all realistic faults for 2P memories will be given.

The 2P memory faults are divided into 2P -MCAFs, 2P -AFs, and read/write circuit faults. The latter faults are mapped onto 2P -MCAFs.

2P-MCAFs:

The 2P -MCAFs are divided into 1P -MCAFs and MCAFs based on weak 1PFs (2PFs); see Figure 3.19:

1P -MCAFs: These faults are divided into three classes: 1. 1PF 1: This consists of four fault types, namely SAF , TF , RDF , and DRF . 2. 1PF 2: This consists of coupling faults: CFid , CFst , and CFds . 3. 1PFk: This consists of k?coupling faults; under other ANPSF , PNPSF , SNPSF , and DNPSF . MCAFs based on w1PF : These faults are classi ed into ve classes:


52

1. 2PF 1: This class consists only of one fault type: wRDF &wRDF . 2. 2PF 2: This class is divided into two subclasses: (a) w1PF 2&w1PF 1: This subclass has four fault types: wCFid &wTF , wCFds &wTF , wCFid &wRDF , and wCFds&wRDF . (b) w1PF 2&w1PF 2: This subclass has three fault types: wCFid &wCFid , wCFid &wCFds, and wCFds &wCFds . 3. 2PF 3: This class has three fault types: wCFid &wCFid , wCFid &wCFds, and wCFds &wCFds . 4. 2PFk: This class is divided into two subclasses: (a) w1PFk&w1PFk: This fault subclass consists of six fault types, namely wFi &wFj whereby fwFi ; wFj g fwANPSF; wPNPSF; wSNPSF; wDNPSF g. (b) w1PFk&w1PF 1: This fault subclass has ve fault types: wANPSF &wTF , wPNPSF &wTF , wDNPSF &wTF , wANPSF &wRDF , and the fault type wDNPSF &wRDF . 5. 2PF (k + 1): This class consists of six fault types, namely wFi &wFj whereby wFi 2 fwANPSF; wPNPSF; wDNPSF g, and wFj 2 fwCFid ; wCFds g 2P -MCAFs

MCAFs based on weak 1PFs

1P-MCAFs

SPF1s

SPF2 s

SAF

CFid

SPF k s

ANPSF

2PF1s

wRDF&wRDF

2PF2s

2PF3s

wCF &wTF id

2PF k s

wCF &wCF id

id

TF

CF st

PNPSF

wCF &wTF

wCF & wCFds

DRF

CFds

SNPSF

wCFid &wRDF

wCFds & wCFds

DNPSF

wCFds &wRDF

RDF

ds

wCF &wCF id

id

wANPSF&wANPSF wANPSF&wPNPSF

id

wCFds & wCFds

wANPSF&wCF

id

wANPSF&wCF

ds

wANPSF&wDNPSF wPNPSF&wPNPSF wPNPSF&wDNPSF wDNPSF&wDNPSF

wPNPSF&wCF

id

wPNPSF&wCF

ds

wDNPSF&wCF

id

id

wCF & wCFds

2PF(k+1) s

wANPSF&wTF wPNPSF&wTF wDNPSF&wTF wANPSF&wRDF wDNPSF&wRDF

wDNPSF&wCF

Figure 3.19: Overview of all realistic 2P-MCAFs

2P-AFs:

2P -AFs have been divided into two classes: AFs involving a single port (AF 1s), and AFs involving two ports (AF 2s); see Figure 3.20: :

ds


53

The AF 1s: AF 1s, i.e., SP -AFs consist of the following faults: AFnca : < X=x > AFnmc : < X=x > # < Y ; x > AFnma : < Y ; x; y > AFmca : < Y ; x >. The AF 2s: The AF 2s are based on port interference. They consist of the following: AFcwc : < X : Y ; y2 > AFcmc : < X : Z ; y2 > AFcnc : < X : Y ; y2 >. 2P-AFs

AF1s

AF2s

Figure 3.20: Overview of all 2P-AFs

3.2.6 Classi cation of functional faults in 2P memories

From a testing point view, faults in 2P memories can be divided into the following classes: 1. Cell faults These faults are not related to a speci c port, but to the memory cell. Once tested for, via any port, they do not have to be retested via any other port, since they are port independent. This class consists of SAFs, DRFs, CFst s, and SNPSFs. 2. Port faults These faults are related to a speci c port. This class consists of the faults RDFs, TFs, SOFs, CFid s, CFdss, ANPSFs, PNPSFs, DNPSFs, and the AF 1s (namely the faults A, B, C, and D). Since these faults are port dependent, they have to be tested for via each port separately. 3. Two-port faults These are faults which can only be sensitized using two ports. This class of faults consists


54

of the 2PF 1s, 2PF 2s, 2PF 3s, 2PFks, 2PF (k + 1)s, and the AF 2s faults (namely the faults E, F, and G). Since such faults depend on two ports, they have to be tested for all two port combinations that can occur in the 2P memory.

Chapter 4

Tests for two-port memories This chapter starts with introducing the notation for march tests, which will be extended in order to be able to specify tests for MP memories. Then, the conditions for detecting the memory cell array faults in 2P memories, introduced in Chapter 3, will be given. These conditions will be used to derive tests. Finally, tests for address decoder faults in 2P memories will be covered

4.1 Notation for march tests A march test consists of a nite sequence of march elements [Suk, 1981]. A march element is a nite sequence of operations applied to every cell in the memory before proceeding to the next cell. The way one proceeds to the next cell is determined by the address order which can be an increasing address order (e.g., increasing address from the cell 0 to the cell n ? 1), denoted by * symbol, or a decreasing address order, denoted by + symbol, and which is the exact inverse of the * address order. When the address order is irrelevant, the symbol m (i.e., * or +) will be used. Moreover, an index can be added to the address symbol, such that the addressing range ?1 denotes: increase the addresses from the cell 0 to can be explicitly speci ed. For example *in=0 the cell n ? 1. An operation can consist of: w0: write 0 into a cell. w1: write 1 into a cell. r0: read a cell with expected value 0. r1: read a cell with expected value 1. In addition, the cell to which the operation is applied can be explicitly given by subscripting the operation. For example, w0i means write 0 into a cell i (i.e., ci ). A complete march test is delimited by the 'f:::g' bracket pair; while a march element is delimited by the '(:::)' bracket pair. The march elements are separated by semicolons, and the operations within a march element are separated by commas. The MATS+ march test [Abadir 1983] fm (w0); * (r0; w1); + (r1; w0)g consist of the march elements m (w0), * (r0; w1), and + (r 1; w0). In order to make the notation and the concepts more clear, the MATS+ algorithm 55

CHAPTER 4. TESTS FOR TWO-PORT MEMORIES

56

is shown in Figure 4.1. Note that all operations of a march element are performed at a certain address, before proceeding to the next address. +-----------------------------------------------------------------------------+ | | | for all i // 0v . The rst pair of simultaneous read operations through the two ports in each march element sensitize the fault, which will be detected by the second pair of simultaneous read operations. Note that the second pair of simultaneous read operations can be replaced by a single read operation through a single port. However, by reading a cell through the two ports, the cell becomes more loaded.

4.2.2 Conditions for detecting 2PF2s

The 2PF 2 fault class consists of two subclasses: w1PF 2&w1PF 1, and w1PF 2&w1PF 2. Note that in the latter subclass, the two wCFs have the same aggressor cell and the same victim cell. The conditions to detect faults of each subclass will be discussed separately.


59

Conditions for detecting the 2PF2s: w1PF 2&w1PF 1

This subclass consists of four fault types: wCFi &wTF and wCFi &wRDF whereby wCFi 2 fwCFid ; wCFds g. First we will develop conditions to detect wCFi &wTF faults, and thereafter conditions to detect wCFi &wRDF faults. To simplify the description of the conditions, the following notation will be used:

w ": up transition, i.e., write 1 into a cell containing 0. w #: down transition, i.e., write 0 into a cell containing 1.

Conditions for detecting wCFi &wTF faults This fault subclass consists of two fault types, namely wCFid &wTF and wCFds &wTF . Each of these types has four subtypes. The wCFid &wTF consists of , , and ; while the wCFds &wTF consists of < w1 :" =0 >, < w1 :# =1 >, < w0 :" =0 >, and < w0 :# =1 >. To detect the presence of such faults in a cell cv whereby v 2 f0; 1; 2; :::; n ? 2; n ? 1g, we have: 1. to select all pairs (ca ; cv ) whereby a 2 f0; 1; :::; v ? 1; v + 1; :::; n ? 2; n ? 1g, 2. to apply sensitizing operations to the two cells, 3. to read the cell cv . The order in which cv will be selected is not important, the only requirement is that v has take ?1. on all values from the set f0; 1; 2; :::; n ? 2; n ? 1g. The select order can be given as follows: mvn=0 In addition, the order in which ca will be selected is also not important; the only requirement is that a has to take on all values from the set f0; 1; :::; v ? 1; v + 1; :::; n ? 2; n ? 1g. Therefore, the select order can be given as follows: mva?=01 and man=?v1+1 . Based on the above select order for cv and ca , Condition 2PF2.1 can be composed. This condition has to be satis ed in order to detect any wCFid &wTF s and wCFds &wTF s. Condition 2PF2.1 Any wCFid &wTF and wCFds &wTF is detectable by a march test if the test contains both march elements of Case A, of Case B, of Case C, and of Case D. These eight march elements can be combined into one, two, three, four, ve, six, or seven march elements.

Case A (to detect and < w1 :" =0 >) ?1 (mv?1 (:::; w "a : w "v ; ? : r1v ; :::)) ; mn?1 (mn?1 (:::; w "a : w "v ; ? : r1v ; :::)) { mvn=0 a=0 v=0 a=v+1

Case B: (to detect and < w0 :# =1 >) ?1 (mv?1 (:::; w #a : w #v ; ? : r0v ; :::)) ; mn?1 (mn?1 (:::; w #a : w #v ; ? : r0v ; :::)) { mvn=0 a=0 v=0 a=v+1


Case C: (to detect ) ?1 (mv?1 (:::; w #a : w "v ; ? : r1v ; ::)) ; mn?1 (mn?1 (:::; w #a : w "v ; ? : r1v ; :::)) { mvn=0 v=0 a=v+1 a=0

Case D: (to detect , and < w1 : r0=1 >) ?1 (mv?1 (:::; w "a : r0v ; ? : r0v ; :::)) ; mn?1 (mn?1 (:::; w "a : r0v ; ? : r0v ; :::)) { mvn=0 a=0 v=0 a=v+1

Case C: (to detect and < w0 : r0=1 >) ?1 (*v?1 (:::; w #a : r0v ; ? : r0v ; :::)) ; mn?1 (mn?1 (:::; w #a : r0v ; ? : r0v ; :::)) { mvn=0 a=0 v=0 a=v+1

Case D: (to detect a;v , when v > a; while the operation \ w #a : r1v " in the second march element will sensitize the same faults when v < a . The operation \ ? : r1v " in both march elements will detect the faults. Similar explanations can be given for Case B, Case C, and Case D.

Conditions for detecting the 2PF2s: wCFi &wCFi, wCFi 2 fwCFid ; wCFds g

This subclass, which consists of three fault types, can be reduced to the wCFid &wCFid and wCFds &wCFds types. The third type, namely wCFid &wCFds is the same as the wCFid &wCFid , since it involves that the single aggressor cell has to make a transition (e.g., ") and has to be written with some data value (e.g., 1) at the same time. Therefore, an up transition is the same as w1 operation, and a down transition is the same as w0 operation. Either wCFid &wCFid and wCFds &wCFds consists of four fault subtypes; the wCFid &wCFid consists of: , and ; while the wCFds &wCFds consists of: < w1 : w1; ">, < w1 : w1; #>, < w0 : w0; ">, and < w0 : w0; #>. In order to detect any simple wCFi &wCFi, we have: 1. to apply sensitizing operations to a cell ci ; i 2 f0; 1; 2; :::; n ? 2; n ? 1g 2. to detect the fault in cell cv ; v 6= i ?1 address order can The order in which ci has to be selected is not relevant. Therefore, the min=0 be speci ed.

Condition 2PF2.3 Any simple wCFi &wCFi , whereby wCFi 2 fwCFid ; wCFds g, is detectable by a march test which contains both march elements of Case A and both march elements of Case B.

Case A: (to detect < Si : Si; 1 > whereby Si 2 f"; #; w1; w0g) { min=0?1 (r0 : ?; :::; w ": w "; :::; w #: w #) ; min=0?1 (r0 : ?; :::) Case B: (to detect < Si : Si ; 0 > whereby Si 2 f"; #; w1; w0g) { min=0?1 (r1 : ?; :::; w #: w #; :::; w ": w ") ; min=0?1 (r1 : ?; :::)

Condition 2PF2.3 can be explained as follows: the operations in the rst march element of Case A will sensitize all wCFid &wCFid and wCFds &wCFds faults when the value of the fault eect is 1, because that march element contains all sensitizing operations. If the address order of i is increasing , then Case A will detect the fault by the r0 operation of the rst march element when the victim cell has a higher address than the aggressor cell (i.e., v > i), and by r0 operation of the second march element when v < i. If the address order of i is decreasing, then Case


62

A will detect the fault by the r0 operation of the rst march element when v < i, and by r0 operation of the second march element v > i. A similar explanation can be given for Case B which is required to sensitize and to detect the wCFid &wCFid and wCFds &wCFds faults, when the value of the fault eect is 0.

4.2.3 Conditions for detecting 2PF3s

The 2PF 3 fault class consists of three fault types, namely wCFid &wCFid , wCFds &wCFds , and wCFid &wCFds . The wCFid &wCFid fault type has eight fault subtypes: < S1 : S2 ; "> and < S1 : S2 ; #>, whereby Si 2 f"; #g (i = 1 or i = 2). The wCFds &wCFds also has eight subtypes: < S1 : S2 ; "> and < S1 : S2 ; #>, whereby Si 2 fw0; w1g; while the wCFid &wCFds has sixteen subtypes: < S1 : S2 ; "> and < S1 : S2 ; #>, whereby Si 2 f"; #; w0; w1g. In total, 2PF 3 consists of 32 faults. To detects these faults we have: 1. to select a pair of aggressor cells (ci ; cj ) whereby i 6= j , 2. to apply all sensitizing operations to (ci ; cj ), 3. to detect the fault in cell cv whereby v 6= i and v 6= j . To select (ci ; cj ), rst we select ci . The order in which this is done is not important; the only requirement is that i has to take on all values from the set f0; 1; 2; :::; n ? 2; n ? 1g. Therefore, ?1 the select order of ci can be given as: min=0 To select cj , for a given ci , j has to satisfy one of the two following requirements:

take all values from the set f0; 1; 2; :::; i ? 2; i ? 1g, take all values from the set fi + 1; i + 2; :::; n ? 2; n ? 1g

This is because the pair of aggressor cells (ci ; cj ) is the same as (cj ; ci ). If j satis es the rst requirement, then its selected order can be increasing from 0 to i ? 1 or decreasing from i ? 1 to 0. This can be given as: mij?=01 . In the other case (i.e., j satis es the second requirement), the select order of j can be given as mjn=?i1+1. Based on the above discussion, Condition 2PF3, which detect all simple 2PF 3 faults, can be composed. Condition 2PF3 Any simple 2PF 3 fault is detectable by a march test which contains one of the two pairs of march elements of Case A, of Case B, of Case C, and of Case D.

Case A: (to detect , < w1 : w1; ">, < w0 : w0; ">, , ) ?1 (mn?1 (r0j : r0i ; :::; w "j : w "i ; :::; w #j : w #i )) ; m (r0 : ?; :::) 1. min=0 j =i+1


63

?1 (mj =i?1 (r0j : r0i ; :::; w "j : w "i ; :::; w #j : w #i )) ; m (r0 : ?; :::) 2. min=0 0

Case B: (to detect , , < w1 : w0; ">, and < w0 : w1; ">, , ) ?1 (mn?1 (r0j : r0i ; :::; w "j : w #i ; :::; w #j : w "i ; n : w0i )) ; m (r0 : ?; :::) 1. min=0 j =i+1 ?1 (mj =i?1 (r0j : r0i ; :::; w "j : w #i ; :::; w #j : w "i ; n : w0i )) ; m (r0 : ?; :::) 2. min=0 0

Case C: (to detect , , < w0 : w0; #>, and < w1 : w1; #>, , and < w0 :#; #>) ?1 (mn?1 (r1j : r1i ; :::; w #j : w #i ; :::; w "j : w "i )) ; m (r1 : ?; :::) 1. min=0 j =i+1 ?1 (mj =i?1 (r1j : r1i ; :::; w #j : w #i ; :::; w "j : w "i )) ; m (r1 : ?; :::) 2. min=0 0

Case D: (to detect , < w0 : w1; #>, and < w1 : w0; #>, , , and < w1 :#; #> ) ?1 (mn?1 (r1j : r1i ; :::; w #j : w "i ; :::; w "j : w #i ; n : w1i )) ; m (r1 : n; :::) 1. min=0 j =i+1 ?1 (mj =i?1 (r1j : r1i ; :::; w #j : w "i ; :::; w "j : w #i ; n : w1i )) ; m (r1 : n; :::) 2. min=0 0

Condition 2PF3 can be explained as follows: the operations in the rst march element in Case A.1 will sensitize the faults: , < w1 : w1; ">, < w0 : w0; ">, , < w1 :"; ">, . If j has an increasing order, then the faults will be detected by the read operation of the rst march element (i.e., \ r0j : r0i ") when the victim cell cv has a higher address than the aggressor cells (i.e., i < j < v) or when i < v < j , and by the read operation of the second march element when v < i < j . A similar explanation can be given if j has a decreasing order. Case A.2 has similar capabilities, except that j takes values from the set fi + 1; i + 2; :::; n ? 2; n ? 1g instead of the set f0; 1; :::; i ? 2; i ? 1g. In Case C, the same faults as in Case A will be detected , except that the value of the fault eect is #. Similar explanations can be given for Case B and Case D. It should be noted that operation \n : w0i " is added to the rst march element of Case B (and Case C), such that the contents of all cells after the rst march element will be 0 (1); which is the expected value of the read operation of the second march element.

4.3 Tests for 2PFs This section describes tests for 2P memory faults. These are divided into SP -MCAFs and MCAFs based on weak SP -MCAFs (i.e., 2PFs). Therefore the test procedure for 2P memories can be divided into two parts:


64

1. Test(s) to detect simple (and linked) SP -MCAFs. For these tests see [van de Goor 1991, 1996, 1997]. 2. Test(s) to detect 2PFs. These tests are described below. Below, new tests for detecting 2PFs will be developed; they are functional tests since they are independent of the memory structure. It should be noted that 2PFs can not be detected with SP march tests.

4.3.1 Test for the 2PF1 fault class

The test of Figure 4.3, referred as March 2PF1, detects all 2PF 1 faults (i.e., wRDF &wRDF faults), since it satis es the Condition 2PF1 of Section 4.2.1. Note that the write operation can also be performed through the two ports simultaneously and that the two march elements can be integrated into a single march element. March 2PF1 has a test length of 6n, whereby n is the size of the memory. fm (w0 : ?; r 0 : r 0; r 0 : r 0); m (w1 : ?; r 1 : r 1; r 1 : r 1)g

M0

M1

Figure 4.3: March 2PF1: march test for 2PF1s


The class of 2PF 2 faults consists of two subclasses: w1PF 2&w1PF 1s, and w1PF 2&w1PF 2s. The tests for each subclass will be discussed separately.

Test for w1PF 2&w1PF 1 fault subclass

Similar to the way followed for developing the test conditions, the tests for wCFi &wTF and wCFi &wRDF , whereby wCFi 2 fCFid ; CFds g, will be given separately. Thereafter, a march test detecting all w1PF 2&w1PF 1 faults will be given.

Test for wCFi &wTF s:

March 2PF2.1.1 shown in Figure 4.4 detects all wCFi &wTF s, since it satis es Condition 2PF2.1 of Section 4.2.2: the second march element of the test (i.e., M1 ) contains the rst march element of both Case A and Case B; while M2 contains the second march element of Case A and of Case B. In addition, M3 contains the rst march element of both Case D and of Case C; while M4 contains the second march element of Case D and of Case C. Note that n can be replaced in some march elements with other operations. For example, in the second operation of M1 , it can be replaced with any allowed operation, except with w0a and w0v . March 2PF2.1.1 has a test length of:

n + n(4 n?2 1 ) + n(4 n?2 1 ) + n(6 n?2 1 ) + n(6 n?2 1 ) = 10n2 ? 9n


?1 (mv?1 fm (w0 : ?) ; mvn=0 a=0

M0

?1 (mn?1 mvn=0 a=v+1

?1 (mv?1 mvn=0 a=0

65

(w1a : w1v ; n : r1v ; w0a : w0v ; n : r0v )) ;

M1

(w1a : w1v ; n : r1v ; w0a : w0v ; n : r0v ));

M2

(n : w1v ; w1a : w0v ; n : r0v ; w0a : w1v ; n : r1v ; n : w0v ));

?1 (mn?1 mvn=0 a=v+1

M3

(n : w1v ; w1a : w0v ; n : r0v ; w0a : w1v ; n : r1v ; n : w0v ))g

M4

Figure 4.4: March 2PF2.1.1 : march test for wCFi &wTF faults

Test for wCFi &wRDF

March 2PF2.1.2 shown in Figure 4.5 detects all wCFi &wRDFs, since it satis es Condition 2PF2.2 of Section 4.2.2: M1 contains the rst march element of Case B and of Case C; while M2 contains the second march element of Case B and of Case C. In addition, M4 contains the rst march element of Case A and of Case D; while M5 contains the second march elements of Case A and of Case D. March 2PF2.1.2 has a test length of:

n + n(3 n?2 1 ) + n(3 n?2 1 ) + n + n(3 n?2 1 ) + n(3 n?2 1 ) = 6n2 ? 4n ?1 (mv?1 fm (w0 : ?) ; mvn=0 a=0

M0

?1 (mn?1 (w1a mvn=0 a=v+1

M1

: r0v ; w0a : r0v ; n : r0v )) ; m (w1 : ?)

M2

?1 (mv?1 (w0a mvn=0 a=0 ?1 (mn?1 mvn=0 a=v+1

(w1a : r0v ; w0a : r0v ; n : r0v ));

: r 1v ; w 1 a : r 1 v ; n : r 1 v ) ;

M3

M4

(w0a : r1v ; w1a : r1v ; n : r1v ))g

M5

Figure 4.5: March 2PF2.1.2: march test for wCFi &wRDF faults

Test for w1PF 2&w1PF 1

March 2PF2.1.1 and March 2PF2.1.2 can be integrated to become a single march test. Figure 4.6 shows March 2PF2.1 which detects all wCFi &wTF faults as well as all wCFi &wRDF faults:

{ Condition 2PF2.1 of Section 4.2.2 is satis ed as follows: M1 contains the rst march

element of both Case A and Case B; while M2 contains the second march element of Case A and of Case B. In addition, M3 contains the rst march element of both Case D and of Case C; while M4 contains the second march element of Case D and of Case C.


66

{ Condition 2PF2.2 of of Section 4.2.2 is satis ed as follows: M1 contains the rst march element of both Case A and Case D; while M2 contains the second march element of Case A and of Case D. In addition, M3 contains the rst march element of both Case C and of Case B; while M4 contains the second march element of Case C and of Case B.

March 2PF2.1 has a test length of:

n + n(6 n?2 1 ) + n(6 n?2 1 ) + n(8 n?2 1 ) + n(8 n?2 1 ) = 14n2 ? 13n ?1 (mv?1 fm (w0 : ?) ; mvn=0 a=0

M0

?1 (mn?1 mvn=0 a=v+1

(w1a : w1v ; w0a : r1v ; w1a : r1v ; n : r1v ; w0a : w0v ; n : r0v )) ;

M1


M2 : w0v ; w0a : r0v ; w1a : r0v ; n : r0v ; w0a : w1v ; n : r1v ; n : w0v )); M3 n ? 1 n ? 1 mv=0 (ma=v+1 (n : w1v ; w1a : w0v ; w0a : r 0v ; w1a : r 0v ; n : r 0v ; w0a : w1v ; n : r 1v ; n : w0v ))g M4

mv0=n?1 (m0a=v?1 (n : w1v ; w1a

Figure 4.6: March 2PF 2:1: march test for wCFi &wTF and wCFi &wRDF faults Furthermore, March 2PF 2:1 can easily be merged with March 2PF1 such that the obtained test will be able to detect wCFi &wTF and wCFi &wRDF faults as well as 2PF1 faults (i.e., wRDF &wRDF s). Figure 4.7 shows March 2PF2.1+ whose march elements are:

{ M0 : is a result of merging M0 of March 2PF 2:1 with M0 of March 2PF 1. { M1 , M2 , M3, and M4: are the same march elements as those of March 2PF 2:1 { M5 : is the same as M1 of March 2PF 1. Note that the test length of March 2PF2.1+ is: 3n + n(6 n?2 1 ) + n(6 n?2 1 ) + n(8 n?2 1 ) + n(8 n?2 1 ) + 3n = 14n2 ? 8n Figure 4.8 pictures the relationship between March 2PF 2:1:1, March 2PF 2:1:2, March 2PF 2:1, and March 2PF 2:1+. March 2PF 2:1 detects all faults detected by March 2PF 2:1:1 (i.e., wCFi &wTF s) as well as by March 2PF 2:1:2 (i.e., wCFi &wRDF s); while March 2PF 2:1+ detects the same faults as March 2PF 2:1:2, and in addition, it detects the faults of 2PF 1 fault class (i.e., wRDF &wRDF s).


fm (w0 : ?; r 0 : r 0; r 0 : r 0)

?1 (mv?1 mvn=0 a=0

M0

67

;


?1 (*n?1 mvn=0 a=v+1

M1


M2 : w0v ; w0a : r0v ; w1a : r0v ; n : r0v ; w0a : w1v ; n : r1v ; n : w0v )); M3 n ? 1 n ? 1 mv=0 (ma=v+1 (n : w1v ; w1a : w0v ; w0a : r 0v ; w1a : r 0v ; n : r 0v ; w0a : w1v ; n : r 1v ; n : w0v )); M4 m (w1 : ?; r 1 : r 1; r 1 : r 1)g M5 ?1 (mv?1 (n : w1v ; w1a mvn=0 a=0

Figure 4.7: March 2PF 2:1+: test for wCFi &wTF, wCFi &wRDF and wRDF &wRDF faults

March 2PF2.1.1 March 2PF1 March 2PF2.1.2 March 2PF2.1+

March 2PF2.1

Figure 4.8: Relationships between the introduced march tests

Test for w1PF 2&w1PF 2 fault subclass

This subclass consists of the wCFi &wCFi faults, wCFi 2 fwCFid ; wCFds g. March 2PF2.2, shown in Figure 4.9, detects all simple wCFi &wCFi , since it satis es Condition 2PF2.3 of Section 4.2.2: M1 and M2 contain the two march elements of Case A, while M3 and M4 contain the two march elements of Case B. March 2PF2.2 has test length of: n +3n +2n +3n + n = 10n. fm (w0 : ?) ; m (r 0 : ?; w1 : w1; w0 : w0) ; m (r 0 : ?; w1 : ?)

M0

M1 M2 m (r 1 : ?; w0 : w0; w1 : w1) ; m (r 1 : ?)g M3 M4

Figure 4.9: March 2PF2.2: march test for wCFi &wCFi

;


68


The 2PF 3 fault class consists of wCFi &wCFj faults, whereby wCFi 2 fwCFid ; wCFds g and wCFj 2 fwCFid ; wCFds g. All such simple faults will be detected with March 2PF3 shown in Figure 4.10, since the test satis es Condition 2PF3 of Section 4.2.3: M1 and M2 of March 2PF3 contain the rst pair of march elements of Case A; M3 and M4 contain the rst pair of Case B; M5 and M6 contain the second pair of Case C; while M7 and M8 contain the second pair of Case D. The test length of March 2PF3 is: n + n(3 n?2 1 ) + n + n(5 n?2 1 ) + 2n + n(3 n?2 1 ) + n + n(5 n?2 1 ) + n = 8n2 ? 2n ?1 (mn?1 fm (w0 : ?) ; min=0 j =i+1

M0

?1 (mn?1 min=0 j =i+1

(r0j : r0i ; w1j : w1i ; w0j : w0i )) ; m (r0 : ?) ;

M1

M2

(r0j : r0i ; n : w1i ; w1j : w0i ; w0j : w1i ; n : w0i )) ; m (r0 : ?; w1 : ?) ;

?1 (mi?1 min=0 j =0 ?1 (mi?1 min=0 j =0

M3

(r1j : r1i ; w0j : w0i ; w1j : w1i )) ; m (r1 : ?) ;

M5

M4

M6

(r1j : r1i ; n : w0i ; w0j : w1i ; w1j : w0i ; n : w1i )) ; m (r1 : ?)g

M7

M8

Figure 4.10: March 2PF3: march test for 2PF3s March 2PF3 can be extended such that it can cover the 2PF 2 subclass: w1PF 2&w1PF 2. Figure 4.11 shows the result of the extension. This requires a small modi cation: M2 of March 2PF3 will be extended with the sensitizing operations (i.e., \ w1 : w1" and \ w0 : w0") such that M2 and M3 will contain the pair of march elements of Case A of Condition 2PF2.2 (see Section 4.2.2). A similar modi cation is done for M6 of March 2PF3 such that it will together with M 7 contain the pair of march elements of Case B of Condition 2PF2.2. The resulting March 2PF3+ is shown in Figure 4.11, and has a test length of (8n2 ? 2n) + 4n = 8n2 + 2n. ?1 (mn?1 fm (w0 : ?) ; min=0 j =i+1

M0

?1 (mn?1 min=0 j =i+1

(r0j : r0i ; w1j : w1i ; w0j : w0i )) ; m (r0 : ?; w1 : w1; w0 : w0) ;

M1

M2

(r0j : r0i ; n : w1i ; w1j : w0i ; w0j : w1i ; n : w0i )) ; m (r0 : ?; w1 : ?) ;

?1 (mi?1 min=0 j =0

M3

M4

(r1j : r1i ; w0j : w0i ; w1j : w1i )) ; m (r1 : ?; w0 : w0; w1 : w1) ;

?1 (mi?1 min=0 j =0

M5

M6

(r1j : r1i ; n : w0i ; w0j : w1i ; w1j : w0i ; n : w1i )) ; m (r1 : ?)g

M7

M8

Figure 4.11: March 2PF3+: march test for 2PF3 faults and w1PF2&w1PF2 subclass


69

4.3.4 Test for all 2PFs

All introduced tests for 2PFs can be merged into a single march test, which detects all 2PF1s, all 2PF2s, and all 2PF3s. Figure 4.12 shows March 2PF which detects all these faults, and which has a test length of 16n2 ? 3n. Condition 2PF1 is satis ed by M0 and M6 . Condition 2PF2.1 is satis ed by M1 , M3 , M5 , and M7 . M1 contains the second march elements of Case A and B, M3 contains the second march elements of Case D and C, M5 contains the rst march elements of Case B and A, and M7 contains the rst march elements of Case C and D. Condition 2PF2.2 is also satis ed by M1 , M3 , M5 , and M7 . M1 contains the second march elements of Case A and D, M3 contains the second march elements of Case C and B, M5 contains the rst march elements of Case A and D, and M7 contains the rst march elements of Case C and B. Condition 2PF2.3 is satis ed by M2 , M3 , M6 , and M7 . M2 and M6 contain the rst march elements of Case A and B, while M3 and M7 contain the second march elements of the two same cases. Condition 2PF3 is satis ed by M1 , M2 , M3 , M4 , M5 , M6 , M7 , and M8 ; note that these march elements are the extended versions of the march elements of March 2PF3. fm (w0 : ?; r 0 : r 0; r 0 : r 0);

?1 (mn?1 min=0 j =i+1

M0

(r0j : r0i ; w1j : w1i ; w0j : r1i ; w1j : r1i ; n : r1i ; w0j : w0i ; n : r0i ));

M1

m (r 0 : ?; w1 : w1; w0 : w0)

?1 (mn?1 min=0 j =i+1

M2

;

(r0j : r0i ; n : w1i ; w1j : w0i ; w0j : r0i ; w1j : r0i ; n : r0i ; w0j : w1i ; n : r1i ; n : w0i )) ;

M3

m (r 0 : ?; w1 : ?)

;

M4 n ? 1 i ? 1 mi=0 (mj =0 (r 1j : r 1i ; w0j : w0i ; n : r 0i ; w1j : w1i ; w0j : r 1i ; w1j : r 1i ; n : r 1i )); M5 m (r 1 : r 1; r 1 : r 1; w0 : w0; w1 : w1) ; M6 n ? 1 i ? 1 mi=0 (mj =0 (r 1j : r 1i ; n : w0i ; w0j : w1i ; n : r 1i ; w1j : w0i ; w0j : r 0i ; w1j : r 0i ; n : r 0i ; n : w1i )) ; M7 m (r 1 : ?)g M8 Figure 4.12: March 2PF: march test for all 2PF3s, 2PF2s, and 2PF1s


70

4.3.5 Classi cation of 2PF tests

The proposed functional tests for 2P memories can be classi ed, based on the required test time, into two classes: Linear tests: these are tests which have a test time of order O (n); i.e., linear with the size of the memory. They consist of March 2PF1 and March 2PF2.2. Exponential tests: these are tests which have a test time of order O (np ); i.e., exponentially proportional with the number of ports. They consist of March 2PF2.1 (i.e., March 2PF2.1.1 merged with March 2PF2.1.2) and March 2PF3. In the following, the two linear tests will be merged into single test which will be called March l2PF. The same will be done for the two exponential tests. This will be referred as March e2PF.

March l2PF March l2PF is shown in Figure 4.13. It results from merging March 2PF1 and March 2PF2.2; i.e., it satis es Condition 2PF1 and Condition 2PF2.3 of Section 4.2.1, respectively, Section 4.2.2.

Condition 2PF1 is satis ed by M1 and M3 ; M1 contains the rst march element of the condition, while M3 contains the second march element of the condition. Condition 2PF2.3 is satis ed by M1 , M2 , M3 , and M4 . M1 and M2 contain the two march elements of Case A; while M3 and M4 contain the two march elements of Case B.

Note that March l2PF has a test length of 12n. fm (w0 : ?) ; m (r 0 : r 0; r 0 : r 0; w1 : w1; w0 : w0); m (r 0 : ?; w1 : ?);

M0

M1

m (r 1 : r 1; r 1 : r 1; w0 : w0; w1 : w1); m (r 1 : ?)g

M3

M2

M4

Figure 4.13: March l2PF: the merged test of March 2PF1 and March 2PF2.2

March e2PF March e2PF is shown in Figure 4.14; it results from merging March 2PF2.1 and March 2PF3. It consists of:

M0 : m (w0 : ?)

This is the same M0 of March 2PF3 as well as of March 2PF2.1. ?1 (mn?1 (r0j : r0i ; w1j : w1i ; w0j : r1i ; w1j : r1i ; n : r1i ; w0j : w0i ; n : r0i )) M1 : min=0 j =i+1 M1 results from merging M1 of March 2PF3 with M2 of March 2PF2.1.


71

M2 : m (r0 : ?)

This march element is the same as M2 of March 2PF3. ?1 (mn?1 (r0j : r0i ; n : w1i ; w1j : w0i ; w0j : r0i ; w1j : r0i ; n : r0i ; w0j : w1i ; n : M3 : min=0 j =i+1 r1i ; n : w0i )) This results from merging M3 of March 2PF3 with M4 of March 2PF2.1. M4 : m (r0 : ?; w1 : ?) This march element is the same as M4 of March 2PF3. ?1 (mi?1 (r1j : r1i ; w0j : w0i ; n : r0i ; w1j : w1i ; w0j : r1i ; w1j : r1i ; n : r1i )); M5 : min=0 j =0 This results from merging M5 of March 2PF3 with M1 of March 2PF2.1. M6 : m (r1 : ?) This march element is the same as M6 of March 2PF3. ?1 (mi?1 (r1j : r1i ; n : w0i ; w0j : w1i ; n : r1i ; w1j : w0i ; w0j : r0i ; w1j : r0i ; n : M7 : min=0 i=0 r0i ; n : w1i )) This results from merging the M7 of March 2PF3 with M3 of March 2PF2.1. M8 : m (r1 : ?)g This march element is same as M8 of March 2PF3.

Note that the test length of March e2PF is: n + n(7 n?2 1 ) + n + n(9 n?2 1 ) + 2n + n(7 n?2 1 ) + n + n(9 n?2 1 ) + n = 16n2 ? 10n fm (w0 : ?);

M0 : r0i ; w1j : w1i ; w0j : r1i ; w1j : r1i ; n : r1i ; w0j : w0i ; n : r0i )); m (r0 : ?) ; M1 M2 n ? 1 n ? 1 mi=0 (mj =i+1 (r 0j : r 0i ; n : w1i ; w1j : w0i ; w0j : r 0i ; w1j : r 0i ; n : r 0i ; w0j : w1i ; n : r 1i ; n : w0i )) ; M3 n ? 1 i ? 1 m (r 0 : ?; w1 : ?) ; mi=0 (mj =0 (r 1j : r 1i ; w0j : w0i ; n : r 0i ; w1j : w1i ; w0j : r 1i ; w1j : r 1i ; n : r 1i )); M4 M5 m (r 1 : ?) ; M6 n ? 1 i ? 1 mi=0 (mj =0 (r 1j : r 1i ; n : w0i ; w0j : w1i ; n : r 1i ; w1j : w0i ; w0j : r 0i ; w1j : r 0i ; n : r 0i ; n : w1i )) ; M7 m (r 1 : ?)g M8 ?1 (mn?1 (r0j min=0 j =i+1

Figure 4.14: March e2PF: the merged test of March 2PF3 and March 2PF2.1


72

The relationship between tests for 2PF faults is shown in Figure 4.15. March 2PF 2:1 detects all faults detected by March 2PF 2:1:1 as well as by March 2PF 2:1:2; March 2PF 2:1+ detects the same faults as March 2PF 2:1, and in addition, it detects the faults of 2PF 1 fault class. March 2PF3+ detects all faults detected by March 2PF2.2 as well as by March 2PF3. March l2PF detects all faults detected by March 2PF 1 as well as by March 2PF 2:2; and March e2PF detects all faults detected by March 2PF 3 as well as by March 2PF 2:1; while March 2PF detect all 2PF faults; i.e., 2PF1s, 2PF2s, and 2PF3s.

March 2PF2.1+ March 2PF2.1.1

March 2PF1

March 2PF2.1.2 March 2PF2.1 March l2PF

March e2PF

March 2PF1

March 2PF2.2 March 2PF3+ March 2PF

Figure 4.15: Relationships between developed tests for 2PFs

4.4 Tests for AF2s As mentioned in Section 3.2.3, the AFs in 2P memories are divided into AF 1s and AF 2s. Moreover, AF2s consist of faults that are subset of AF1s and faults which require new tests. Therefore the test procedure can be divided into two parts: 1. Test(s) to detect AF 1s 2. Test(s) to detect AF 2s. For the detection of AF 1s (and AF2s which are a subset of AF1s) a march test like MATS +, March X , etc (see [van de Goor, 1991]) can be used. The test has to be applied via each port of the 2P memory separately. It should be noted that in order to detect AF 2s which are a subset of AF1s, that when the test is applied via the one port, the other port has to be not active (i.e., no row is selected via this port); see Table 3.7. For the detection of AF 2s (see Table 4.1) in row decoders, the test is given in Figure 4.16 in a C + + pseudo code (denoted as Test AF 2s), and is rewritten in a compact march notation in Figure 4.17 (denoted as March (rw ? rw)AF 2). To detect the same faults in the column decoders, a similar test has to be applied to the columns (Note: shorts between row- and column decoders are not realistic, considering the layout positions of these decoders). In Figure 4.16, the rst loop initializes the


73

Table 4.1: The reduced set of AF2s Fault If A1X : AY2 then Cx1 : Cy2 If A1X : A2Z , Z 6= Y; then Cx1 : Cz2 : Cy2 If A1X : A2Y then Cx2 : C2

Name Fault E Fault F Fault G

memory cells of two distinct columns c1 and c2 to 0. The second double loop generates all address pairs required in order to detect the faults; the operations \w1r1 ;c1 : w1r2 ;c2 ' ' sensitize the faults, while the operations \r0r1 ;c1 : r0r2 ;c2 ", \r1r1 ;c1 : n", \n : r1r2 ;c2 " and the operation \r1r;c1 : ?" (of the third loop) detect them. The two single write operations are added to the second loop to make the content of the cells equal to 0 after each inner loop; this is the expected value of the simultaneous read operations (i.e.,\r0r1 ;c1 : r0r2 ;c2 "). Select two columns c1 and c2 ; c1 6= c2 ; for all r //r 2 f0; 1; :::; R ? 1g f w0r;c1 : n; // Initialize c1 to 0 n : w0r;c2 ; // Initialize c2 to 0 g

for(r1 = 0; r1 < R; r1 + +) f for(r2 = 0; r2 < R; r2 + +) f r 0r1 ;c1 : r 0r2 ;c2 ; w1r1 ;c1 : w1r2 ;c2 ; r1r1 ;c1 : n; n : r1r2;c2 ; w0r1 ;c1 : n; n : w0r2 ;c2 ; g

g

for all r f r 0r;c1 : ?; g

Figure 4.16: Test for AF2s in 2P memories The fault coverage of the test of Figure 4.16 is analyzed below. First, consider Fault E; i.e., \If A1X : AY2 then Cx1 : Cy2". Depending on the value of Y (Y 2 f0; 1; :::; R ? 1g) two cases can be distinguished: 1. Y = 0 (i.e., Y 6= 0 ). In this case the fault will be sensitized by the operation \w1r1 ;c1 : w1r2 ;c2 " when r1 = X and r2 = 0(= Y ). In the presence of the fault, 1 will not only be written into the cells Cx;c1 and Cy;c2 , but also into the cell Cy;c2 (due to Fault E) which content was 0. The fault will be detected by the operation \r0x;c1 : r0y;c2 ".

CHAPTER 4. TESTS FOR TWO-PORT MEMORIES ?1 fmrR=0

(w0r;c1 : n; n : w0r;c2 );

1 (*R?1 *rR1?=0 r2 =0

?1 mrR=0

74

M0

(r0r1 ;c1 : r0r2 ;c2 ; w1r1 ;c1 : w1r2 ;c2 ; r1r1 ;c1 : n; n : r1r2 ;c2 ; w0r1 ;c1 : n; n : w0r2 ;c2 )); M1

(r0r;c1 : ?)g

M2

Figure 4.17: March AF2 for AF2 faults in 2P memories 2. Y 6= 0 (i.e., Y = 0). In this case the fault will be sensitized by the operation \w1r1 ;c1 : w1r2 ;c2 " when r1 = X and r2 6= 0 (e.g., r2 = 1). In the presence of the fault, 1 will not only be written into the cells Cx;c1 and Cy;c2 , but also into the cell Cy;c2 which content was 0. The fault will be detected by the operation \r0x+1;c1 : r0y;c2 "(i.e., in the next iteration of the inner loop; this will be for r1 = X + 1) The second form of Fault E; i.e., \If AX1 : A2Y then Cx1 : Cy2 " will be sensitized by the operation \w1r1 ;c1 : w1r2 ;c2 ". We distinguish also two cases:

X = 0 (i.e., X 6= 0). In this case the fault will be sensitized when r1 = 0(= X ) and r2 = Y . Due to the fault, 1 will be also written into cell Cx;c1 which content was 0. The fault will be detected by the operation \r0r1 ;c1 : r0r2 ;c2 " when r1 = X . X 6= 0. In this case the fault will be sensitized when r1 6= 0 (e.g., r1 = 1) and r2 = Y . Due to the fault, 1 will be also written into cell Cx;c1 which content was 0. The fault will be detected by the read operation of the third loop.

Second, consider the Fault F; i.e., \If A1X : A2Z , Z 6= Y; then Cx1 : Cz2 : Cy2 ". Since the second loop in the test generates all pairs of rows, the fault will be sensitized by the operation \w1r1 ;c1 : w1r2 ;c2 " when r1 = X and r2 = Z . In the presence of the fault, 1 will not only be written into the cells Cx;c1 and Cz;c2 , but also into the cell Cy;c2 which content was 0; whereby Y 2 f0; 1; :::; R ? 1g, and Y 6= Z . The fault will be detected by the operation \r0x;c1 : r0y;c2 " if Y > Z (i.e., in the same inner loop in which the fault is sensitized), and by the operation \r0x+1;c1 : r0y;c2 " if Y < Z (i.e., in the next iteration of the inner loop; this will be for r1 = X +1). The second form of Fault F; i.e., \If A1W : A2Y , W 6= X; then Cx1 : Cw1 : Cy2 " will be sensitized by the operation \w1r1 ;c1 : w1r2 ;c2 " when r1 = W and r2 = Y ; and detected by the operation \r0x;c1 : r00;c2 " if X > W and by the march element of the third loop if X < W . Finally, consider Fault G; i.e., \If A1X : A2Y then Cx1 : C2 " (or the second form of Fault G: \If A1X : A2Y then C1 : Cy2 "). This fault will be sensitized by the operation \w1r1 ;c1 : w1r2 ;c2 " when r1 = X and r2 = Y , and detected by the operation \r1r1 ;c1 : n" or \n : r1r2 ;c2 ". As can be seen from the Figure 4.16, the number of operations required to perform the test is 3R + 6R2 ; and therefore the time complexity of the test is O(R2 ) whereby R is the number of rows in the memory cell array. If we assume a two dimensional memory cell array with size n, p then the test length will be 3 n +6n and therefore the time complexity of the test will be O(n).


75

4.5 Summary of two-port memory tests Table 4.2 summarizes the tests introduced in this section. It shows their required number of operations (i.e., test length), including initialization ; together with their fault coverage; see Figure 3.21 and Figure 3.22. Table 4.2: Summary of two-port memory tests

Test Test length Fault coverage March 2PF 1 6n All 2PF 1s : wRDF &wRDFs March 2PF 2:1 14n2 ? 13n 2PF 2s : wCFid &wTFs, wCFds &wTFs, wCFid &wRDFs and wCFid &wRDFs. March 2PF 2:2 10n 2PF 2s : wCFid &wCFid , wCFds &wCFds March 2PF 3 8n2 ? 2n All 2PF 3s : wCFid &wCFid , wCFds &wCFds wCFid &wCFds 2 March 2PF 16n ? 3n All 2PF 3s, all 2PF 2s, all 2PF 1s. March l2PF 12n All 2PF 1s and 2PF 2s : wCFid &wCFid , wCFds &wCFds March e2PF 16n2 ? 10n All 2PF 3s, 2PF 2s : wCFid &wTFs, wCFds &wTFs, wCFid &wRDFs and wCFid &wRDFs. p March AF 2 3 n + 6n All AF 2s : faults E, F, and G.

Chapter 5

Fault and test simpli cation In this chapter the fault models and their tests introduced in Chapter 3 and Chapter 4 respectively for two-port memories will be simpli ed. First, the simpli cation will be based on the port mix. Thereafter, the simpli cation will be based on the topology.

5.1 Classi cation of 2P memories based on the port mix 2P memories come in dierent forms depending on the type of ports they consist of. Each of the two ports of a 2P memory may have the capability to be a read-only port (Pro), a write-only port (Pro), or a read-write port (Prw). Therefore, four types of 2P memories can be distinguished based on the port mix:

2P 2P 2P 2P

memories with Prw = 2 (noted as (rw ? rw)2P memories). memories with Prw = 1 and Pwo = 1 (noted as (rw ? wo)2P memories). memories with Prw = 1 and Pro = 1 (noted as (rw ? ro)2P memories). memories with Pwo = 1 and Pro = 1 (noted as (wo ? ro)2P memories).

5.2 Simpli cation of 2PFs based on the port mix The functional fault models, 2PFs, introduced in Chapter 3 are valid for (rw ? rw)2P memories. The 2PFs concern faults in the memory cell array. They consist of 1P -MCAFs, and MCAFs based on weak faults (2PFs); see Figure 3.21. 1P -MCAFs can appear in all types of the 2P memories; i.e., they are independent of the port mix. However, the 2PFs are port mix dependent, because they require two simultaneous operations in order to be sensitized. For example, a fault type based on two simultaneous write operations can not appear in (wo ? ro)2P memories since the latter allows only for a single write operation at time. The (rw ? rw)2P memories are memories which allow for single operations (read or write) as well as for two simultaneous operations (read and/or write); the (rw ? wo)2P memories are memories which allow for a single operation and two simultaneous write operations; the (rw ? ro)2P 76

CHAPTER 5. FAULT AND TEST SIMPLIFICATION

77

memories are memories which allow for a single operation and two simultaneous read operations; while the (ro ? wo)2P memories are memories which allow for a single operation and a simultaneous read and write operations. In the following, the 2PFs for (rw ? wo)2P memories, (rw ? ro)2P memories, and (ro ? wo)2P memories will be derived based on (rw ? rw)2P memory faults developed in Chapter 3. The 2PFs for (rw ? rw)2P memories are divided into ve fault classes: the fault class involving a single cell (2PF 1), two cells (2PF 2), three cells (2PF 3), k cells (2PFk), and k + 1 cells (2PF (k + 1)). Below, the possibility to simplify these fault classes will be discussed; the result is shown in Figure 5.1.

2PF1 fault class

The 2PF 1 fault class consists of only one fault type: wRDF &wRDF . This type requires two simultaneous read operations in order to be sensitized. Therefore, the fault class 2PF 1 is: not realistic for (rw ? wo)2P memories. realistic for (rw ? ro)2P memories. not realistic for (wo ? ro)2P memories.

2PF2 fault class

The 2PF 2 fault class is divided into two subclasses: w1PF 2a;v &w1PF 1v , and w1PF 2a;v &w1PF 2a;v . The rst subclass involves a weak single cell fault and a wCF ; while the second subclass involves two wCFs with the same aggressor cell and the same victim cell.

The fault subclass w1PF2&w1PF1

This subclass consists of four fault types for (rw ? rw)2P memories; two are wCFi &wTF , and two are wCFi &wRDF , whereby wCFi 2 fwCFid ; wCFds g. The wCFi &wTF fault requires two simultaneous write operations in order to be sensitized; while the wCFi &wRDF fault is sensitized by writing a cell and reading another one at the same time. Therefore:

{ both wCFi &wTF and wCFi&wRDF are realistic for (rw ? wo)2P memories. { only wCFi&wRDF is realistic for (rw ? ro)2P and (wo ? ro)2P memories.

The fault subclass w1PF2&w1PF2 This subclass consists of two fault types for (rw ? rw)2P memories, namely wCFid &wCFid and wCFds &wCFds . The two faults are sensitizable by writing a single cell via the two ports of the memory simultaneously. Therefore, this subclass:

{ is realistic for (rw ? wo)2P memories. { is not realistic for (rw ? ro)2P and (wo ? ro)2P memories.


78

2PF3 fault class

The 2PF 3 fault class, which is based on a combination of two wCFs, consists of three fault types: wCFid &wCFid , wCFid &wCFds , and wCFds &wCFds . For multi-port SRAMs, All three fault types involve two simultaneous write operations. Hence, this fault class is:

realistic for (rw ? wo)2P memories. not realistic for (rw ? ro)2P and (wo ? ro)2P memories.

2PFk fault class

This is class is divided into two fault subclasses: 2P -NPSF and wNPSF &w1PF 1. The rst subclass is based on a combination of two wNPSFs with the same base cell; while the second subclass is based on a combination of a wNPSF with a weak single cell fault.

The fault subclass 2P-NPSF 2P -NPSF fault subclass consists in total of six fault types, namely wNPSFi &wNPSFj , whereby fwNPSFi ; wNPSFj g fwANPSF; wPNPSF; wDNPSF g. All these fault types require two simultaneous write operations in order to be sensitized in multi-port SRAMs (note that the wDNPSF for SRAMs assumes partially disturb only by write operations). Therefore, the 2P -NPSF fault subclass is:

{ realistic for (rw ? wo)2P memories. { not realistic for (rw ? ro)2P and (wo ? ro)2P memories.

The fault subclass wNPSF&1PF1 This subclass consists in total of ve fault types: three are wNPSFi &wTF types and two are wNPSFj &wRDF types; whereby wNPSFi 2 fwANPSF; wPNPSF; wDNPSF g and wNPSFj 2 fwANPSF; wDNPSF g. The wNPSFi &wTF faults occur in memories which allow for two simultaneous write operations; while the wNPSFj &wRDF faults occur in memories which allow for read and write operation to be performed simultaneously. Hence,

{ both wNPSFi &wTF and wNPSFj &wRDF are realistic for (rw ? wo)2P memories. { only wNPSFj &wRDF is realistic for (rw ? ro)2P and (wo ? ro)2P memories. 2PF(k+1) fault class

The 2PF (k + 1) fault class is based on a combination of wCFs and wNPSFs; it has six fault types: wNPSFi &wCFj , whereby wNPSFi 2 fwANPSF; wPNPSF; wDNPSF g and wCFj 2 fwCFid ; wCFds g. All these faults are sensitized by two simultaneously write operations; and therefore this fault class is:

realistic for (rw ? wo)2P memories. not realistic for (rw ? ro)2P and (wo ? ro)2P memories.


79

All realistic 2PFs for the dierent 2P memories types are summarized in Figure 5.1. Note that 2PFs for (wo ? ro)2P memory are faults which occur in (rw ? wo)2P memory as well as in (rw ? ro)2P memory. 2PFs for (rw-wo)memory

2PF1s

2PF3s

2PF2s

wCF &wTF

No faults

wCF &wCF id

id

id

wCF &wCF

wCF &wTF

ds

ds

ds

wCF &wCF id

id

wCF &wCF ds

ds

wCF &wCF

wCFid &wRDF

ds

2PF(k+1) s

2PF k s

ds

wANPSF&wANPSF

wANPSF&wTF

wANPSF&wCF id

wANPSF&wPNPSF

wPNPSF&wTF

wANPSF&wCF ds

wDNPSF&wTF

wPNPSF&wCF id

wANPSF&wDNPSF wPNPSF&wPNPSF wPNPSF&wDNPSF

wCFds &wRDF

wDNPSF&wDNPSF

wANPSF&wRDF wDNPSF&wRDF

wPNPSF&wCFds wDNPSF&wCF id wDNPSF&wCF ds

(a} 2PFs for (rw-wo)2P memories

2PFs for (rw-ro)memory

2PF1s

wRDF&wRDF

2PF2s

wCF &wRDF id

2PF3s

No faults

2PF k s

2PF(k+1) s

wANPSF&wRDF

No faults

wANPSF&wRDF

wCF &wRDF ds

(b) 2PFs for (rw-ro)2P memories

2PFs for (wo-ro)memory

2PF1s

No faults

2PF2s

wCF &wRDF id

wCF &wRDF ds

2PF3s

No faults

2PF k s

2PF(k+1) s

wANPSF&wRDF

No faults

wANPSF&wRDF (c) 2PFs for (wo-ro)2P memories

Figure 5.1: Overview of all realistic 2PFs for dierent 2P memory types

5.3 Simpli cation of AF2s based on the port mix AFs concern faults in address decoder. They consist of AF s involving a single port (AF 1) and AF s involving two ports (AF 2); see Figure 3.22. AF 1s for 2P memories are the same as those for SP memories, while AF2s occur only in 2P memories and are based on interference between

the two ports. The two fault classes, AF1 and AF2, occur in all types of 2P memories; this is because each 2P memory contains two duplicated sets of address decoders, irrespective the type of ports. However, the port restriction (in the form of ro or wo) impacts the possible tests;


80

e.g., two simultaneous write operations can not be applied to (rw ? ro)2P memories, nor to (wo ? ro)2P memories. This will be discussed in Section 5.5.

5.4 Impact of port restrictions on the tests for 2PFs The tests introduced in Chapter 4 for 2PFs can be simpli ed based on the fault simpli cation of Section 5.2 and Section 5.3. In the following, march tests will be derived for realistic faults in each of the 2P memory types.

5.4.1 Test for (rw-wo)2P memories

The 2PFs for (rw ? wo)2P memories are the same as those of (rw ? rw)2P memories; except that the 2PF 1s (i.e., wRDF &wRDF ) can not occur. March 2PF of Figure 4.13, which detect all 2PF 1s, 2PF 2s, and 2PF 3s can be modi ed in such way that it will detect the same faults except the 2PF 1s. The result of modi cation is shown in Figure 5.2. This test, referred as March (rw ? wo)2PF , is obtained from March 2PF by removing the sensitizing and detecting operations of 2PF 1s; i.e., the operations \r0 : r0; r0 : r0" of the rst march element (M0 ), and the operations \r1 : r1" of M6 . Note that the other simultaneous read operations \r1 : r1" can not be removed from M6 since they have to detect the 2PF 3 sensitized by M5 . However, they have to be applied sequentially; i.e., \r1 : n; n : r11 " (1 denotes explicitly Prw). This is because (rw ? wo)2P memories do not allow for simultaneous read operations. Note that March (rw ? wo)2PF has a test length of 18n2 ? 8n fm (w0 : ?);

M0 : w1i ; w0j : r1i ; w1j : r1i ; n : r1i ; w0j : w0i ; n : r0i )); M1 m (r 0 : ?; w1 : w1; w0 : w0) ; M2 n ? 1 n ? 1 1 mi=0 (mj =i+1 (r 0j : n; n : r 0i ; n : w1i ; w1j : w0i ; w0j : r 0i ; w1j : r 0i ; n : r 0i ; w0j : w1i ; n : r 1i ; n : w0i )) ; M3 m (r 0 : ?; w1 : ?) ; M4 ?1 (mi?1 (r1j : n; n : r11 ; w0j : w0i ; n : r0i ; w1j : w1i ; w0j : r1i ; w1j : r1i ; n : r1i )); min=0 i j =0 M5 m (r 1 : r 1; w0 : w0; w1 : w1) ; M6 ?1 (mi?1 (r1j : n; n : r11 ; n : w0i ; w0j : w1i ; n : r1i ; w1j : w0i ; w0j : r0i ; w1j : r0i ; n : r0i ; n : w1i )) ; min=0 i i=0 M7 m (r 1 : ?)g M8 ?1 (mn?1 (r0j min=0 j =i+1

: n; n : r01i ; w1j

Figure 5.2: March (rw-wo)2PF: march test for 2PFs of (rw-wo)2P memory


81

5.4.2 Test for (rw-ro)2P memories

2PFs for this memory type consist only of three fault types: wRDF &wRDF , wCFid &wRDF , and wCFds &wRDF ; see Figure 5.1. To detect these faults, March 2PF2.1.2 of Figure 4.6 (which detects wCFid &wRDF , and wCFds F &wRDF ) can be extended such that it will cover wRDF &wRDF faults. This can be done by adding the operations \r0 : r0; r0 : r0" to M0 and the operations \r1 : r1; r1 : r1" to M3 . The resulting march test, referred as March (rw-ro)2PF, is shown in Figure 5.3; it has a test length of: (6n2 ? 4n) + 4n = 6n2 . ?1 (mv?1 fm (w0 : ?; r 0 : r 0; r 0 : r 0) ; mvn=0 v=0

(w1a : r0v ; w0a : r0v ; n : r0v )); M0 M1 n ? 1 n ? 1 mv=0 (ma=v+1 (w1a : r 0v ; w0a : r 0v ; n : r 0v )) ; m (w1 : ?; r 1 : r 1; r 1 : r 1) M2 M3 n ? 1 v ? 1 ma=0 (ma=0 (w0a : r 1v ; w1a : r 1v ; n : r 1v ) ; M4 ?1 (mn?1 (w0a : r1v ; w1a : r1v ; n : r1v ))g mvn=0 a=v+1 M5 Figure 5.3: March (rw-ro)2PF: march test for 2PFs of (rw-ro)2P memory

5.4.3 Test for (wo-ro)2P memories

The 2PFs for this 2P memory type consist only of two fault types, namely wCFid &wRDF and wCFds &wRDF ; see Figure 5.1. Such faults are detectable with March 2PF2.1.2 of Figure 4.6. This test, which has a test length of 6n2 ? 4n, is again given in Figure 5.4, and it is referred as March (wo ? ro)2PF . ?1 (mv?1 fm (w0 : ?) ; mvn=0 a=0

M0

?1 (mn?1 mvn=0 a=v+1

(w1a : r0v ; w0a : r0v ; n : r0v ));

M1

(w1a : r0v ; w0a : r0v ; n : r0v )) ; m (w1 : ?)

M2

?1 (mv?1 (w0a mvn=0 a=0 ?1 (mn?1 mvn=0 a=v+1

: r 1v ; w 1 a : r 1 v ; n : r 1 v ) ;

M3

M4 (w0a : r1v ; w1a : r1v ; n : r1v ))g M5

Figure 5.4: March (wo ? ro)2PF: march test for 2PFs of (wo-ro)2P memory

5.5 Impact of port restrictions on the tests for AF2s The test, March (rw ? rw)AF 2, given in Section 3.2 applies to (rw ? rw)2P memories only. In this section tests for detecting AF 2s in each of restricted 2P memory types will be derived. Remember that all AFs discussed in Section 3.2.3 occur in all types of 2P memories.


82

5.5.1 Test for AF2s in (rw-wo)2P memories

The (rw ? wo)2P memories allow for two simultaneous write operations, and only a single read operation. The test detecting all AF 2s in such memories is given in Figure 5.5, and is referred as March (rw ? wo)AF 2. It is the same as that of Figure 4.17, however the simultaneous read operations of Figure 6 have to be applied sequentially; (i.e., \r02r1 ;c1 : n; n : r0r2 ;c2 " [Note: port 2 (P2)= Prw]). March (rw ? wo)AF 2 has the same fault coverage as March (rw ? rw)AF 2; see Section 3.2. ?1 fmrR=0

(w0r;c1 : n , n : w0r;c2 );

1 (*R?1 *rR1?=0 r2 =0

?1 mrR=0

M0

(r02r1 ;c1 : n , n : r0r2 ;c2 , w1r1 ;c1 : w1r2 ;c2 , r12r1 ;c1 : n , n : r1r2 ;c2 , w0r1 ;c1 : n , n : w0r2 ;c2 )); M1

(r0r;c1 : ?)g

M2

Figure 5.5: March (rw-wo)AF2 for AF2s in (rw-wo)2P memories

5.5.2 Test for AF2s in (rw-ro)2P memories

The (rw ? ro)2P memories allow for simultaneous read operations and only for a single write operation. Therefore the sensitizing operations used in March (rw ? rw)AF 2 and March (rw ? wo)AF 2 (i.e., \w1r1 ;c1 : w1r2 ;c2 ") can not be used for such memories. The march test for AF 2s in (rw ? ro)2P memories is given in Figure 5.6. By assuming that P 1 = Pro and P 2 = Prw, the test of Figure 5.6 guarantees the detection of one form of Fault E (i.e., \If A1X : AY2 then Cx1 : Cy2 " ), one form of Fault F (i.e., \If A1X : A2Z , Z 6= Y , then Cx1 : Cz2 : Cy2 ") and one form of Fault G (i.e., \If A1X : A2Y then Cx1 : C2 "). In addition, the test can detect the second form of Fault E (i.e., \If AX1 : A2Y then Cx1 : Cy2 "), the second form of Fault F (i.e., \If A1W : A2Y , W 6= X; then Cx1 : Cw1 : Cy2") and the second form of Fault G (i.e.,\If A1X : A2Y then C1 : Cy2"); see below. ?1 fmrR=0

(w12r;c1 : n , n : w0r;c2 );

?1 (*R?1 *rR=0 r2 =0

(r1r1 ;c1 : n , n : r0r2 ;c2 , w02r1 ;c1 : n , r0r1 ;c1 : w1r2 ;c2 , n : r1r2 ;c2 , w12r1 ;c1 : r11r2 ;c2 , n : w0r2 ;c2 ))g

Figure 5.6: March (rw-ro)AF2 for AF2s in (rw-wo)2P memories First, consider the rst form of Fault E; i.e., \If A1X : AY2 then Cx1 : Cy2 ". Depending on the value of Y we can distinguish two cases: 1. Y 6= 0. In this case the fault will be sensitized by the operation \r0r1 ;c1 : w1r2 ;c2 " when r1 = X and r1 = 0. In the presence of the fault, the cell Cy;c2 will be written with 1 via Prw. The fault will be detected by the operation \n : r0y;c2 ".


83

2. Y = 0. In this case the fault will be sensitized by the operation \r0r1 ;c1 : w1r2 ;c2 " when r1 = X and r1 6= 0 (e.g., =1). As consequence of the fault, 1 will also written in cell Cy;c2 which content was 0. The fault will be detected by the operation \n : r0y;c2 ". Second, consider the rst form of Fault F; i.e., \If A1X : A2Z , Z 6= Y; then Cx1 : Cz2 : Cy2 ". The fault will be sensitized by the operation \r0r1 ;c1 : w1r2 ;c2 " when r1 = X and r2 = Z . In the presence of the fault, 1 will not only be written into cell Cr2 ;c2 but also in the cell Cy;c2 (via port Prw) which content was 0. The fault will be detected by the operation \n : r0y;c2 ". Third, consider the rst form of fault G; i.e., \If A1X : A2Y then Cx1 : C2 ". This fault will be sensitized by the operations \r0r1 ;c1 : w1r2 ;c2 " when r1 = X and r2 = Y , and detected by the operations \n : r1y;c2 ". Consider now the second form of Fault E (i.e., \If AX1 : A2Y then Cx1 : Cy2 "), the second form of Fault F (i.e., \If A1W : A2Y , W 6= X; then Cx1 : Cw1 : Cy2 "), and the second form of Fault G (i.e., \If A1X : A2Y then C1 : Cy2 "). These faults can not be sensitized using write operations via P1 since P1= Pro. That means that the read operation is the only possibility to use. Assume the presence of the second form of Fault E, then applying the operation \r0r1 ;c1 : w1r2 ;c2 " (when r1 6= X and r2 = Y ) will have as consequence that P 1 will read two cells (i.e., Cr1 ;c1 and Cx;c1 ), which have dierent data values, simultaneously while P2 will correctly write into cell Cy;c2 (see Figure 7). A similar explanation can given by applying the operation \w12r1 ;c1 : r11r2 ;c2 ". Depending on the technology of the sense ampli er, the value can be:

A 0 or a 1 (Stuck at fault behavior): in this case the detection of the fault will be guaranteed by the operation \r0r1 ;c1 : w1r2 ;c2 " if it appears as SA1 and by the operation \w12r1 ;c1 : r11r2 ;c2 " if it appears as SA0.

The last read value: in this case the detection of the fault will be guaranteed by the operation \r0r1 ;c1 : w1r2 ;c2 " since the last read value was 1 (by the operation \r1r1;c1 : n"); see Figure 8.

The OR logic function of the read values. The detection of the fault is guaranteed by the operation \r0r1 ;c1 : w1r2 ;c2 " since all cells of column c1 contain 1, and only the cell Cr1 ;c1 contains 0; that means that the content of cell Cr1 ;c1 is 0 and the content of Cx;c1 is 1.

The AND logic function of the read values. The detection of the fault is guaranteed by the operation \w12r1 ;c1 : r11r2 ;c2 " since all cells of column c2 contain 0, and only the cell Cr2 ;c2 contains 1; that means that the content of cell Cr2 ;c2 is 1 and the content of Cx;c2 is 0.

Random: in this case the detection of the fault can not be guaranteed. However, applying the test multiple times can detect the fault probabilistically.

A similar explanation can be given for the detection of the second form of the Fault F and Fault G. However, the presence of second form of Fault G will has as consequence that a cell will not be accessed; and therefore the read value depends on the type of sense ampli er (see above).


84

5.5.3 Test for AF2s in (wo-ro)2P memories

The (wo ? ro)2P memories allow for only a single write operation, and/or a single read operation. The test detecting AF 2s in such memories is given in Figure 5.7; it is referred as March (wo ? ro)AF 2. Note that this test is the same as that of Figure 5.6, and therefore it has the same fault coverage as March (rw ? wo)AF 2; see Section 4.2. However, all read operations have to be done via P 1 = Pro, and all write operations via P 2 = Pwo. ?1 fmrR=0

(w12r;c1 : n , n : w0r;c2 );

?1 (*R?1 *rR=0 r2 =0

(r1r1 ;c1 : n , n : r01r2 ;c2 , w02r1 ;c1 : n , r0r1 ;c1 : w1r2 ;c2 , n : r11r2 ;c2 , w12r1 ;c1 : r11r2 ;c2 , n : w0r2 ;c2 ))g

Figure 5.7: March (wo-ro)AF2 for AF2s in (wo-ro)2P memories

5.6 Simpli cation of tests based on the topology The test complexity of the tests introduced in Chapter 4 for 2PFs was of order O(n2 ); that implies that the test time is exponentially proportional with the number of the ports. In spite of reducing the 2PFs and their tests based on the port mix in the previous section, the test time remains exponentially proportional with the number of the ports; i.e., O(np ). This is also the case for any functional test. That makes these tests less practical for larger multi-port memories. In order to allow for economically justi ed testing of such memories, it is necessary to simplify the fault models in such way that the test time will be linear, while the fault coverage remains high. The approach is to take the topology of the memory into account. The functional test with O(n2 ) allows for the cells involved in weak faults (that compose the 2PF fault) to be located anywhere in the memory. As coupling faults are due to leakage current and/or capacitive and/or resistive coupling, it is reasonable to restrict this in uence to cells in the same row or column, or in the physical adjacent rows and columns; see Figure 5.8. Moreover, this in uence can be further reduced to physical neighbor cells; this is because of the fact that if a fault in a v-cell is caused with two a-cells which have the same row or column or in adjacent rows or columns, then the same fault is caused with at least two adjacent cells of the v-cell. In the memory array shown in Figure 5.8, if a fault in cv is caused with the two a-cells ci and ct , then the same fault can be sensitized with the two a-cells cm and cn. That implies that the fault caused with ci and ct in cv can be detected by restricting the a-cells to the neighbors of cv (e.g., cells cm and cn ). This topological restriction will reduce the test complexity from O(n2 ) to O(n) without sacri cing the fault coverage. The march tests introduced in Chapter 4 for 2PFs are classi ed as linear and exponential tests. The linear tests are tests which detect faults of 2PF1 fault class and/or faults of the fault subclass wCF &wCF (of 2PF2 fault class). The exponential tests are tests which detect faults of the fault subclass wCF &w1PF 1 (of 2PF2 fault class) and faults of 2PF3 fault class, like


C

85

i

Coupling between bit lines

C

C

Cm

k

word lines

C

v

C

n

t

Bit lines

Figure 5.8: Reduction of a-cells space March 2PF2.1, March 2PF3, and March 2PF. In the rest of this section, we will simplify the exponential tests based on the topology approach.

5.6.1 Reduction of March 2PF2.1

This tests detects wCF &1PF 1 faults. To reduce its time complexity, we have to reduce the a-cells space (i.e., reduce the search space of the test). As mentioned above, it is reasonably to limit the a-cells space to the physical neighborhood of the v-cell. Assuming that the memory cell array is two-dimensional with n rows and m columns, a cell can be addressed by its row address and column address. Therefore, the cell cv can be addressed as cr;c, whereby r is the row address and c is the column address. Each cell cv = cr;c has at most eight neighbors (see Figure 5.9); since if r = 0, or r = n ? 1, or c = 0, or c = n ? 1, then the number of the neighborhoods will be at most ve. It is clear, that by using the topology, for every v-cell, the number of a-cells is at most eight; while this was n ? 1 for the O(n2 ) functional tests. Therefore, the test length of March 2PF2.1 will be less then (see Figure 4.7): n + n(6 28 ) + n(6 28 ) + n(8 28 ) + n(8 28 ) = 113n


C

86

C

0,0

0,m-1

C r-1,c-1

C r-1,c

C

r-1,c+1

C

C

C

C

C

C

r,c-1

r+1,c-1

r,c

r,c+1

r+1,c r+1,c+1

C

C n-1,m-1

n-1,0

Figure 5.9: Neighborhoods of the cell cv = cr;c

5.6.2 Reduction of March 2PF3

March 2PF2.3 detects wCF &wCF faults, whereby the two a-cells of the two wCF s are dierent. From Figure 5.9, we can see that by using the topological approach, the maximal row distance as well as the maximal column distance between any two aggressor cells is 2. Therefore, March 2PF3 has to select only couples (ci ; cj ) having this property. Figure 5.10 shows that for a given ci = cr;c, there are at most 24 couples which satis es this property. Note that for c = 0, or c = 1, or c = n ? 2, or c = n ? 1, the number of the couples is smaller. For reasons which are explained by composing Condition 2PF3 (Section 4.2.3), only 12 couples will be considered. It is clear from the above, that for a given ci , there are only 12 cj candidates which form a couple (ci ; cj ). This was n ? 1 for the O(n2 ) functional tests. The reduced test length of March 2PF2.3 is less then (see Figure 4.11): n + n(3 122 ) + n + n(5 122 ) + 2n + n(3 122 ) + n + n(5 122 )n + n = 102n.

5.6.3 Reduction of March 2PF

We have seen, that for a given cell cv = cr;c, the reduced March 2PF2.1 restricts the a-cells space to at most eight cells; and for a given cell ci = cr;c, March 2PF3 selects only 12 cells cj which form together with the cell ci the a-cells couples (ci ; cj ). March 2PF has to cover all these cells (i.e., the eight and 12 cells), since it detects the faults detected by March 2PF2.1 as well as by March 2PF3. From Figure 5.10 we can see that in the case that ci = cr;c is assumed to be a v-cell, then the 12 cells cover four of the neighborhood cells of ci (see also Figure 5.9). Hence, the total number of cells cj that March 2PF has to take into account for each cell ci is at most 16 cells. Therefore, test length of March 2PF will be less then (see Figure 4.13): 3n + n(7 162 ) + 3n + n(9 162 ) + 2n + n(7 162 ) + 4n + n(9 162 ) + n = 269n


87

C

C

0,0

0,m-1

C

r-2,c-2

C

r-1,c-2

C r-2,c-1

C r-1,c-1

C r-2,c

C r-1,c

C

r-2,c+1

C

r-1,c+1

C

r-2,c+2

C

r-1,c+2

C

C

Cr,c

C

C

C

C

C

C

C

r,c-2

r,c-1

r+1,c-2 r+1,c-1

C

r+2,c-2

C

r+2,c-1

r,c+1

r,c+2

r+1,c r+1,c+1 r+1,c+2

C

r+2,c

C

C

r+2,c+1 r+2,c+2

C

C

n-1,0

n-1,m-1

Figure 5.10: Couples (ci ; cj ) with a distance 2

5.7 Comparison of tests based on the complexity The time complexity of the functional testing for 2PFs in 2P memories is O(n2 ). The simpli cation of faults models based on the topology of the memory has reduced the complexity to O(n). Table 5.1 shows the comparison between the two versions of tests. The test length together with the duration of the tests are also given. We have assumed a 2P memory with a memory cell array of 256Kbits; and a cycle time of 10ns Table 5.1: Comparison of the functional tests and their reduced versions based on the topology;

n denotes the memory size

Fuctional O(n2 ) Topological O(n) Test Test lenght Test Duratuin Test lenght Test Duratuin March 2PF 2:1 14n2 ? 13n 2:54h < 113n < 0:289s March 2PF 3 8n2 ? 2n 1:45h < 102n < 0:261s 2 March 2PF 16n ? 3n 2:91h < 269n < 0:688s

Chapter 6

Test strategy Testing 2P memories requires the use of single-port tests as well as special two-port tests. The test strategy determines which tests to be used. As is shown in Chapter 5, many 2P memories have ports which are read-only or write-only; this impacts not only the fault models and tests (as is shown in Chapter 5), but also the test strategy. In this chapter the test strategy for 2P memories, and the consequence of port restrictions will be covered. First, the test strategy for memory cell array faults will be discussed; second, the same will be done for address decoder faults; and nally the test strategies will be integrated.

6.1 Test strategy for MCAFs in 2P memories The MCAFs in 2P memories are divided into 1PFs and 2PFs. Therefore, the test procedure can be divided into two parts: 1. Test(s) to detect simple (and linked) 1PFs, like March U [van de Goor 1997], March LR [van de Goor 1996], etc. 2. Test(s) to detect 2PFs. The 1PFs can be classi ed as cell faults and port faults. 1. Cell faults are port independent faults; they occur in 1P and all types of 2P memories. Therefore, they can be tested via a single 1P test. Cell faults consist, as shown below, of SAF s, DRF s, and CFst s. A SAF can be caused by short between Vdd (or Vss ) and a non-Vss node (and a non-Vdd node), etc. Therefore, a SAF is port independent. A DRF is caused by a broken pull-up device within a SRAM cell. Hence, it is port independent. A CFst does not require any operation in order to be sensitized; therefore, it is port independent. 88

CHAPTER 6. TEST STRATEGY

89

2. Port faults are port dependent and their occurrence depends on the type the 2P memory; e.g., no TF can occur via a Pro. Port faults consist, as is shown below, of SOF s, RDF s, TF s, CFid s and CFds.

A SOF can be due to an open WL, or a WL connected to Vss , etc, such that the cell becomes unaccessible. Therefore, it is a port fault. A RDF is caused by a resistive voltage divider formed with a pass transistor and the on-transistor; hence, it is a port fault. A TF can be caused by a defect in polysilicon layer covering a diusion region, which may result in an extra parasitic pass transistor; and therefore, it is a port fault. A CFid and CFds are caused generally by resistive or capacitive coupling (between bit lines or word lines); and therefore they are port faults.

Table 6.1 gives the three port types and the corresponding sensitizable faults; the + and - denote that the fault can be, respectively can not be, sensitized via the correspondenting port (e.g., the fault RDF can be sensitized via Prw but not via Pwo). Note that CFds is considered only for SRAMs (see Section 3.1.1) and therefore can not occur via Pro. Port faults have to be tested via each port separately. Table 6.1: Port types and their correspondenting port faults Port faults Port type SOF RDF TF CFid CFds Prw + + + + + Pwo + ? + + + Pro + + ? ? ?

The 2PFs are faults based on two simultaneous operations via the two ports. Their sensitization requires the use of the two ports simultaneously, while their detection requires a single read operation via an arbitrary port. Figure 6.1 shows a general strategy to follow in order to test MCAFs in 2P memories: First, the 1PFs are detected in Step A. Step A.1 consists of a (march) test to detect the cell faults (SAF , DRF , and CFst ). Because they are port independent, this test can be applied via either port. Step A.2 consists of a (march) test to detect the port faults (SOF , RDF , TF , CFid , and CFds); it has to be applied twice, once via the rst port and once via the second port. Note that (march) tests for port faults can be selected such that they also detect all faults (e.g., March UD [van de Goor 1997] and March LRD [van de Goor 1996] detect all listed cell and port faults). That means that Step A.1 can be omitted. In that case the march test of Step A.2 is required to detect DRF s. Such march tests contain several operations which are unique for the detection of DRF s. This means that for time eciency reasons, a simpler test (e.g., March U and March LR) can be applied via the second port. The 2PFs are detected by applying an appropriate test (e.g., March 2PF of Figure 10) via both ports simultaneously.


90

In addition, detecting MCAFs depends on the type of ports the 2P memory consists of. For example, it is not always possible to apply a test via any port; e.g., a test (which consists of write and read operations) can not be applied via a Pro or a Pwo. In the rest of this section, the test strategy to detect MCAFs for each type of 2P memory will be discussed. A. To detect 1PFs: A.1. Choose an arbitrary port and apply a test(s) detecting cell faults; A.2. For each port apply a test(s) detecting port faults; B. To detect 2PFs: Apply a test(s) detecting the 2PFs Figure 6.1: General test strategy for MCAFs in 2P memories

6.1.1 Test strategy for MCAFs in (rw-rw)2P memories

Each port has the read-write capability; therefore their port faults consist of SOF s, RDF s, TF s, CFid s, and CFds s; see Table 6.1. March test(s) to detect 1PFs can be applied via each port. Figure 6.2 shows the test strategy that guarantees the detection of all MCAFs in (rw ? rw) 2P memories: Step A guarantees the detection of all 1PFs (i.e., cell faults and port faults of both Prws, assuming the proper test is used), and Step B guarantees the detection of all 2PFs. The 1P-Test has to be a march test that detects all 1PFs, like March UD or March LR; or a combination of march tests that (together) detect all 1PFs. A. To detect all 1PFs: For each port apply a 1P-Test; B. To detect all 2PFs: Apply March 2PF // see Section 4.4 Figure 6.2: Test strategy for MCAFs in (rw-rw) 2P memories

6.1.2 Test strategy for MCAFs in (rw-wo)2P memories

To detect the 1PFs, the test(s) has to be applied via each port. However, this is not possible via Pwo, since it has a write only capability while tests require write as well as read operations. To detect the port faults caused via Pwo, the test(s) has to be applied in such way that the write operations will be done via Pwo and the read operations via the Prw. Figure 6.3 shows the test strategy for (rw ? wo)2P memories which guarantees the detection of all MCAFs. The Step A.1 guarantees the detection of all cell faults and all Prw faults. The Step A.2 guarantees the detection of all Pwo faults. It should be noted that the tests 1P-Test1 and 1P-Test2 can each consists of a single test (e.g., March LR) or of a set of march tests. The Step B guarantees the detection of 2PFs in (rw ? wo)2P memories.


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A. To detect all 1PFs: 1. Apply a 1P-Test1 via the Prw; 2. Apply a 1P-Test2 in such way that: write operation will be done via Pwo; and read operations via Prw; B. To detect all (rw-wo)2PFs: Apply March (rw-wo)2PF //see section 5.3 Figure 6.3: Test strategy for MCAFs in (rw-wo) 2P memories

6.1.3 Test strategy for MCAFs in (rw-ro)2P memories

The (rw ? ro)2P memories have one Prw and one Pro. The Prw faults consist of SOF s, RDF s, TF s, CFid s, and CFds s; while the Pro faults consist only of SOF s and RDF s; see Table2. The port faults of Prw can be detected by applying a test via the Prw, while those of Pro can be detected by applying a test in such way that the write operations will be done via the Prw and the read operations via Pro. Figure 6.4 shows the test strategy that guarantees the detection of all MCAFs in (rw ? ro)2P memories. A similar explanation can be given as by strategy for (rw-wo)2P memories. A. To detect all 1PFs: 1. Apply a 1P-Test1 via the Prw; 2. Apply a 1P-Test2 in such way that: write operations will be done via Prw; and read operations via Pro; B. To detect all (rw-ro)2PFs: Apply March (rw-ro)2PF //see section 5.3 Figure 6.4: Test strategy for MCAFs in (rw-ro) 2P memories

6.1.4 Test strategy for MCAFs in (wo-ro)2P memories

The (wo ? ro)2P memories have one Pwo and one Pro. The Pwo faults consist of SOF s, TF s, CFid s, and CFdss, while the Pro faults consist only of SOF s and RDF s. Note that no test can be applied via Pwo nor via Pro. The only possibility is to apply a test in such way that the write operations will be done via Pwo and the read operations via Pro. Figure 6.5 shows the test strategy for (wo ? ro)2P memories. The Step A guarantees: (1)the detection of all cell faults since they are port independent: they can be sensitized via Pwo and detected via Pro, (2) the detection of all Pwo faults (i.e., SOF s, TF s, CFid s, and CFds s) since they will be sensitized via Pwo and detected via Pro, and (3) the detection of Pro faults: SOF s are sensitized via Pwo and detected via Pro and RDF s are sensitized and detected via Pro. Step B guarantees the detection of 2PFs for (wo ? ro)2P memories using March (wo ? ro)2PF .


92

A. To detect all 1PFs: Apply a 1P-Test in such way that: write operations will be done via Pwo; and read operations via Pro; B. To detect all (rw-ro)2PFs: Apply March (rw-ro)2PF //see section 5.3 Figure 6.5: Test strategy for MCAFs in (wo-ro) 2P memories

6.2 Test strategy for AFs in 2P memories As mentioned in Section 3.2.3, AFs in 2P memories are divided into AF1s and AF2s. Moreover, AF2s consist of faults that are a subset of AF1s (the sAF 2s) and faults which require new tests (the dAF 2s, which will be referred to as AF 2s at this point). Therefore, the test procedure can be divided into two parts: 1. Test(s) to detect AF 1s 2. Test(s) to detect AF 2s. For the detection of AF1s , a march test like MATS+, March X, etc (see [van de Goor 1991]) can be used. The test has to be applied via each port separately. However, this is not always possible; e.g., a test consisting of write as well as read operations can not be applied via a Pro or via a Pwo. In the rest of this section, the test strategy to detect AF1s for each type of 2P memory will be discussed.

6.2.1 Test strategy for AFs in (rw-rw)2P memories

In such memories, each port has the read-write capability; therefore march tests to detect AF1s can be applied via each port separately. Figure 6.6 shows the test strategy that guarantees the detection of all AFs in (rw ? rw)2P memories. Step A guarantees the detection of all AF1s of each port. The test '1P-test' can be any appropriate test. Step B guarantees the detection of AF 2s in row decoders and column decoders; it uses the test described in Section 4.4. A. To detect AF 1s : Apply a 1P-Test via P1, while Port P2 is not active; Apply a 1P-Test via P2, while Port P1 is not active; B. To detect AF 2s: Apply March (rw-rw)AF2 for row decoders; Apply March (rw-rw)AF2 for column decoders Figure 6.6: Test strategy for AFs in (rw-rw)2P memories

6.2.2 Test strategy for AFs in (rw-wo)2P memories

To detect the AF1s, the test has to be applied via each port. However, this is not possible via Pwo, since it has a write-only capability while tests require write as well as read operations. To detect AF1s for Pwo, the test has to be applied in such way that the write operations will


93

be done via Pwo and the read operations via Prw. Figure 6.7 shows the test strategy for (rw ? wo)2P memories which guarantees the detection of all AFs. The Step A.1 guarantees the detection of all AF1s for Prw. Step A.2 guarantees the detection of all AF1s for Pwo. The Step B guarantees the detection of AF 2s in (rw ? wo)2P memories and use March (rw ? wo)AF 2s of section 5.5. A. To detect AF 1s : 1. Apply a 1P-Test via Prw, while Pwo is not active; 2. Apply a 1P-Test in such way that : write operations will be done via Pwo; and read operations via Prw; B. To detect AF 2s: Apply March (rw-wo)AF2 for row decoders; Apply March (rw-wo)AF2 for column decoders Figure 6.7: Test strategy for AFs in (rw-wo)2P memories

6.2.3 Test strategy for AFs in (rw-ro)2P memories

The (rw ? ro)2P memories have one Prw and one Pro. AF1s of Prw can be detected by applying a test via Prw, while those of Pro can be detected by applying a test in such way that the write operations will be done via Prw and the read operations via Pro. Figure 6.8 shows the test strategy that detects AFs in (rw ? ro)2P memories. A similar explanation can be given as for the strategy of (rw ? wo)2P memories. A. To detect AF 1s: 1. Apply a 1P-Test via Prw, while Pro is not active; 2. Apply a 1P-Test in such way that : read operations will be done via Pro; and write operations via Prw; B. To detect AF 2s: Apply March (rw-wo)AF2 for row decoders; Apply March (rw-wo)AF2 for column decoders; Figure 6.8: Test strategy for AFs in (rw-ro)2P memories

6.2.4 Test strategy for AFs in (wo-ro)2P memories

The (wo ? ro)2P memories have one Pwo and one Pro. Note that no test can be applied via Pwo nor via Pro. The only possibility is to apply a test in such way that the write operations will be done via Pwo and the read operations via Pro. Figure 6.9 shows the test strategy for (wo ? ro)2P memories. Step A guarantees the detection of AF 1s since they can be sensitized via Pwo and detected via Pro; however, it can not specify whether the detected AF1 belongs to Pwo or to Pro. Step B guarantees the detection of AF 2s in (wo ? ro)2P memories, using March (wo ? ro)AF 2s of Section 5.5.


94

A. To detect AF 1s: Apply a 1P-Test in such way that : read operations will be done via Pro; and write operations via Pwo; B. To detect AF 2s: Apply March (wo-ro)AF2 for row decoders; Apply March (wo-ro)AF2 for column decoders Figure 6.9: Test strategy for AFs in (wo-ro)2P memories

6.3 Test strategy for all faults in 2P memories

In Section 6.1 the test strategy has been introduced for detecting MCAFs ; and in Section 6.2 the test strategy has been introduced for detecting AFs. In this section, the two strategies will be integrated such that the result test strategy will guaranty the detection of MCAFs as well as AFs. This will be done for each 2P memory type separately.

6.3.1 Test strategy for (rw-rw)2P memories

The test strategy to detect faults in (rw-rw)2P memories is given in Figure 6.10; it results from merging test strategies of Figure ref g:(rw-rw)MCAFsStr and Figure ref g:(rw-rw)AFsStr. Step A guarantees the detection of all 1PFs (i.e., cell faults and port faults) and all AF1s. The test '1P-Test' can be any appropriate test like March DU. Step B guarantees the detection of 2PFs and AF2s A. To detect 1PFs and AF 1s : Apply a 1P-Test via P1, while Port P2 is not active; Apply a 1P-Test via P2, while Port P1 is not active; B. To detect 2PFs and AF 2s: Apply March (rw-rw)2PF; Apply March (rw-rw)AF2 for row decoders; Apply March (rw-rw)AF2 for column decoders Figure 6.10: Test strategy for (rw-rw)2P memories

6.3.2 Test strategy for (rw-wo)2P memories

The integration of test strategy of Figure 6.3 and the test strategy of Figure 6.7 results in the test strategy shown in 6.10; it guarantees the detection of MCAFs as well as AFs in (rw-rw)2P memories. Step A detects all 1PFs (Step A.1 detects cell faults and Prw faults, and Step A.2 detects Prw faults) and all AF1s. Step B detects all 2PFs using March (rw-wo)2PF of Section 5.4, and all AF2s in row decoders and column decoders using March (rw-wo)AF2 of Section 5.5.

6.3.3 Test strategy for (rw-ro)2P memories

Figure 6.7 shows the result of integrating the test strategy of Figure 6.4 and the test strategy of Figure 6.8; it consists of the test strategy for detecting MCAFs as well as AFs in (rw-ro)2P memories. Step A detects all 1PFs (Step A.1 detects cell faults and Prw faults, and Step A.2


95

A. To detect 1PFs and AF 1s : 1. Apply a 1P-Test via Prw, while Pwo is not active; 2. Apply a 1P-Test in such way that : write operations will be done via Pwo; and read operations via Prw; B. To detect 2PFs and AF 2s: Apply March (rw-wo)2PF; Apply March (rw-wo)AF2 for row decoders; Apply March (rw-wo)AF2 for column decoders Figure 6.11: Test strategy for AFs in (rw-wo)2P memories detects Prw faults) and all AF1s. Step B detects all 2PFs using March (rw-wo)2PF of Section 5.4, and all AF2s in row and columns using March (rw-wo)AF2 of Section 5.5. A. To detect 1PFs and AF 1s: 1. Apply a 1P-Test via Prw, while Pro is not active; 2. Apply a 1P-Test in such way that : read operations will be done via Pro; and write operations via Prw; B. To detect 2PFs and AF 2s: Apply March (rw-ro)2PF; Apply March (rw-wo)AF2 for row decoders; Apply March (rw-wo)AF2 for column decoders Figure 6.12: Test strategy for AFs in (rw-ro)2P memories

6.3.4 Test strategy for (wo-ro)2P memories

Figure 6.3 shows the test strategy that detects MCAFs and AFs in (wo-ro)2P memories; it result from merging the strategy of Figure 6.5 and that of Figure 6.9. Step A detects all 1PFs (cell faults and port faults) and all AF1s; while Step B detects all 2PFs using March (rw-wo)2PF of Section 5.4, and all AF2s in row and columns using March (rw-wo)AF2 of Section 5.5. A. To detect 1PFs and AF 1s: Apply a 1P-Test in such way that : read operations will be done via Pro; and write operations via Pwo; B. To detect 2PFs and AF 2s: Apply March (rw-ro)2PF; Apply March (wo-ro)AF2 for row decoders; Apply March (wo-ro)AF2 for column decoders Figure 6.13: Test strategy for (wo-ro)2P memories

Chapter 7

Conclusions and recommendations In this thesis, the functional and the electrical models for single-port (SP) as well as for multiport memories have been covered. The functional models give functions to be realized in terms of block diagrams, while the electrical models give the explicit descriptions of them in terms of transistors. In addition, a complete set of fault models for single-port memories has been described. They have been divided into memory cell array faults (MCAFs), address decoder faults (AFs) and read/write logic faults. The memory cell array faults have been classi ed into three fault classes: the fault class involving a single cell, the fault class involving two cells, and the fault class involving k cells. Address decoder faults have been divided into no access faults and multiple access faults; while read/write logic faults have been mapped onto memory cell array faults. Moreover, memory cell array faults for single-port memories have been analyzed in more detail; they have been divided into strong faults and weak faults. Strong faults are faults which always sensitize a fault, while weak faults are faults which partially sensitize a fault. However, the presence of two or more weak faults at the same time can sensitize a fault, when they have an additive fault eect. This applies to multi-port memories, since they allow for simultaneous multiple operations. That implies that weak faults can be used to develop fault models for these memories. New fault models for two-port (2P) memories have been introduced. They have been divided, as with single-port memories, into MCAFs (2P-MCAFs), AFs (2P-AFs) and read/write logic faults. The latter faults are mapped onto the rst ones. The 2P-MCAFs consist of single-port MCAFs (SP-MCAFs) and MCAFs based on weak SP-MCAFs (denoted as 2PFs). The 2PFs have been classi ed into ve fault classes: the fault class involving a single cell (2PF1), the fault class involving two cells (2PF2), the fault class involving three cells (2PF3), the fault class involving k cells (2PFk), and the fault class involving k + 1 cells (2PF(k + 1)). The 2P-AFs consist of AFs involving a single port (i.e., single-port memory AFs (AF1s)) and AFs involving two ports (AF2s). The AF2s are based on interference between ports. In order to establish a set of AF2s, rst shorts have been injected in the electrical circuits of the two address decoders; thereafter, functional faults have been derived based on the electrical behavior of the circuits in the presence of shorts. Furthermore, functional tests to detect the rst three fault classes of 2PFs (which are the most 96

CHAPTER 7. CONCLUSIONS AND RECOMMENDATIONS

97

important for SRAMs) and functional tests to detect the AF2s have been represented.. The obtained test complexity for such tests is of O(n2 ) for tests for 2PFs and of O(n) for tests for AF2s, whereby n is the size of the memory. The O(n2 ) time complexity makes tests developed for 2PFs less practical for larger 2P memories. The fault models for 2P memories and their tests have been simpli ed based on the port mix, since each of the two port can be read/write, read only, or write only port. In spite of this simpli cation, the test time for 2PFs remains exponentially proportional with the number of ports (i.e., O(n2 )). In order to further reduce the complexity, the topology of the memory has to take into account; while the fault coverage remains high. In this thesis, we have used a presumed topology. The resulting tests are of order O(n), i.e., linear with the size of the memory. All introduced memory cell array faults (i.e., 2PFs) for two-port memories in this thesis are based on the classical fault models of single port memories. Therefore, the possibility of existence of other kind of faults which do not have any origin in a single-port memories remains still to be investigated. This can be done by using Inductive Fault Analysis, which is a systematic procedure to predict the faults in an integrated circuits by injecting spot defects in the stimulated geometric representation of the circuit. The same method can be used to investigate the validity of the introduced fault models.

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Appendix This appendix gives a copy of the paper sent to the 16th IEEE VLSI Test Symposium, Monterey, California, 1998.

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