Formal specification of an FPGA based educational microprocessor Ivan Mezei and Veljko Malbaša Abstract – The goal of the project Edulent has been to produce specification and design of an educational microcomputer that is simple enough to be implemented on a medium complexity FPGA. In this paper we present formal specification of the Edulent by using Register Transfer Notation (RTN) language, [1]. The RTN specification is refined into concrete specification that is the foundation of the Edulent design. We also present some design and implementation details and the features of the final product.
core, memory, and I/O ports that are implemented on an FPGA development board, see Figure 1. FPGA Personal LPT
II. SYSTEM DESCRIPTION Edulent microcomputer consists of microprocessor Ivan Mezei and Veljko Malbasa are with the Faculty of Technical Sciences, University of Novi Sad, Department for electronics, Fruskogorska 11, 21000 Novi Sad, Yugoslavia, E-mail:
[email protected]
J7 conector
J8
computer
Power supply
board
Fig. 1: Edulent system
I. INTRODUCTION Edulent is an FPGA based microcomputer that will be used in the educational environments. Edulent has been developed for an USA company that markets the Xilinx based development boards to the Universities throughout the world. The Edulent requirements are: visual user interface, simple enough for medium size FPGA implementation, formal design, educational, capable to run simple programs, machine and assembly language programming and interface to the real world. The goals of Edulent are: to help the student visualize the functionality of a simple, but real computer, enable students easy understanding of microprocessor design and functioning, assembly and machine language programming, program execution simulation, step by step program debugging and simple interfacing to the real world. There are many FPGA based processor implementations, (extensive list is available in [2]), but very few are educationaly oriented [3,4]. The advantage of the approach is that the Edulent can be implemented on the FPGA based development boards that the students already use in the digital system labs, [5]. This project consists of development of an FPGA based educational microprocessor system and apropriate Windows based software support. Edulent microprocessor is specified using Register Transfer Notation (RTN) language, [1]. Concrete RTN specification was developed afterward and Edulent microprocessor was implemented and tested on Xilinx FPGA development board which is connected to personal computer(PC) via bidirectional parallel port.
cable
A. Microcomputer architecture description Edulent microcomputer architecture consists of an 8bit microprocessor with 11 registers, arithmetic-logic unit (ALU), control unit and 128 bytes memory unit which contains program code and stack. Control unit is microprogrammed [1,6]. ALU can perform addition, substraction, logical negation, logical and, or, exclusive or and shift right functions. All registers are 8 bit except status register that has only two flags – carry and zero. Figure 2 depicts Edulent microcomputer architecture.
PC
A
IR
AP
Control unit
SP memory address register
Mux
ALU
memory data register
R register
Out register In register
Memory 128 bytes
out data in data
Status register
Fig. 2: Microcomputer architecture B. Instruction set Edulent supports four addressing modes: direct, immediate, register indirect and predecrement or postincrement. Instructions that use direct or immediate addressing modes take 2 bytes to execute while register indirect and predecrement/postincrement addressing mode instructions take 1 byte to execute. First byte of the instruction is fetched into instruction register. It is usefull to give alternate names to parts of instruction register since
they have special purpose and are important in interpreting the meaning of an instruction. Instruction format is shown in Figure 3. 7
43
op
2
am
1
0
r1
r0
Fig. 3: Instruction format First 4 bits (op) contain instruction operation code, and next two bits addressing mode. Direct addressing mode is designated in am field as 00, indirect addressing mode as 01, immediate adsressing mode as 10 and predecrement/postincrement as 11. Bit r1 determines whether the register is used as a destination or source. If the last bit r0 is 0 instruction takes one byte to execute. Otherwise it takes two bytes. Instructions are grouped into data movement, arithmetic, logic, branching, procedure control, I/O and program control instructions. Total of 39 instructions (different addressing modes included) are developed. Table 4 lists all instructions that use register indirect addressing and predecrement/postincrement addressing. Table 5 lists all instructions that use direct or immediate addresing. It is assumed that the second byte is an address or a constant and is not specified in Table 5. III. FORMAL EDULENT SPECIFICATION A. About RTN Moving data among registers and memory cells can be specified using notation scheme known as register transfer language. RTN language is based on Instruction Set Processor (ISP) language developed by G. Bell and A. Newell, [7]. It is a good method for incorporating the right level of precision into a computer specification, [1]. B. RTN description of instruction set The following notation is used: PC program counter IR instruction register SP stack pointer A accumulator AP address pointer MA memory address register MD memory data register OUT output data register IN input data register CZ status register R ALU result register M[0..27-1] memory op:=IR operation code am:=IR addressing mode or special for branch instructions r1:=IR result destination or address source(0 - A, 1 - AP) r0:=IR determines instruction length (0 – 1 byte, 1 – 2 byte)
RTN description for instruction fetch is: instruction_fetch → (IR ← M[PC] : PC←PC+1) RTN description of address/constant fetch is: address/constant_fetch → (MD ← M[PC]: PC←PC+1) RTN description of execution phase for all instructions follows: mov(:=op=1)→ ((am=0 ∧ r1=0) → A ←M[address]): (am=0 ∧ r1=1) → AP ← M[address]): (am=1 ∧ r1=0) → A ← M[AP]): (am=2 ∧ r1=0) → A ← const): (am=2 ∧ r1=1) → AP ← const): (am=3 ∧ r1=0) → (A ← M[SP]:SP←SP+1)): (am=3 ∧ r1=1) → (AP ← M[SP]:SP←SP+1))) mov(:=op=2)→ ((am=0 ∧ r1=0) → M[address] ← A): (am=0 ∧ r1=1) → M[address] ← AP): (am=3 ∧ r1=0) → (SP←SP-1 : M[SP] ← A): (am=3 ∧ r1=0) → (SP←SP-1 : M[SP] ← AP)) add(:=op=3)→ ((am=0 ∧ r1=0 ) → A ← A + M[address]): (am=1 ∧ r1=0) → A ← A + M[AP]): (am=2 ∧ r1=0) → A ← A + const): (am=2 ∧ r1=1) → AP ← AP + const)) sub (:= op = 4) → (am=0 ∧ r1=0) → A ← A - M[address]): (am=1 ∧ r1=0) → A ← A - M[AP]): (am=2 ∧ r1=0) → A ← A - const): (am=2 ∧ r1=1) → AP ← AP - const)) not (:= op = 5) → ((am=0 ∧ r1=0) → A ← ¬A ) or (:= op = 6) → ((am=0 ∧ r1=0) → A ← A ∨ M[address] ): (am=1 ∧ r1=0) → A ← A ∨ M[AP]): (am=2 ∧ r1=0) → A ← A ∨ const )) and (:= op = 7) → ((am=0 ∧ r1=0 ) → A ← A ∧ M[address]): (am=1 ∧ r1=0) → A ← A ∧ M[AP]): (am=2 ∧ r1=0) → A ← A ∧ const)) xor (:= op = 8) → ((am=0 ∧ r1=0) → A ← A ⊕ M[address]): (am=1 ∧ r1=0) → A ← A ⊕ M[AP]): (am=2 ∧ r1=0) → A ← A ⊕ const )) shr (:= op = 9) → ((am=0 ∧ r1=0) → A ← 0 # A:CZ=A) jmp (:= op = a) → ((am=0) → PC ← address ) jz (:= op = a) → (((am=1) ∧ ((CZ=1) ∨ (CZ=3))) → PC ← address ) jc (:= op = a) → (((am=2)∧((CZ=2)∨(CZ=3)))→PC←address )
in(:=IR=d0) → (A ← IN )
address )
out (:= IR = e0) → (OUT ← A ) ret (:= IR = b0) → (PC ← M[SP] ) call (:= IR = c0) → ((M[SP] ← PC-1) : ( PC ← nop(:=IR=0) → :
C. Concrete RTN Concrete RTN description is a basis for microprocessor implementation. Design of control unit is simplified after concrete RTN description. The following tables ilustrate concrete RTN description of instruction fetch, address/constant fetch and RET instruction. All other instructions are specified similarly. The following control signals are used in this concrete RTN examples: XXin input from data bus into XX register XXout output XX register on data bus RDMEM read memory PCINC increment program counter SPCH change stack pointer value Table 1: Concrete RTN description of instruction fetch Step T0 T1 T2
RTN MA ← PC MD ← M[PC] : PC ← PC+1 IR ← MD
Control Sequence PCout, Main RDMEM, MDin, PCINC MDout, IRin
Table 2: Concrete RTN description of address/constant fetch Step T3 T4
RTN MA ← PC MD ← M[PC] : PC ← PC+1
Control Sequence PCout, MAin RDMEM, MDin, PCINC
Table 3: Concrete RTN description of RET instruction Step T0-T2 T3 T4
RTN Control Sequence Instruction fetch Instruction fetch SPout, MAin MA ← SP MD ← M[MA]: SP RDMEM, MDin, SPINC, SPCH ← SP + 1 T5 MDout, PCin PC ← MD Concrete RTN description is usefull since it is actually a sequence of microinstructions that creates a microprogram. All control signals that are needed are listed in table and that make control unit development easy and straitforward. IV. IMPLEMENTATION AND TEST Edulent microcomputer is implemented and tested on Xilinx FPGA based development board. Memory is implemented by using FPGA look-up tables. Datapath is implemented by means of standard logic elements [6]. Control unit memory is specified as truth table using Abel hardware description language. By means of that, significant logic reduction is achieved in
comparison to read-only memory implementation due to the fact that implementation software is capable for optimizing logic, and that control unit memory is sparse matrix. Communication block is developed and implemented in FPGA also. It enables communication between the PC and FPGA development board, and enables transfer of Edulent system states to PC. FPGA device utilization summary is reported by Xilinx Foundation Software: Number of CLBs: 190 out of 196 96% Total CLB Flops: 142 out of 392 36% 4 input LUTs: 354 out of 392 90% 3 input LUTs: 97 out of 196 49% Number of TBUFs: 220 out of 448 49% Edulent software support provides user with visualization, single instruction stepping and clock based stepping, assembly language compiler, machine language translator and simulator. Complete system is tested first in simulator mode and after that in real mode, with FPGA development board. System is tested with several simple assembly language programs that included all instructions, addressing modes and all operating modes. V. CONCLUSION We developed Edulent, a simple computer for the educational purposes. The students can use Edulent in several ways. First, they can be exposed to and practice with the Edulent formal specification and design. Next, the students can implement the complete Edulent on an FPGA chip, write Edulent programs, and observe the step by step program execution. Finally, the students can interface Edulent to the real world and write programs that interact with the attached peripheral devices. Edulent can be programmed into Xilinx Spartan chips and it occupies 96% configurable logic blocks (CLBs) of 10000 gate XCS10-4PC84 FPGA [8]. Concrete RTN description is very usefull and efficient method for design of microprocessor not only because it is very generic and straitforward, but it also alows logic reduction. By means of control unit optimization about 7% of total CLBs are saved in FPGA. ACKNOWLEDGMENT The authors thank to Digilent Inc., Pullman, USA, for funding this research. REFERENCES [1] [2] [3]
Heuring P.V., Jordan F.H., Computer systems design and architecture, Prentice Hall, 1997. S. Guccione, “List of FPGA-based Computing Machines”, http://www.io.com/~guccione/HW_list.html S.M.Loo, B.E.Wells, R.K.Gaede, “Exploring the Hardware Software Continuum in a Computer Engineering Capstone Design Class using FPGA-based Programmable Logic”, presented at International Conference on Microelectronic Systems Education, Las Vegas, NV, June 2001
[4] [5] [6] [7] [8]
Jan Gray, “Hands-on Computer Architecture - Teaching Processor and Integrated Systems Design with FPGAs”, presented at ISCA-2000, Vancouver, Canada. Digilab development boards, Digilent Inc., Pullman, USA, http://www.digilent.cc Маno M.M., Kime R.C., Logic and Computer Design fundamentals, Prentice Hall, 2001. Bell C. G., A. Newell, Computer structures: Readings and Examples, McGraw-Hill, 1971. Xilinx Spartan data sheet, http://www.xilinx.com
Table 4: Register indirect, predecrement/postincrement addresing instruction list Assembly language
Machine language
MOV A, [AP]
register indirect addressing 0001 01 00
ADD A, [AP]
0011 01 00
SUB A, [AP]
0100 01 00
OR [AP]
0110 01 00
AND [AP]
0111 01 00
XOR [AP]
1000 01 00
predecrement/postincrement addressing MOV A, [SP+] 0001 11 00 MOV AP, [SP+] 0001 11 10 MOV [-SP], A 0010 11 00 MOV [-SP], AP 0010 11 10
Table 5: Direct and immediate addressing instruction list Assembly language NOP END MOV A, address MOV AP, address MOV A, const MOV AP, const MOV address, A MOV address, AP ADD A, address ADD A, const ADD AP,const SUB A, address SUB A, const SUB AP, const NOT OR address OR const AND address AND const XOR address XOR const SHR JMP label JZ label JC label RET CALL procedure IN OUT
Machine language (first byte) 0000 00 00 0000 00 10 0001 00 01 0001 00 11 0001 10 01 0001 10 11 0010 00 01 0010 00 11 0011 00 01 0011 10 01 0011 10 11 0100 00 01 0100 10 01 0100 10 11 0101 00 00 0110 00 01 0110 10 01 0111 00 01 0111 10 01 1000 00 01 1000 10 01 1001 00 00 1010 00 01 1010 01 01 1010 10 01 1011 00 00 1100 00 01 1101 00 00 1110 00 00
