FPGA-based Random PWM Control of a Buck DC/DC Converter

Massimiliano Luna, Marcello Pucci*, Gianpaolo Vitale and Giuseppe Abbate

J. Electrical Systems 6-3 (2010): 323-338 Regular paper FPGA-based Random PWM Control of a Buck DC/DC Converter

The basic component of an electromagnetic levitation systems are inductance and resistance of the actuator, input DC link voltage, mass of the payload, air-gap between the pole face of the magnet and ferromagnetic guide-way, controller parameters etc. All these parameters are supposed to get change in real life situation. Electromagnetic levitation system (EMLS) is inherently unstable and strongly nonlinear in nature. In most cases a classical controller has been designed for the linear model around an operating point for maintaining overall closedloop stability. In this work, a cascade lead compensation control scheme utilizing inner current loop and outer position loop has been designed and implemented for stabilization of a single magnet based single axis levitation system. The prototype has been successfully tested and stable levitation has been demonstrated at the desired operating gap. The performances of the linear controller with the change in different parameters have been studied experimentally. The dynamic performance of the controller has been tested by applying different disturbance inputs (square wave, sinusoidal etc.) with increasing magnitudes and frequencies. The parameters of the designed controller also get varied during experimentation. So a sensitivity study of the controller for an EMLS is also important.

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Keywords: Electromagnetic levitation, cascade lead compensation, DC to DC chopper, dynamic response, tracking performance.

1. INTRODUCTION

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Recently, a great number of papers dealing with the use of Random Pulse Width Modulation (RPWM) techniques instead of the traditionally used deterministic Pulse Width Modulation (PWM) for DC/AC and DC/DC power conversion have been published. A selection is presented in references [1]-[10]. Studies primarily concerned three-phase inverters but also choppers, converters for switched reluctance motors, high-frequency DC/DC switching converters and many others [1]. The theoretical framework needed to address analysis and synthesis problems for random modulation schemes is given in [5]. The spread of voltage spectra resulting from the adoption of such techniques implies greatly improved acoustic and vibration effects in the supplied converters or drive systems [1]-[4]. A lower conducted and radiated EMI content is an additional benefit of random modulation [2]-[3]. The computational complexity involved in applications such as RPWM control makes it difficult to achieve real-time performance on a general purpose CPU or DSP [11]. The main architectural approach to this challenge is the use of Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA) platforms. The emergence of FPGAs has drawn much attention thanks to the distinct advantages such as high speed, complex functionality, low power consumption, shorter design cycle, lower cost and higher density [3],[12]. The programmability of FPGAs by means of standard hardware description languages such as VHDL and Verilog make them one of the most favorable choices for prototyping digital systems. Previous works concerned the use of FPGAs in systems such as magnetic bearings, PWM inverters, induction motors, AC/DC converters, variable-speed

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I.S.S.I.A.-C.N.R. Sezione di Palermo Institute on Intelligent Systems for the Automation - National Council of Research. Section of Palermo email [email protected] , [email protected] , [email protected] , [email protected] *Address correspondence to this author at I.S.S.I.A.-C.N.R. Sezione di Palermo. Via Dante n. 12. 90141 Palermo, Italy. Tel: +390916113513. Fax: +390916113028. E-mail: [email protected] Copyright © JES 2010 on-line : www.journal.esrgroups.org/jes

Massimiliano Luna et al. : FPGA-based Random PWM Control of a Buck DC/DC Converter

drives and anti-windup compensation of controllers [12]. When comparing the dynamic performance and control capabilities in PWM-controlled power converters, FPGA-based digital techniques perform better than DSPs because of their capability to execute concurrent operations [13], so that the various signals are processed almost simultaneously as if in an analog circuit, enabling a larger bandwidth of the control scheme. In other words, latency is just one clock cycle. Furthermore, the entire scheme could be embedded into a single chip without any additional element; hence evolving high density FPGA architectures, such as those with embedded multipliers, memory blocks, high I/O (input/output) pin count and built-in A/D and D/A converters, represent an ideal solution for power converters applications. This paper proposes a real-time, modular and compact architecture for the FPGA-based RPWM control of the output voltage of a buck DC/DC converter by means of the Random Center Displacement (RCD) technique [2]. No publications dealing directly with RCD modulation in conjunction with buck DC/DC converters have been traced in the literature apart from [6]-[7]. Authors of these papers discuss various randomized schemes, but either they do not present experimental results (power spectra) [6] or they present a spectral analysis which is not exhaustive [7]. Furthermore, both papers do not provide implementation details. All the other examined RPWM implementations refer to Random Lead-Lag (RLL) or Randomized Carrier Frequency (RCF) schemes for DC/DC converters [5],[8]-[9] and to RCD for three-phase power converters [4]. Hence a RCD controller algorithm is proposed, integrated into a PID-driven digital feedback control system and tested using a commercial FPGA to demonstrate the validity of the implementation. A major effort is placed on hardware optimization, so that the design can fit in a smaller FPGA chip, resulting in cost reduction of the controller hardware. The paper is organized as follows. Sections II recalls the fundamentals of deterministic PWM; section III addresses RPWM and describes the RCD technique. Section IV gives the details of the used DC/DC converter and recalls the related closed-loop control scheme. Section V describes the proposed architecture and gives some details of the implementation. Experimental set-up and results are reported in section VI. Conclusive remarks close the paper.

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2. DETERMINISTIC PULSE WIDTH MODULATION Output voltage control in PWM static power converters is performed by choosing at any instant the most appropriate duty cycles driving the converter switches. The duty cycle d is the ratio of the on-time of the switch to the duration T of the switching period: t t on (1) d = on = T t on + t off The PWM waveform can be obtained in different ways [14]. The classical analog implementation encompasses a comparator and an integrator, which generates a ramp from a constant signal. The output of the integrator gives either a sawtooth or triangular carrier at the sampling frequency f s = 1 , which is compared to a reference signal in order to T determine the switching instants, as shown in fig. 1. With a sawtooth carrier of amplitude A, a reference signal u* in the range [0; A] will correspond to a duty cycle in the range [0; 1]. Instead, by using a triangular carrier which varies in the range [-A; A], the reference signal u* shall belong to the same interval in order to generate an output signal u with a duty cycle in the range [0; 1]. When digital signal processing methods are preferred, integrators are replaced by digital timers at frequency f c >> f s and the digitized reference signal is compared with the actual timer count at the high repetition rate fc to obtain the required time resolution. This process 324

J. Electrical Systems 6-3 (2010): 1-12

is referred to as natural sampling. However other sampling techniques exist which are optimized for digital platforms, especially for microprocessors.

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Fig. 1. Analog generation of PWM waveform.

The method used in this paper is referred to as symmetrical regular sampling [14]. It allows to sample the reference waveforms at the very low repetition rate fs, i.e. just once in a sampling period. Referring to fig. 2, in order to simplify the discussion, the carrier has unity amplitude. The sampling instants are referred to as tsn, where subscript n denotes the n-th period. The switching instants are denoted by T1n and T2n, for negative and positive edges respectively.

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Fig. 2. Symmetrical regular sampling.

The triangular carrier shown as a dotted line does not have to be generated as a signal since, by means of geometrical relationships, it is possible to obtain equations which allow to compute the switching instants in real time, starting from the reference value u*. If both carrier and reference signal vary in the range [-1; 1] the switching instants are given by (2) and (3), where the subscript n has been omitted for the sake of simplicity. T (2) T1 = ⋅ 1 + u * (t s ) 4

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T T (3) + ⋅ 1 − u * (t s ) 2 4 Instead, if the range for both carrier and reference signal is [-R; R], equations (2) and (3) become: T (4) T1 = ⋅ R + u * (t s ) 4R T T T (5) 2 R + R − u * (t s ) T2 = + ⋅ R − u * (t s ) = 2 4R 4R which can be expressed also as: 1 (6) T1 = ⋅ R + u * (t s ) 4 Rf S 1 (7) T2 = ⋅ 3R − u * (t s ) 4 Rf S As fig. 2 shows, this technique allows to generate a PWM signal with the desired duty cycle in which the low pulse is centered at the sampling instant. The duty cycle of the PWM output waveform varies in the range [-1; 1] as the reference signal goes from –R to R. Resolution α on the pulse width is given by the following formula: 1 (8) α= 2 Rf s T2 =

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3. RANDOM CENTER DISPLACEMENT PWM

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The duty cycle of the switching signal does not depend on the location on the oninterval within the switching interval, i.e., the pulse position, nor on the length of the switching interval, i.e., the switching frequency. On the other hand, the presence of discrete harmonics in the spectrum is tied to periodical repetition of events. For these reasons, if either the pulse position or the switching frequency is varied in a random manner, the power spectrum of the output voltage of the converter acquires a continuous part, while the discrete (harmonic) part is significantly reduced. This is the basic principle of random pulse width modulation (RPWM) [1]. Several RPWM schemes are available, each with its set of advantages and disadvantages. The chosen scheme belongs to the family of fixed switching frequency techniques and it is referred to as Random Center Displacement (RCD) [2] or Random Pulse Position (RPP) [7]. Starting from a deterministic PWM waveform, which is e.g. left-aligned in the switching period, it consists in displacing the pulse center by a random amount ΔT from the alignment reference, as shown in fig. 3 for a signal with a constant duty cycle equal to 0.4.

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Fig. 3. Typical Random Center Displacement waveform.

This method is a variant of the random lead-lag (RLL) technique, which is simpler because it consists of a random selection of only two possible positions, namely at the beginning or at the end of the interval. To be coherent with the symmetrical regular sampling technique described in the previous section, it is possible to start from a deterministic PWM waveform whose low pulse is center-aligned in the switching period and then to apply the random displacement 326


to the pulse position. To prevent overlap between consecutive PWM periods, it is required that the pulse displacement satisfies the following equation: T (9) | ΔT |≤ d 2 On the contrary, if the random displacement is applied to the high pulse position, to prevent overlap the following equation should be satisfied: T (10) | ΔT |≤ (1 − d ) 2 A practical RCD implementation could use a pseudo-random number generator whose output n is uniformly distributed. If, for example, n ∈ [-100; 100], taking into account equations (9),(10) the pulse displacement could be determined as: ΔT = n ⋅ ΔTmax / 100 (11) T T where ΔTmax = d or ΔTmax = (1 − d ) respectively. 2 2

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4. CONTROL SCHEME FOR THE BUCK CONVERTER

The considered buck DC/DC converter was built for a previous work in order to measure and emulate the I-V behaviour of a photovoltaic array [15]. The rated power is about 3 kW and the design of the converter’s output filter was carried out so to obtain continuous-current conduction operation and output voltage ripple not exceeding a few percent. The above mentioned conditions led to choose the following values for the capacitor and the inductor: C=33 μF, L=3.7 mH. As for the power device, a power MESH IGBT was chosen in order to manage a maximum current of about 20 A. The converter was operated at constant switching frequency (10 kHz) and input DC voltage (250 V). The present work proposes a general architecture which allows to control a buck converter by means of a conventional PID regulator in a closed-loop control system, as shown in fig. 4. Specifically, the algorithm is tested with the parameters expressed by (12), which correspond to a PI regulator designed with traditional methods [16] aimed to get suitable steady state error, bandwidth and stability margins. K P = 0.002, K I = 0.22, K D = 0 (12)

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Fig. 4. Control scheme of the buck converter.

The output of the regulator, being the reference value for the duty cycle of the signal which drives the IGBT of the converter, is saturated to a suitable range, namely [0.1; 0.9], to avoid the stall of the converter, i.e. a very long time interval during which the

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semiconductor device does not change state, due to a very high error signal. The power switch is driven by either a deterministic or a random PWM signal, generated by the PWM modulator; its carrier frequency will be incremented to 25 kHz and made equal to the sampling frequency of the whole control system.

5. ALGORITHM IMPLEMENTATION Aiming to test the algorithm on a starter board with an embedded Altera Cyclone III EP3C25F324 FPGA [17], it has been coded in VHDL and synthesized by using a software tool provided by the same manifacturer, i.e. Altera Quartus II [18]. In the following, the FPGA design flow is described. First, the design is coded and simulated to verify its correctness. Then the user assigns the pins of the FPGA chip by using the pin planner and invokes the logic synthesis: the software will optimize the design and will carry out the placement and routing automatically to generate the FPGA implementation file. Finally, the generated file can be downloaded to the FPGA for testing. This section explains the algorithm implementation, while the experimental set-up is fully described in section VI. A modular architecture has been chosen, in order to build reusable blocks of code implemented as VHDL components. This has allowed also to verify individual components before integrating them into the closed-loop system and testing the final system on the experimental setup. The synopsis of the system is shown in fig. 5, in which the internal connections of clock and reset lines have been omitted for the sake of simplicity. Besides those which correspond to the control blocks of fig. 4, other components have been implemented, which allow additional features.

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ssd_dp ssd_sign

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Fig. 5. Synopsis of the control system implemented on FPGA, with the I/O pin assignments.

The select reference block, driven by the related input sel_ref, chooses whether the reference voltage is equal to the value read by the first channel of the ADC, which is connected to an external potentiometer, or to the output of an internal 0.5 Hz square wave generator, in order to test the response of the system to a step input voltage. The ADC interface block allows the FPGA to be interfaced to a serial ADC located on an expansion board. Handshaking between FPGA and ADC is through four signals whose names are related to the peripheral, so that e.g. signal adc_dout goes into the FPGA. A suitable block interfaces the FPGA to a 4-digit, 7-segment display (SSD), placed on a purposely designed board with a mechanical selector, connected to the sel_disp input, which allows to select the item to display (reference voltage or actual output voltage). The sel_random input allows to choose either deterministic or random PWM operation. Finally, two FPGA pins are connected respectively to the 50 MHz oscillator and to the reset button, which are located on the demo board. The following subsections describe thoroughly the implementation of the two main blocks of the control system (PID controller and PWM 328


generator) and the various scaling blocks needed.

A. PID controller The continuos-time transfer function of the PID regulator is given by (13), where KP, KI, KD are the parameters of the controller, and E(s), V(s) denote the Laplace transforms of its input and output signals respectively. V ( s) 1 (13) G(s) = = KP + KI ⋅ + KD ⋅s E ( s) s In order to implement the control algorithm using digital technology, equation (13) has to be discretized [19]. Denoting the sampling period as T and using Euler’s backward approximation, the difference equations for the proportional, integral and derivative components of the PID regulator can be determined. If k denotes the k-th sampling instant and e(k), v(k) represent the sampled values of the input and output signals respectively, it is possible to say that: v(k ) = P(k ) + I (k ) + D(k ) (14) where: ⎧ P ( k ) = K P ⋅ e( k ) ⎪ ⎪ (15a,b,c) ⎨ I (k ) = I (k − 1) + K I T ⋅ e(k ) ⎪ KD (e(k ) − e(k − 1)) ⎪ D(k ) = T ⎩ Having obtained the discretized control algorithm, the focus is then placed on its efficient implementation. Since real numbers as defined in VHDL standard [20] are not synthesizable, two possibilities exist in order to manipulate such numbers: either to use nonstandard floating-point libraries (provided by FPGA manifacturers or self-written), or to use fixed-point notation. Aiming to make the software implementation simple, reusable with different sets of parameters and portable across different hardware devices, it has been decided to use fixed-point notation and to represent numbers using suitable scale factors. The choice of signal width in fixed-point arithmetic is crucial in maintaining system stability. Even if a longer signal width reduces quantization effects, it results in an increase in hardware resources; on the other hand, a short signal width will affect the controller precision, causing an increase in control error or destabilization of the system [12]. In order to have a sufficient resolution, the range [-512; 511] has been chosen for the input signal of the PID controller. Instead, the coefficients of the PID regulator, multiplied by ten, can vary in the range [0; 255] so that the algorithm is able to implement a PID regulator with a set of actual coefficients in the range [0; 25.5] in 0.1 increments. Therefore, the following quantities can be considered: K P ' = 10 ⋅ K P , K I ' = 10 ⋅ K I , K D ' = 10 ⋅ K D (16) and substituted in equations (16a,b,c) so to obtain the equations to implement: K '⋅e(k ) ⎧ P(k ) = P ⎪ 10 ⎪⎪ K '⋅e(k ) (17a,b,c) I (k ) = I (k − 1) + I −1 ⎨ 10 ⋅ T ⎪ ⎪ D (k ) = K D '⋅ T −1 ⋅ (e(k ) − e(k − 1) ) 10 ⎪⎩ Referring to each fraction in (17a,b), it is worth noting that the product of the terms in the numerator should be calculated before performing the division by the denominator, in order to minimize the negative effect of the integer division. The number of bits (nP) required to represent correctly the proportional output signal

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can be determined from (17a) by means of the following calculations: 255 Pmax = ⋅ 512 = 13,056 n P = 1 + log 2 Pmax = 14.67 → 15bit (18a, b) 10 As to (17c), remembering that e(k) is signed and that the sampling frequency is 25 kHz, it is possible to determine that nD=31. Equation (17b) for the integral part is recursive and it has a large denominator, thus some problems could arise. Firstly, if the absolute value of the input e(k) multiplied by K I ' is lower than the quantity 10 ⋅T −1 , the second term in (17b) will be null due to the integer division and the integrator’s output will not increase nor decrease, in spite of a non-null input. Therefore it is convenient to define a new signal M ( k ) = 10 ⋅ T −1 ⋅ I (k ) , so that (17b) can be written as:

M (k ) = M (k − 1) + K I '⋅e(k ) (19) By choosing M(k) as the internal variable and by implementing (19) instead of (17b), the value of M(k) will increase or decrease correctly as e(k) varies. The output of the integrator, then, can be calculated as: M (k ) I (k ) = (20) 10 ⋅ T −1 The second problem is that signal M(k) could overflow. Therefore, the algorithm must include a check for this condition; specifically, in the proposed implementation, the maximum size allowed for VHDL signals has been chosen for M(k), i.e. 32 bit signed. Thus, by using (20), it is possible to determine that the number of bits required to represent correctly the integrator’s output signal is nI=15. Finally, the three components will be summed according to (14), so the number of bits (nPID) required to represent correctly the PID output signal can be determined as follows: (21) n PID = 1 + log 2 ( Pmax + I max + D max ) = 30.28 → 31bit

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In order to track past values of signals e(k) and M(k), two arrays have been used: a 2-elements, 10-bit array and a 2-elements, 32-bit array respectively. Each array acts like a shift register, since at each sampling instant a new element enters the array, the other ones are shifted back by one position and the oldest one exits the array. In addition to what explained before, it is necessary to implement a suitable anti-windup action. It has been pointed out in section IV that the output of the PID regulator should be saturated to a suitable range to avoid the stall of the converter. Therefore, in order to keep the software as simple as possible, though effective, it has been chosen to use another saturator with the same limits applied to the integrator’s internal variable M(k) as an antiwindup technique.

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B. PWM generator The second main component of the control system is the PWM generator, which is able to generate both deterministic and random (RCD) PWM signals, as described in sections II and III. The parameter R for the symmetrical natural sampling technique has been set to 250, so that resolution on the pulse width is 80 ns, according to (8). Hence the reference signal u* will be represented with a signed 9 bit signal. The chosen sampling frequency is 25 kHz and it is equal to the theoretical carrier’s frequency. A counter is needed to track time starting from the origin shown in fig. 2 (negative peak of the theoretical triangular carrier). Equations (6),(7) show that a remarkable simplification can be attained if the quantity 1 is used as the timebase; this means that the PWM 4 Rf S clock, obtained by a division of the main 50 MHz clock, should be equal to 4 Rf S so there will be 4R ticks in a PWM period. Then the values which identify the switching instants will be expressed by the following simpler equations: 330


T1 ' = R + u * (t s )

(22) (23)

T2 ' = 4 R − T1 ' and they will belong to the following intervals: T1 '∈ [0;2 R ] and T2 '∈ [2 R;4 R ] . As to equation (23), it should be noticed that most compilers and synthesis tools will automatically optimize the calculation by substituting the product with shift and subtraction operations, as T2 ' = R

FPGA-based Random PWM Control of a Buck DC/DC Converter

FPGA-based Random PWM Control of a Buck DC/DC Converter

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