FPGA implementation of ICA algorithm for blind ... - Semantic Scholar

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IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 14, NO. 5, SEPTEMBER 2003

FPGA Implementation of ICA Algorithm for Blind Signal Separation and Adaptive Noise Canceling Chang-Min Kim, Hyung-Min Park, Taesu Kim, Yoon-Kyung Choi, and Soo-Young Lee, Member, IEEE

Abstract—An field programmable gate array (FPGA) implementation of independent component analysis (ICA) algorithm is reported for blind signal separation (BSS) and adaptive noise canceling (ANC) in real time. In order to provide enormous computing power for ICA-based algorithms with multipath reverberation, a special digital processor is designed and implemented in FPGA. The chip design fully utilizes modular concept and several chips may be put together for complex applications with a large number of noise sources. Experimental results with a fabricated test board are reported for ANC only, BSS only, and simultaneous ANC/BSS, which demonstrates successful speech enhancement in real environments in real time. Index Terms—Adaptive noise canceling (ANC), blind signal separation (BSS), independent component analysis (ICA), speech recognition, system on chip.

I. INTRODUCTION

A

LTHOUGH current speech-recognition technologies have been quite successful for clean speech signals, poor performance in real-world noisy environments prevents speechrecognition technology from becoming popular. To overcome this critical difficulty, it is necessary to enhance speech signals by eliminating noises from speech-and-noise mixtures. Speech enhancement has two approaches, i.e., adaptive noise canceling (ANC) and blind signal separation (BSS). ANC is an approach to reduce noise based on reference noise signals while no reference signal is known for BSS. The least-mean-square (LMS) algorithm has been the popular choice for ANC [1], [2]. With the assumption of linear mixing and statistical independence among acoustic sources, independent component analysis (ICA) has recently been developed for BSS [3]–[7]. The ICA algorithm is also applicable to ANC with much better performance than that of LMS algorithm [8]. Also, the ICA results in a unified framework for simultaneous ANC and BSS for practical applications. However, the ICA-based algorithms for convolutive mixtures with multipath reverberation require enormous computing Manuscript received September 15, 2002; revised March 18, 2003. This work was supported by the Korean Ministry of Science and Technology. C.-M. Kim and H.-M. Park are with the Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 305-701, Korea (e-mail: [email protected]; [email protected]). T. Kim is with the Department of BioSystems, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 305-701, Korea (e-mail: tkim @neuron.kaist.ac.kr). Y.-K. Choi is with the Extell Technology Corporation, Seoul 44-10, Korea (e-mail: [email protected].) S.-Y. Lee is with the Department of BioSystems and the Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology(KAIST), Daejeon 305-701, Korea (e-mail: [email protected]). Digital Object Identifier 10.1109/TNN.2003.818381

power in real time. Also, the algorithms are memory intensive and conventional digital signal processor (DSP) architecture is not efficient. Although a few analog VLSI implementations had been reported for ICA algorithm, they were applicable to instantaneous mixtures only and were unable to be utilized for real-world speech-enhancement applications with convolutive mixtures [9], [10]. For convolutive BSS problems, only a few VLSI architectures had been presented without actual implementation and experimental results [11]–[13]. A DSP implementation was reported for only a simplified mixing condition with two closely spaced microphones [14]. In this paper, an FPGA implementation of digital chip is reported with modular design concept. The chip is capable of up to 32-channel convolutive BSS/ANC with total 30 512 time delays. In Section II, an ICA-based unified theory is introduced for the ANC and BSS. In Section III, an FPGA implementation and a test board are presented. Experimental results are reported in Section IV. II. ICA-BASED ALGORITHM FOR BLIND SIGNAL SEPARATION AND ADAPTIVE NOISE CANCELING A. ICA-Based Blind Signal Separation As shown in Fig. 1, BSS attempts to separate unknown from linear mixtures of sources . Here, the independent sources number of microphones and the number of sources are the same as . The measured mixed signal at the th microphone at the th sampling time may be represented as

(1)

(2) denotes the th source signal at the th sampling where is the convolutive mixing coefficient from the time and th source to the th microphone with the th time delays for the multipath reverberation. is the number of the longest time is the undelays for the convolutive mixing filters. Also, mixing coefficient from the th source to the th microphone with the th time delays. Here, to avoid signal whitening, we without any time-delay set component and do not attempt to deconvolve each source and

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KIM et al.: FPGA IMPLEMENTATION OF ICA ALGORITHM FOR BLIND SIGNAL SEPARATION AND ADAPTIVE NOISE CANCELING

Fig. 1.

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Network architecture of the blind signal separation.

Fig. 2. Network architecture of the adaptive noise canceling.

concentrate on the signal separation only. In this case, the feedfor easy estimation of time back architecture allows time delays are considered for simplicity. Dedelays. Only pending upon acoustic environments and sampling frequency, the maximum number of time delays may be set between several hundreds and several thousands. The BSS algorithm adaptively estimates the unknown mixing coefficients from examples of mixed signals . In an ICA-based BSS algorithm, the adaptation is made toward the extraction of statistically independent sources by maximizing entropy as [5], [6]

sources

through convolutive channels . The other sensors receive the noise signals to form the reference signals. The goal , which is the best estimate of the is to get a system output as signal (4) The successful noise-canceling filters are . The most popular algorithm for noise cancellation is the least-mean-square (LMS) algorithm, which minimizes the squared error and results in [1], [2]

(3) (5) denotes the probability denwhere is a learning rate and sity function of . Here, we assume that the demixing filter coefficients are updated at every sampling index , but the index is not shown in (3) for simplicity. Speech signals usually have sign . The Laplacian distribution, which results in stochastic learning rule may be implemented as online or batch mode. B. ICA-Based Adaptive Noise Canceling

where is a learning rate. Equation (5) decorrelates the output signal from the reference noise signals and removes noise components of the primary input signal based on second-order statistics only. However, the speech and noise signals may depend upon in higher order statistics. Comparing Figs. 1 and 2, it is clear that ANC is a special case of BSS with zero values for some mixing coefficients. Therefore, we may derive an ANC algorithm based on ICA by minimizing entropy as

An adaptive noise-canceling system is shown in Fig. 2, is transmitted over a channel to a where the signal www.cadfamily.com is added from the noise microphone and the noiseEMail:[email protected]

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(6)

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(a)

(a)

(b) Fig. 3. Signal flow of the basic ANC module. (a) Straightforward implementation and (b) memory bandwidth reduction by delayed learning. (b)

Comparing (5) and (6), one notices that the LMS algorithm is a special case of the ICA-based algorithm for Gaussian signals. In [8], the same adaptation rule was derived with linear approximation near convergence for independent identically distributed (i.i.d.) signals. Also, the convergence property of (6) is similar to that of LMS algorithm [15]. However, only statistical independence is assumed in this paper. The ICA-based ANC algorithm can remove noise components based on statistical independence, which incorporates both second-order and higher order statistics [8]. The ICA-based algorithm outperforms the popular LMS algorithm, especially for the speech and music noises [8]. Both speech and music have super-Gaussian probability distribution and higher order statistics are important in these signals.

Fig. 4. Block diagram of the basic ANC modules. (a) One-channel ANC module. The bandwidth of weight memory is twice of the system clock, because the memory operation of weight is (load, save) while noise is (load). (b) Two-channel ANC module with half time delays. All critical paths including memory operation are using an identical system clock. TABLE I HARDWARE SPECIFICATIONS OF THE BASIC ANC MODULE

C. Simultaneous ANC and BSS Now we combine the BSS in Section II-A and ANC in Section II-B. An array of microphones measures the mixed signals, which consist of multipath convolutions of speech signal and several noise sources. Also, it is assumed that some of the For example, one may put several microphones in a running car www.cadfamily.com EMail:[email protected] noise sources may be approximately extracted by other means. to measure mixtures of speech, car audio music, engine noise,



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Fig. 5. Input and output configurations of the ANC module.

wind noise, etc., and the music signals may be extracted from the “line” jack of the car audio. By combining (2) and (4) and applying the same maximum entropy concept simultaneously, one obtains adaptive learning rules similar to (3) and (6). III. FPGA IMPLEMENTATION OF ICA ALGORITHM A. Basic ANC Module In general, the neural network is composed with repetitions of simple core operation. For this reason, one can implement a highperformance system using parallelism. However, in practical applications for memory-intensive ICA algorithm, parallelism is limited by memory bandwidth. Therefore, we incorporate a processor and memory in a basic ANC module, which is designed for a single-channel ANC in Fig. 2. By incorporating many ANC modules, one can design more powerful chips for multichannel ANC and BSS applications. The function of ANC module at the th sampling time can be expressed as (7a) (7b) The required memory bandwidth can be calculated as 5 K, i.e., and for (7a) and 3 K for loading and 2 K for loading , and saving for (7b). This computation is illustrated in Fig. 3(a). Straightforward implementation of (7) requires us to first and adapt later with the calculated , calculate and twice at every iterwhich results in loading ative learning epoch (i.e., sampling time). To reduce required and should be utimemory bandwidth, each loading of in (7a) and in lized twice for the calculation of both (7b). Therefore, (7) was modified as (8a) (8b)

the required memory bandwidth can be reduced as 3 K(load , load , save ) while memory utilization goes down as . The loss of memory utilization is very trivial, because the number of time delays for deconvolution in real-world applications is very large. Fig. 4(a) presents the block diagram when the ANC module is working in a deeply pipelined state. By adding a register to keep the previous noise data, the weight update procedure and the noise deconvolution procedure are performed concurrently. This removes the redundant memory operation of weight coefficients. The design parameters are chosen after careful simulations based on the real data. We use 12-KHz sampling with 12-bit A/D conversion, which is commonly used for the automatic speechrecognition system. With higher sampling rates, we just need more computing power and memory bandwidth with given convolutive mixing channels. For successful performance, 12-bit integer data and 30-bit floating-point data are used for the mixed signals and the unmixing matrix element , respectively. Although the magnitude normalization had been incorporated into the learning rule, the unmixing matrix elements still require much higher precision than the signal itself and are represented as floating-point value with a reduced exponent that is normalized with the minimum learning rate. Also, 512 time delays are appropriate for practical room reverberation with 12-KHz sampling. When system clock frequency and sampling frequency are 12.288 MHz and 12 KHz, respectively, the number of time delays is 1024 in the module proposed in Fig. 4(a). Since the memory operations related to weight is (load, save) while noise is load only, the required memory bandwidths of noise data and weight coefficients are 12.288 and 24.576 M/s, respectively. We used the separated weight memory to reduce the bandwidth equal to system clock. Therefore, all critical paths including memory operation utilizes an identical system clock speed and the maximum number of time delays is expressed as the ratio of sampling frequency to system clock frequency. This design scheme is easily implemented by adding a buffer register for the weight and guarantees the successful working in any technology even in FPGA. The basic element of the developed hardware is a two-channel ANC module, of which specifications are summarized in Table I. The modified function of the basic ANC module can be expressed as

in the learning phase, the By using the delayed output learning procedure and the deconvolution can be done at the and are loaded, same time. At every , is accumulated for , and is updated and saved. In (8a), to specify the extra memory required to store previously , the summation limit is reduced to calculated value www.cadfamily.com . The computation EMail:[email protected] flow is illustrated in Fig. 3(b) and


(9a) (9b)

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(a)

(b)

(c) Fig. 6. Construction for the extended chips for multichannel ANC and/or BSS. (a) 16-channel ANC with 500 time delays, (b) four-channel ANC with 2000 time delays, and (c) simulation two-channel BSS and seven-channel ANC with 500 time delays.

We designed the basic ANC module that performs note update signal, microphone input, noise-reference input, two-channel noise canceling with 512 time delays. Only output of submodule, deconvolution output, and the oldest one accumulator register is used here for the single noise-ref- noise data, respectively. The “Update” controls the direction erence sensor. This basic module is the common factor of of the learning and is unique for each microphone channel. multichannel ANC and multichannel BSS. There is no need One can construct extended systems with more channels by to integrate complex functions in a module. The basic ANC accumulating the “Do” of submodules that have the same module is designed in modular concept to extend the numbers “Update” and connecting to the “SubIn” of a master module. of BSS channels, ANC channels, and time delays. In Fig. 5, Also, the “DnSub” is useful for the extension of time delays “Update,” “Dm,” “Dn,” “SubIn,” “Do,” and “DnSub” de- by connecting the “DnSub” to the “Dn” of hierarchically www.cadfamily.com EMail:[email protected]



upper module. It is worth noting that each module has its own memory for noise data and weight coefficients for easy multimodule system implementations. Unlike the fully parallel architecture for convolutive BSS [11], [12], our basic ANC module utilizes time multiplexing to reduce chip size while maintaining realistic number of time delays for real-world convolutive ANC and BSS applications.

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TABLE II FIVE TASKS FOR THE TESTING EXPERIMENTS

B. Multichannel ICA Chip Extended multichannel ICA chips are developed based on the ANC module for ANC and/or BSS applications. Several configurations of the extended multichannel ANC and BSS systems are illustrated in Fig. 6. Fig. 6(a) and (b) show the 16-channel ANC with 500 time delays and four-channel ANC with 2000 time delays, respectively. A simultaneous two-channel BSS with 500 time delays and seven-channel ANC with 500 time delays is shown in Fig. 6(c). Although the developed multichannel ANC systems are efficient with variable number of time delays and without any loss of memory capacity, the memory utilization for the multichannel BSS systems is reduced. In the BSS systems, because the weight update is dependent on the output values of the other modules, one cannot share the weight memory among modules. However, the noise memory can be shared among modules that have the same reference noise source. In the extended system, all ANC modules are working independently until the final outputs are accumulated. The ANC operation can be extended easily up to 32 channels and the number of time delays can be extended to 32 512. IV. EXPERIMENTAL RESULTS

Fig. 7. Twelve different impulse reponses for the mixed signals. The horizontal axis is the number of time delays.

based on auditory models [16]. Although approximately 10 min are required for complete convergence, it provides reasonable performance after 1 min, as shown in Fig. 8.

A. Results With Artificially Mixed Signals We have implemented the ICA chip with ALTERA B. Results With Real Mixed Signals EP20K600EBC652–1 FPGA, which supports embedded To test the performance of the developed FPGA, we had fabmemory. The developed chip was tested for five different tasks, ricated a test board that consists of six-channel AD converters as summarized in Table II. with amplifiers for analog signals, an FPGA for BSS and/or To calculate signal-to-noise ratios (SNRs) accurately for this ANC operations, and two-channel DA converters for signal outtesting phase, we used artificially mixed signals with known puts. As shown in Fig. 9, two microphones are connected to two measured room impulse responses in Fig. 7. As shown in Fig. 7, input channels for mixed BSS signals and the other four input the impulse responses have about 500 time delays. The mixed channels are used for ANC sources. The signal sources for BSS signals were simulated on a computer with several impulse re- are a male speech signal and speaker-generated female speech sponses randomly chosen from Fig. 7. Then, an implemented or car-noise signal. The 4 ANC noise signals are electrically FPGA was connected to the computer for conducting required tapped from 4 speakers with different music signals. However, BSS and/or ANC. the ANC noise signals undergo room impulse responses and the Fig. 8 shows results of the five experiments with music and noise signals at microphones are different from these electrical car noises. Also, the SNRs of mixed and unmixed signals are signals. During testing, all five speakers are turned on and a male summarized in Table III. For ANC-only operation of Tasks I speaks at approximately 1–2-m distances from the two microand II, the single chip results in unmixed signals with 21-dB or phones. A headset is also available to actually hear the enhanced higher SNRs, which is high enough for good speech-recogni- speech signals. The test board with an FPGA works in real time tion performance. Both ANC tasks demonstrated about 30-dB with a 12-kHz sampling rate. enhancements of SNRs. For simultaneous BSS with/without The experimental results in the real world are shown in ANC operations of Tasks III, IV, and V, the performance is Fig. 10. In Fig. 10, BSS sources are two human speech signals, either limited to about 15-dB final SNR or about 21-dB SNR en- one male speech and one female speech. In this real experiment, hancements. It is commonly understood that BSS performance we do not know the exact noise signals at the microphones for is limited by mismatches of estimated Laplacian distribution SNR calculations. However, the enhanced outputs have very and actual probability density functions (pdfs) of signals. The good speech quality, which is considered as about 16-dB SNR www.cadfamily.com EMail:[email protected] 15-dB SNR is acceptable with noise-robust feature extractors by human hearing and popular speech-quality measures.


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Fig. 8. Experimental learning curves of the five experiments.

Fig. 9. Demonstration system for simultaneous two-channel BSS and four-channel ANC operations.

features based on an auditory model and recognizes with radial basis function (RBF) neural networks [17]. For the test of noisy environments, we used artificially mixed signals with known room impulse responses in Fig. 7 and performed simultaneous two-channel BSS (car noise and speech) and four-channel ANC (music) operations. At the training phase of the RBF networks, only the clean TI-46 digit database was used. At the test phase, speech signals with and without the FPGA enhanceFig. 10. Experimental results for the demonstration system for simultaneous ments are tested. The results of experiment are shown Fig. 11. two-channel BSS and four-channel ANC operations. Although speech-recognition rates are greatly reduced from the initial 99.8% recognition rate without speech enhancement, C. Results of Speech Recognition no reduction of recognition rates are shown up to 10 dB The enhanced speech signals are also tested for speech SNR with the FPGA implementation of ICA-based speech recognition. For the speech signal, male speeches in TI-46 enhancements. Therefore, the developed FPGA demonstrated digit database are used. The enhanced speech signals are fed successful performance to be used as a preprocessor for speech www.cadfamily.com EMail:[email protected] to an ESR-700 speech-recognition chip, which extracts speech recognition systems in the real-world noisy environments.



Fig. 11.

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Experimental results for speech recognition with and without speech enhancements.

The power dissipation of the ANC module is estimated as 98.8 mW at 1.8 V and 12.288 MHz with the FPGA. This includes the dissipation of the embedded memory and excludes the power dissipation at pads. It can be expressed as 49.4 mW per single-channel ANC with 500 time delays. Currently, we are designing a multichannel system with Hynix 0.35 CMOS technology and the power consumption is estimated as 14.5 mW per ANC module. V. CONCLUSION In this paper, we present an FPGA implementation of simultaneous ANC and BSS operations for speech enhancement. Both ANC and BSS algorithms are based on ICA and performed by an FPGA in real time. Experimental results with the FPGA and a test board for simultaneous two-channel BSS and four-channel ANC at normal office environments demonstrate that the final SNRs reach about 16 dB, which is good enough for robust speech-recognition systems with an auditory model. In the future, the FPGA implementation of ICA-based speech-enhancement algorithm will be integrated into existing speech recognition chip, which consists of AD converters, auditory-based feature extractor, and RBF classifier. REFERENCES

[10] K. S. Cho and S. Y. Lee, “Implementation of infomax ICA .Algorithm with analog CMOS circuits,” in Proc. Int. Workshop Independent Component Analysis and Blind Signal Separation, San Diego, CA, Dec. 2001. [11] M. M. Cohen and G. Cauwenberghs, “Blind separation of linear convolutive mixtures through parallel stochastic optimization,” in Proc. IEEE Int. Symp. Circuits and Systems, vol. 3, 1998, pp. 17–20. [12] M. Stanacevic, M. Cohen, and G. Cauwenberghs, “Blind separation of linear convolutive mixtures using orthogonal filter banks,” in Proc. Int. Workshop Independent Component Analysis and Blind Signal Separation, San Diego, CA, Dec. 2001. [13] H. P. D. Xia, S. C. Douglas, and K. F. Smith, “A scalable VLSI architecture for multichannel blind deconvolution and source separation,” , 1998, pp. 297–306. [14] P. He, P. C. W. Sommen, and B. Yin, “A real-time DSP blind signal separation experimental system based on a new simplified mixing model,” in Proc. EUROCON’01 Int. Conf. Trends in Communications, vol. 2, Slovakia, 2002, pp. 467–470. [15] S. C. Douglas and T. H. Meng, “Stochastic gradient adaptation under general error criteria,” IEEE Trans. Signal Process., vol. 42, pp. 1335–1351, June 1994. [16] D. S. Kim, S. Y. Lee, and R. M. Kil, “Auditory processing of speech signals for robust speech recognition in real-world noisy environments,” IEEE Trans. Speech Audio Process., vol. 7, pp. 55–69, Jan. 1999. [17] C. M. Kim and S. Y. Lee, “A digital chip for robust speech recognition in noisy environment,” in Proc. IEEE Int. Conf. Acoustics, Speech, and Signal Processing, vol. 2, 2001, pp. 1089–1092.

Chang-Min Kim was born in Jeungdo, Korea, in 1975. He received the B.S. and M.S. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1998 and 2000, respectively. He is currently pursuing the Ph.D. degree in electrical engineering from KAIST. His research interests include both system and digital IC design for signal processing and microprocessor for speech recognition. His main topics of interest are the fast prototyping of digital systems

[1] B. Widrow et al., “Adaptive noise canceling: Principles and applications,” Proc. IEEE, vol. 63, pp. 1692–1716, 1975. [2] H. Haykin, Adaptive Filter Theory, 3rd ed. Englewood Cliffs, NJ: Prentice-Hall, 1996. [3] S. Amari, A. Cichocki, and Y. H. Yang, “A new learning algorithm for blind source separation,” in Advances in Neural Information processing Systems 8. Cambridge, MA: MIT Press, 1996, pp. 757–763. [4] A. J. Bell and T. J. Sejnowski, “An information-maximization approach to blind separation and blind deconvolution,” Neural Computation, vol. 7, pp. 1129–1159, 1995. and speech recognition. [5] T. W. Lee, A. J. Bell, and R. L. Lambert, “Blind separation of delayed and convolved sources,” in Advances in Neural Information Processing Systems 9. Cambridge, MA: MIT Press, 1997, pp. 758–764. [6] K. Torkkola, “Blind separation of convolved sources based on information maximization,” in Proc. IEEE Workshop Neural Networks for Hyung-Min Park received the B.S. and M.S. degrees Signal Processing, Kyoto, Japan, 1996, pp. 423–432. in electrical engineering from Korea Advanced Insti[7] H. M. Park, H. Y. Jeong, T. W. Lee, and S. Y. Lee, “Subband-based blind tute of Science and Technology (KAIST), Daejeon, signal separation for noisy speech recognition,” Electron. Lett., vol. 35, Korea, in 1997 and 1999, respectively. He is currently pp. 2011–2012, 1999. pursuing the Ph.D. degree in electrical engineering at [8] H. M. Park, S. H. Oh, and S. Y. Lee, “Adaptive noise canceling based on KAIST. independent component analysis,” Electron. Lett., vol. 38, pp. 832–833, His current research interests include the theory July 2002. and applications of independent component analysis, [9] M. H. Cohen and A. G. Andreou, “Current-mode subthreshold mos imblind signal separation, adaptive noise canceling, and plementation of Herault-Jutten autoadaptive network,” IEEE J. Solidnoise-robust speech recognition. www.cadfamily.com EMail:[email protected] State Circuits, vol. 27, pp. 714–727, May 1992.


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Taesu Kim was born in Gyeongsangnam-do, Korea, in 1978. He received the B.S. degree from Hanyang University, Seoul, Korea, in 2001 and the M.S. degree from Korea Advanced Institude of Science and Technology (KAIST), Daejeon, Korea, in 2003, both in electrical engineering. He is currently pursuing the Ph.D. in biosystems from KAIST. His research interests include biologically motivated information processing, independent component analysis, and noise-robust speech recognition. Recently, he has been involved with speech enhancement and feature extraction based on the information processing mechanism of human brain.

Yoon-Kyung Choi was born in Suwon, Korea, in 1967. He received the B.S. degree in 1990 from the Korea University, Seoul, Korea, and the M.S. and Ph.D. degrees from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1992 and 1996, respectively, all in electrical engineering. From 1997 to 2001, he was with the LG Semicon Co. Ltd., Seoul, Korea, and the Hynix Semiconductor Incorporated, Seoul, Korea, where he specialized in mixed-mode IC design. Since 2001, he has been with Extell Technology Co., Seoul, Korea, where he is engaged in the design of noise-robust speech recognition chips and adaptive acoustic signal processing algorithms.


Soo-Young Lee (S’81–M’83) received the B.S. and M.S. degrees from Seoul National University, Seoul, Korea, in 1975 and Korea Advanced Institute of Science (KAIST), Daejeon, Korea, in 1977, respectively, both in electronics. He received the Ph.D. degree from Polytechnic Institute of New York, Brooklyn, NY, in electrophysics in 1984. From 1982 to 1985, he was with General Physics Corporation, Columbia, MD, as a Staff and Senior Scientist. In early 1986, he joined the Department of Electrical Engineering, KAIST, where he is now is a Full Professor and Chairman for the newly established Department of BioSystems. In 1997, he established the Brain Science Research Center, which is the main research organization of the Korean Brain Neuroinformatics Research Program from 1998 to 2008. His research interests have included artificial auditory systems based on the biological information-processing mechanism in the brain. He has also developed an auditory model for noise-robust speech feature extraction, analog and digital chips for speech recognition and adaptive noise canceling, blind signal separation for speech enhancement, and top-down selective attention models for noisy and superimposed pattern recognition. Dr. Lee had served as the President of the Asia-Pacific Neural Network Assembly in 2001 and received the Leadership and Achievement awards from International Neural Network Society in 1994 and 2001, respectively. He is the Editor-in-Chief of a new journal, Neural Information Processing—Letters and Reviews.

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