Full custom layout design flow

Full Custom Layout Design Flow

指導教授: 董蘭榮 負責助教: 原祥富 上課日期: 2013/11/13

1

Outlines    

Schematic design with Composer Pre-simulation using Hspice Layout design with Virtuoso Layout verification with Calibre  Design Rule Check (DRC)  Layout Versus Schematic (LVS)  Layout Parasitic Extraction (PEX)

 Post-simulation using Hspice

2013/11/15

2

Announcements  Workstation: 140.113.146.24~27 & 34  Technology file: CIC 0.18um 1.8V/3.3V 1P6M Virtual Mixed Mode/RFCMOS Process  Tool    

Hspice - hspice_2012.06-SP2_linux CosmosScope - cosmos_scope_2010.03_linux Virtuoso - IC_51.41.151_linux Calibre - calibre_2012.2_26.20_linux32

2013/11/15

3

Full Custom Layout Design Flow Specification

Circuit Design tool: Schematic Pre-Simulation tool: Hspice Layout Design tool: Virtuoso or Laker Design Rule Check (DRC) tool: Calibre Layout Versus Schematic (LVS) tool: Calibre Layout Parasitic Extraction (PEX) tool: Calibre Post-Simulation tool: Hspice

2013/11/15

Tapeout

4

Technology Files Hspice Virtuoso DRC LVS PEX

2013/11/15

cic018.l display.drf cic18.tf rule.drc Rule.lvs Rule.rce Rule_08KA.rc Rule_20KA.rc

5

Prepare Files      

Type: “cp /usr2/ce21/student/u97/u9712525/.tcshrc . ” Type: “cp /usr2/ce21/student/u97/u9712525/.cdsinit . ” Type: “cp /usr2/ce21/student/u97/u9712525/calibre.cshrc . ” Type: “source .tcshrc ” Type: “source calibre.cshrc” Type: “cp /usr2/ce21/student/u97/u9712525/test/CadenceVirtuoso . ”  Type: “./CadenceVirtuoso” ( to create the symbolic link of the technology files )

2013/11/15

6

Cadence Virtuoso 2.

 Command: icfb &

1.

Ignore this error

2013/11/15

7

Create a New Library (1)  Tools  Library manager

3.

2.

1.

2013/11/15

8

Create a New Library (2)  File  New  Library 2.

1.

New a library name

3.

The path of this new library

Press ok to build up

2013/11/15

9

Setup the Technology File  Browse  cic18.tf (CIC technology file) 1.

2.

3.

2013/11/15

10

Loaded Successfully  You must place the “ cic18.tf ” in the same directory where you execute the command “ icfb & ”, or the complete path must be given.

2013/11/15

11

Start to Schematic Work  Library manager  select the library name you just created, ex “VLSI” in this example.  File  New  Cell View 2.

1.

your library name

3.

2013/11/15

Type cell name Composer-Schematic for design your ckt

12

Schematic Window Check and Save Save

Add instance

Hot Key

Wire

Add Pin

2013/11/15

13

Add Instance: NMOS 1.

2.

Library: analogLib Cell: nmos4 View: symbol

3. Model name: n_18 Width: Length:

4.

Modify the parameter of the component: click and choose the component, and press Q to modify. 2013/11/15

14

Add Instance: PMOS 1.

2. 3.

Library: analogLib Cell: pmos4 View: symbol

4.

Model name: p_18 Width: Length:

2013/11/15

15

Add Instance: VCC 1.

3. 2.

2013/11/15

16

Add Instance: GND

1.

2.

3.

2013/11/15

17

Add Pin

1. Choose the type of the pin

2.

2013/11/15

18

Example: Inverter Remember to Check and Save

You need to make sure no error in the schematic.

2013/11/15

19

Export the sp file  File  Export  CDL

1.

3.

Browse the schematic file

2.

Type your sp ffile name

4. 2013/11/15

20

The sp file The path you save the (name).sp

2013/11/15

21

File Modification for LVS Title

Add “*” berfore “.PARAM”

LVS will burst out many errors if you don’t modify this file!! Modification: 1. MM1  M1 2. MM0  M0 3. PM  p_18 4. NM  n_18 2013/11/15

The (name).sp file will be used later in LVS!!

22

Pre-Simulation

2013/11/15

Notice: 1. The technology file changes to “cic018.l”. 2. Model name for NMOS: n_18 3. Model name for PMOS: p_18

23

Example Code

2013/11/15

24

HSPICE Simulation Commands hspice -i path/input_fi: Name of the input netlistfile. If you do not enter an extension, HSPICEassumes .sp. -o path/output_file: Name of the output file. If you do not specify an extension, HSPICEassigns .lis.

2013/11/15

25

HSPICE Simulation Commands Examples hspice -i demo.sp demo is the root input file name. Without the -o argument and without redirection, HSPICE does not generate an output listing file. hspice -i demo.sp -o demo demo is the output file root name (designated with the -o option). Output files are named demo.lis, demo.tr0, demo.st0, and demo.ic0. hspice demo.sp -n 7 > demo.out This command redirects output to a file instead of stdout. demo.sp is the input netlist file. The .sp extension is optional. The -n 7 starts the output data file revision numbers at 7; for example: demo.tr7, demo.ac7, demo.sw7, and so forth. The > redirects the program output listing to file demo.out.

2013/11/15

26

CosmosScope  scope &

2013/11/15

27

Start to Layout Work  Tools  Library manager  select the library name you just created, ex “VLSI” in this example.  File  New  Cell View 1.

2.

2013/11/15

Choose Virtuoso for layout cell view

28

Layout Work Windows  LSW: Choose the material for your layout  Layout plane: A design platform with P-substrate in default

2013/11/15

29

Hot Key for Layout Design

2013/11/15

R

Rectangle

shift + Z

Zoom in

K

Create ruler

ctrl + Z

Zoom out

S

Sketch

shift + K

Clear all rulers

F

Fit all

Esc

Cancel

C

Copy

Delete

Delete

M

Move

ctrl + P

Add pins

Mouse

left button to choose , right botton to zoom in

30

Display Options

Adjust the snap spacing to 0.01um, so that you can draw the minimum length 0.18um.

2013/11/15

31

Inverter Layout

vcc

Nwell PMOS

PIMP DIFF

in

out

PO1 ME1

NMOS

gnd

NIMP M1_TEXT CONT

2013/11/15

32

Calibre – DRC (1)  Calibre  Run DRC

2013/11/15

DRC starts here!!

33

Calibre – DRC (2)

Cancel

2013/11/15

34

Calibre – DRC (3)  Rule  …  select “rule.drc”  ok

2.

1.

3.

4.

2013/11/15

35

Calibre – DRC (4) DRC file is ready.

2013/11/15

36

Calibre – DRC (5)  Input page  Don’t change anything!!

Your layout file

Cell name

2013/11/15

37

Calibre – DRC (6)  Output page - Don’t change anything!!  Start to run DRC

1.

2.

2013/11/15

38

Calibre – DRC (7)  Summary report  You should need to make sure no any DRC errors before going to LVS.

No error!!

2013/11/15

39

Calibre – DRC (8)  Error: the two PIMP regions are too close!!  The minimum space between two PIMP region is 0.45um.

You can highlight the error. error!!

2013/11/15

40

Calibre – LVS (1)  Calibre  Run LVS LVS starts here!!

2013/11/15

41

Calibre – LVS (2)

Cancel

2013/11/15

42

Calibre – LVS (3)  Rule  …  select “Rule.lvs”  ok

2.

1.

3.

4.

2013/11/15

43

Calibre – LVS (4) LVS file is ready.

2013/11/15

44

Calibre – LVS (5)  Input page  Compare Layout vs. Netlist

Your layout file

The sp file produced from the schematic. Netlist extracted from layout

2013/11/15

45

Calibre – LVS (6)  Output page - Don’t change anything!!  Start to run LVS

1. 2.

2013/11/15

46

Calibre – LVS (7)  LVS pass!!

2013/11/15

47

Calibre – PEX (1)  Calibre  Run PEX PEX starts here!!

2013/11/15

48

Calibre – PEX (2)  Rules  …  Rule.rce  ok

2.

1.

3.

4.

2013/11/15

49

Calibre – PEX (3)

2013/11/15

50

Calibre – PEX (4)  Input page

The sp file produced from the schematic.

2013/11/15

51

Calibre – PEX (5)  Output page  Netlist:  Extraction type: R+C  Format: HSPICE  Names: LAYOUT

 Nets:

1.

 All Nets 2.

2013/11/15

52

Calibre – PEX (6)  Output Result:  INV.pex.netlist  INV.pex.netlist.INV.pxi  INV.pex.netlist.pex

 Netlist with the parasitic RC

2013/11/15

53

Post-Simulation

Post-simulation

2013/11/15

54

Simulation Results

Pre-sim result

2013/11/15

Post-sim result

55

Thank you

2013/11/15

56