FULLY PROGRAMMABLE UNIVERSAL FILTER WITH

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Journal of Circuits, Systems, and Computers Vol. 18, No. 5 (2009) 875–897 c World Scientific Publishing Company

J CIRCUIT SYST COMP 2009.18:875-897. Downloaded from www.worldscientific.com by UNIVERSITY OF GUELPH on 02/06/15. For personal use only.

FULLY PROGRAMMABLE UNIVERSAL FILTER WITH INDEPENDENT GAIN-ω0 -Q CONTROL BASED ON NEW DIGITALLY PROGRAMMABLE CMOS CCII

TAREK M. HASSAN∗ and SOLIMAN A. MAHMOUD† Electrical Engineering and Electronics Department, German University in Cairo (GUC), New Cairo City-Main Entrance Al Tagamoa Al Khames, Cairo, 11835, Egypt ∗[email protected] †[email protected] Revised 12 February 2009 A fully programmable second-order universal filter with independently controllable characteristics is presented in this paper. The proposed filter is based on a new ± 0.75 V second-generation current conveyor with digitally programmable current gain. The input stage of the current conveyor is realized using two complementary MOS differential pairs to ensure rail-to-rail operation. The output stage consists of a Class-AB CMOS push-pull network, which guarantees high current driving capability with a 47.2 µA standby current. The digital programmability of the current conveyor, based on transistor arrays and MOS switches, provides variable current gain using a digital code-word. Two approaches for implementing current conveyors with programmable current gain either greater or less than one are described. The fully programmable universal filter and the proposed digitally programmable current conveyor circuits are simulated using PSPICE with 0.25 µm CMOS technology from MOSIS. Keywords: Current conveyor; digital programming; current summing network; variable current gain; code-word; universal filter.

1. Introduction Digital programming of analog blocks has gained overwhelming attraction in recent years. Its popularity stems from the rich useful applications that can be realized using analog blocks with programmable characteristics. Common applications encompass tunable filters, variable gain amplifiers and field programmable arrays.1 Although analog programming is sometimes used in certain applications, the limitation on the allowable range of the analog tuning voltage makes it inconvenient for low-voltage applications. Hence, in these applications, the digital control is more attractive.2 The second-generation current conveyor (CCII) is one of the most functionally flexible and versatile analog blocks.3 Since its first introduction by Sedra and Smith in 1970,4 several circuit realizations have been proposed for its implementation.5–10 875

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Fig. 1.


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Block representation of the CCII.

It has been used in a wide range of applications, e.g., in high frequency analog signal applications, like filters,11, 12 and in current-mode oscillators.13 Basically, a CCII is a three-terminal device (Fig. 1), whose properties are governed by the following matrix equation:      0 0 0 VY IY VX  = 1 (1) 0 0  IX  . IZ VZ 0 ±1 0 While the X-terminal voltage is following the voltage at terminal Y , a current injected at the X-terminal is being replicated to the Z-terminal. An ideal CCII exhibits infinite resistance at terminals Y and Z, and zero resistance at terminal X. The flow direction of the output current with respect to the input current defines two types of current conveyors; positive CCII (or CCII+) with both currents either flowing into or out of the device, and negative CCII (or CCII−) having opposite current flow directions. Basically, a CCII− can be derived from a CCII+ by using current mirrors to invert the output current direction, and vice versa. In this paper a new fully programmable second-order universal filter with independently controllable characteristics (gain, ω0 , and Q) is proposed. The filter is based on a new low-voltage low-power CMOS CCII with digitally programmable current gain. The digitally programmable second-generation current conveyor (DPCCII) is a four-terminal device that employs a digital code-word to provide variable current transfer gain between the X- and Z-terminals, while maintaining all other characteristics of a traditional CCII. The proposed low-voltage DPCCII is operating under a supply voltage of ± 0.75 V with a 154 µW standby power dissipation. The input stage is realized using two complementary MOS differential pairs to ensure rail-to-rail operation. The output stage consists of a ClassAB push-pull network, which guarantees high current driving capability and low standby current. Depending on the internal structure of the DPCCII, it can provide current gains either greater or less than one, denoted by symbols K or K −1 respectively (Fig. 2). These two DPCCII structures are used as the main building blocks for the proposed fully programmable universal filter. This paper is organized as follows: In Sec. 2 a complete analysis for the proposed second-order fully programmable universal filter is given. Section 3 provides new CMOS realizations for the two proposed DPCCII structures with current gains either greater or less than one. Finally in Sec. 4 all proposed circuits are verified using PSPICE simulations with 0.25 µm TSMC CMOS technology.

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Fully Programmable Universal Filter with Independent Gain-ω0 -Q Control


Fig. 2(a).

Fig. 2(b).

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Block representation of the DPCCII with gain K.

Block representation of the DPCCII with gain K −1 .

2. Proposed Fully Programmable Universal Filter The proposed fully programmable universal filter is deduced from a second-order universal filter introduced in Ref. 12, where five CCII blocks, two grounded capacitors, and six grounded resistors were combined in a unique configuration that, depending on the polarity of the used CCII blocks, provided inverting and noninverting low-pass (LP), band-pass (BP) and high-pass (HP) output responses. The characteristics of the output responses (gain, ω0 , and Q) were defined through the values of the resistors and capacitors. In the proposed fully programmable filter, however, all the CCII blocks are replaced with their DPCCII counterparts. This modification provides great flexibility for changing the filter characteristics without changing the resistors and capacitors values. In the following subsections, two filter configurations are suggested employing different combinations of the DPCCII blocks. The first configuration (Fig. 3(a)) is most suitable for high- and low-pass filters, while the second configuration (Fig. 3(b)) provides a band-pass filter with independently controllable characteristics. In both configurations the first DPCCII block is operating as a summer, the second and third blocks are integrators, and the last two are voltage to current converters, with their currents fed back to the X-terminal of the first DPCCII block. Both configurations provide several advantages over the typical active filters with current conveyors. They have infinite input and output impedances while all

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Fig. 3(a).

Fig. 3(b).

First realization of the universal filter using DPCCII blocks.

Second realization of the universal filter using DPCCII blocks.

elements are grounded. In addition, the characteristics of the filter including ω0 , Q, and gain can be adjusted independently. Moreover, the numerous possible combinations of the K and K −1 DPCCII blocks can generate universal filters with versatile programmable characteristics.

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2.1. HP-LP filter configuration As stated before, the filter configuration presented in Fig. 3(a) creates a universal filter, where all HP and LP characteristics can be independently controlled. By direct analysis, the following transfer functions and gains are obtained: S 2 KRiiR vHP , = vi D(S)


vLP = vi

Ki K1 R K2 C1 C2 R1 R2 Ri

D(S)

(2) ,

S Ki K1 R vBP = C1 R1 Ri , vi D(S) D(S) = S 2 + S

Ki K1 R Ki K1 R + , K4 C1 R1 R4 K2 K3 C1 C2 R1 R2 R3

(3)

(4) (5)

AvHP =

Ki R , Ri

(6)

AvLP =

K3 R3 , Ri

(7)

AvBP =

K4 R4 . Ri

(8)

From Eq. (5), ω0 and Q of the filter are given by: Ki K1 R ω0 = , K2 K3 C1 C2 R1 R2 R3 C1 R1 . Q = K4 R4 Ki K1 K2 K3 C2 R2 R3 R

(9) (10)

If all resistances and capacitances are taken equal, which is an advantage of this configuration, the gains, ω0 , and Q are simplified to: AvHP = Ki ,

AvLP = K3 , AvBP = K4 , Ki K1 1 ω0 = , RC K2 K3 K42 Q= . Ki K1 K2 K3

(11) (12)

(13)

On the one hand, the gains of the HP and LP filters can be programmed by varying parameters Ki and K3 , respectively, whereas they should be equally adjusted for compensating the variations in to keep same ω0 . Parameter K4 is responsible √ Ki and K3 in order to maintain Q at 1/ 2, which is required for a maximally flat

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response. This value of Q can be achieved simply by setting either K1 or K2 to a value of two. On the other hand, ω0 of the universal filter can be programmed independently, increasingly or decreasingly, via parameters K1 and K2 . In both cases Parameter for compensating the variations in K1 and K2 in order to maintain K4 is responsible √ Q at 1/ 2. Besides, parameters Ki and K3 are fixed at the required gain values of HP and LP filters respectively.


2.2. BP filter configuration The filter configuration presented in Fig. 3(b) creates a universal filter, where all the band-pass characteristics can be independently controlled. By direct analysis, the following transfer functions and gains are obtained: S Ki R vBP = K1 C1 R1 Ri , vi D(S)

(14)

S 2 KRiiR vHP , = vi D(S)

(15)

vLP = vi D(S) = S 2 + S

Ki K2 R K1 C1 C2 R1 R2 Ri

D(S)

,

Ki R Ki K2 R + , K1 K4 C1 R1 R4 K1 K3 C1 C2 R1 R2 R3 K4 R4 , Ri Ki R = , Ri

(16) (17)

AvBP =

(18)

AvHP

(19)

AvLP =

K3 R3 . Ri

From Eq. (17), ω0 and Q of the filter are given by: Ki K2 R ω0 = , K1 K3 C1 C2 R1 R2 R3 K1 K2 C1 R1 . Q = K4 R4 Ki K3 C2 R2 R3 R

(20)

(21) (22)

Taking all resistances and capacitances equal, the gains, ω0 and Q are simplified to: AvBP = K4 ,

AvHP = Ki , AvLP = K3 , Ki K2 1 , ω0 = RC K1 K3 K1 K2 K42 . Q= Ki K3

(23) (24)

(25)

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From the previous equations, the gain of the BPF is depending on K4 . Hence, if it is required to vary the gain while conserving the value of Q, then Ki and K3 should be programmed to the value of K4 . This also ensures that ω0 remains unchanged. In this case, ω0 and Q are defined through the value of R, C, K1 , and K2 . Next, in order to increase or decrease ω0 , the two parameter pairs Ki , K2 and K1 , K3 are programmed. However, maintaining the value of Q requires the parameters belonging to one pair to have the same value. In this case, parameter K4 is responsible for the required gain and Q of the BP filter, while the initial value of ω0 is depending on RC. Finally, if Q should be programmed for a constant gain, then the two parameter pairs Ki , K3 and K1 , K2 are involved. Here again, preserving ω0 requires the parameters belonging to one pair to comprise the same value. It should be noted that K4 sets the required gain and initial Q value, while the value of RC defines ω0 . 3. Proposed DPCCII CMOS Circuit Realization In this section the two different DPCCII blocks employed in the fully programmable universal filter are realized using CMOS technology. The first realization provides gains greater and equal to one (gain K), while the second realization presents a DPCCII with gains less and equal to one (gain K −1 ). Both realizations evolve from a novel CCII circuit realization, which is shown in Fig. 4. The new CCII employs an N-MOS matched differential pair (M1, M2) and another P-MOS matched differential pair (M8, M9), for implementing the voltage follower between the Y - and X-terminals. Transistors (M7, M14) provide the necessary biasing currents for each

Fig. 4.

CMOS realization of the proposed CCII+ circuit.

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differential pair separately. Besides, the current mirroring for the N and P pairs is achieved via the two matched current mirror pairs (M3, M4) and (M10, M11) in sequence. In addition, (M5, M12) comprise a Class-AB output stage, providing current swings up to ± 1 mA and standby currents in the vicinity of 47 µA. Furthermore, the current at the X-terminal is transferred to the Z-terminal with the aid of (M6, M13), which must be for a unity current gain matched with (M5, M12) respectively. All transistors are assumed to be operating in saturation. Ideally, when a positive voltage is applied at the Y -terminal, only the N-MOS differential pair along with (M5, M6) will be involved for providing the necessary following actions. The same applies for a current coming out from the X-terminal that is replicated to the Z-terminal. On the other hand, if a negative voltage is applied at the Y -terminal or a current is injected to the X-terminal, the P-MOS differential pair along with (M12, M13) will be the ones responsible for providing the necessary following actions. In the following subsection the DPCCII with current gain K is described. Thereafter, the DPCCII with current gain K −1 is presented. 3.1. DPCCII with current gain K The properties of the DPCCII with current gain K can be described by the following matrix equation:      IY 0 0 0 VY VX  = 1 0 0  IX  . (26) IZ VZ 0 K 0 The basic design idea of the proposed DPCCII is to control the current transfer gain parameter K by replacing the Z-terminal transistors of the recently presented CCII with transistor arrays associated with switches (Fig. 5). The gain parameter K can take values from 1 to (2n − 1), where n represents the number of transistor arrays. The concept of using transistor arrays was introduced in Ref. 1 to control the transconductance of basic transistors in a digitally controlled balanced output transconductor. It has been modified here to implement a current summing network (CSN) at the Z-terminal. The CSN consists of n transistor pairs, whose N-MOS aspect ratios are given by: W W i =2 i = {0, 1, . . . , n − 1} . (27) L Ni L 15 The same applies for the P-MOS array, where the aspect ratios follow the equation: W W i =2 i = {0, 1, . . . , n − 1} . (28) L Pi L 5 Consequently, the current at the Z-terminal, if flowing out the DPCCII block, can be expressed by: IZ =

n−1 i=0

ai 2i (IM5 − IM15 ) .

(29)

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Fig. 5.

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CMOS realization of the DPCCII with gain K.

Therefore, the proposed DPCCII provides a current transfer gain equal to: n−1 IZ = ai 2 i . IX i=0

(30)

Parameter ai represents the digital code-bit applied to the ith branch in the CSN. It is responsible for enabling and disabling the current flowing in that particular branch. 3.2. DPCCII+ with current gain K −1 The design idea described in the previous subsection can be similarly employed to implement a DPCCII with current gain less than one. However, the transistor arrays are placed on the X-terminal, moving the CSN to the input side (Fig. 6). Besides, the Z-terminal gets only a replica of the smallest current in the array. As previously discussed, the CSN consists of n transistor pairs with same aspect ratios described in Eqs. (27) and (28). The current at the X-terminal, flowing out the DPCCII block, is therefore given by: IX =

n−1 i=0

ai 2i (IM5 − IM15 ) .

(31)

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Fig. 6.

CMOS realization of the DPCCII with gain K −1 .

As a consequence, the DPCCII provides a current transfer gain equal to: IZ 1 = n−1 . i IX i=0 ai 2

(32)

Here again, parameter ai is responsible for enabling and disabling the current flowing in the ith branch of the CSN. Since the current fed to the X-terminal is always K times greater than the current received at the Z-terminal. The matrix equation can be expressed by:   0 IY VX  = 1 IZ 0 

0 0 K −1

  0 VY 0  IX  . 0

(33)

VZ

The parameter K can still take value from 1 to (2n − 1), where n is the number of transistor arrays.

4. Simulation Results The performance of the fully programmable universal filter and the proposed digitally programmable current conveyor circuits were verified by performing PSPICE simulations with supply voltages ± 0.75 V using 0.25 µm TSMC CMOS technology. First of all, the performance of the CCII+ (Fig. 4) is simulated using the parameters and aspect ratios given in Table 1.

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Table 1(a). Transistor aspect ratios for the proposed CCII and the DPCCII with gain K. Transistors

W (µm)

L (µm)

M1–M2 M3–M4 M5–M6 M7 M8–M9 M10–M11 M12–M13 M14

5 0.5 25 0.5 5 0.5 25 0.5

0.25 0.5 0.25 0.25 0.25 0.5 0.25 0.25

Table 1(b). Biasing voltages for the proposed CCII+ and the DPCCII with gain K.

Fig. 7.

Biasing source

Value

VB1 VB2

− 219 mV 105 mV

The X- and Z-terminal output voltage versus changes of VY .

As shown in (Fig. 7), the voltage following actions of the CCII+ exhibit a nearly rail-to-rail voltage transfer between the input and output terminals. The linearity range extends from − 0.62 V to 0.65 V. Moreover, the CCII+ shows acceptable linearity, when used to realize an amplifier with gain two (Fig. 8). In addition, plotting the magnitude of the voltage transfer gain at different frequencies (Fig. 9), with an open-circuited Z-terminal, clarifies that the CCII+ has a flat response with an 86.3 MHz bandwidth. The input and output referred noise spectral densities are also evaluated (Fig. 10), showing a noise voltage in the √ vicinity of 44 nV/ Hz. The current following action between the X- and Z-terminals is thereafter simulated (Fig. 11) demonstrating a high linearity range of ± 1 mA. The variation of the

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Fig. 8.

The voltage swings VZ and VX of the CCII+ based amplifier with gain two.

Fig. 9.

Magnitude frequency response of the voltage transfer gain.

Fig. 10.

The input and output referred noise spectral densities.

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Fig. 11.

Fig. 12.

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The Z-terminal output current versus changes of IX .

The offset voltage of the X-terminal along with its derivative.

offset voltage across the X-terminal with grounded VY is also illustrated (Fig. 12), showing an offset voltage less than 16 mV while the X-terminal input resistance does not exceed 32 Ω. Furthermore, the push-pull action of the class-AB output stage is verified (Fig. 13) having a standby current of 47.2 µA. Moreover, plotting the magnitude of the current transfer gain at different frequencies (Fig. 14), with a short-circuited Z-terminal, reveals that the CCII+ has an approximately flat response with a high bandwidth of 580 MHz. Verifying the overall stability and linearity of the CCII+, the transient response is examined for a 1 MHz square wave input voltage (Fig. 15), and the total harmonic distortion is evaluated for different input voltage amplitudes (Fig. 16), respectively. Obviously, the CCII+ shows a smooth transition with rise and fall times in the vicinity of 6.9 ns, while the THD of a 1 MHz sinusoidal input is less than 1.2%. In addition, the power supply rejection-ratio (PSRR) from the positive supply to the output has a value of 64.01 dB and from the negative supply to the output is 89.95 dB (Table 2).

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Fig. 13.

Fig. 14.

Driving capabilities of the output stage.

Magnitude frequency response of the current transfer gain.

Fig. 15.

The X-terminal step response of the CCII+.

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Fig. 16.

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Total harmonic distortion of the X-terminal (for input frequencies 100 KHz and 1 MHz).

Table 2.

Performance analysis of the proposed CCII.

Parameters

Proposed CCII+

CCII+ in Ref. 3

CCII+ in Ref. 7

CMOS technology Power supply (VDD , VSS ) No. of transistors Total power dissipation Standby current of the output stage (ISB ) PSRR+ PSRR− Voltage dynamic range Voltage transfer gain AV Current driving capability Current transfer gain AI VXoff while Y and Z are grounded Rx while Y and Z are grounded The X-terminal open circuit B.W The Z-terminal short circuit B.W The open circuit X-terminal THD @ VY = 0.5∗ sin(2πf) Rise time/fall time

0.25 µm 0.75 V, − 0.75 V

0.35 µm 0.75 V, − 0.75 V

0.35 µm 0.75 V, − 0.75 V

14 0.154 mW 47.2 µA

22 0.213 mW N.A.

24 0.26 mW N.A.

64.01 dB 89.95 dB ± 0.65 V at 10 kΩ 0.0057 dB

N.A. N.A. ± 0.65 V at 0.5 kΩ − 0.012 dB

N.A. N.A. ± 0.5 V at 0.5 kΩ − 0.02 dB

− 1 mA, + 1 mA

− 1 mA, + 1 mA

− 1 mA, + 0.8 mA

− 0.011 dB

− 0.037 dB

− 0.06 dB

< 16 mV for ± 1 mA

< 2.5 mV for ± 0.5 mA

< 1.5 mV for ± 0.8 mA

< 32 Ω for ± 1 mA

< 7 Ω for ± 0.5 mA

< 150 Ω for ± 0.8 mA

86.3 MHz

10.5 MHz

2.4 MHz

580 MHz

6.2 MHz

3 MHz

− 39 dB @ 1 MHz

− 53 dB @ 1 kHz

− 50 dB @ 1 kHz

6.9 ns/6.6 ns

< 2 µs % settling time

< 2 µs 1% settling time

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In order to emphasize the potentiality of the proposed CCII+ architecture, its performance is compared with two recent CCII+ architectures as reported in Refs. 3 and 7. Table 2 shows that the proposed circuit is exhibiting comparable performance regarding dynamic range, transfer gain, and offset voltage, while demonstrating overweighed superiority in terms of bandwidth, transistor count, and power consumption. In the second simulation set, the performance of the two different DPCCII circuits with a three-branch CSN is evaluated. The DC and AC current transfer gains are examined at all possible combinations of the digital code-word excluding zero. The simulated responses of the DPCCII with gain K (Fig. 5) show acceptable linearity for an input range that extends from − 150 µA to + 150 µA (Fig. 17(a)), while the AC gain exhibits constant bandwidth of 162 MHz (Fig. 17(b)).

Fig. 17(a).

The Z-terminal output current of the DPCCII with gain K for K = 1 − 7.

Fig. 17(b).

Magnitude frequency response of the DPCCII with gain K for K = 1 − 7.

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Fig. 18(a).

The Z-terminal output current of the DPCCII with gain K −1 for K = 1 − 7.

Fig. 18(b).

Magnitude frequency response of the DPCCII with gain K −1 for K = 1 − 7.

Similarly, the simulated responses of the DPCCII with gain K −1 (Fig. 6) demonstrate an acceptable linearity for an input range of − 1 mA to + 1 mA (Fig. 18(a)), while the AC gain exhibits almost a constant bandwidth (Fig. 18(b)). The aspect ratios for the DPCCII with gain K −1 were optimized as given in Table 3. The last set of simulations verifies the operation and programmability of the second-order fully programmable universal filter. The two proposed filter structures (Figs. 3(a) and 3(b)) are simulated using the DPCCII circuits described previously. The responses of the second-order HP and LP filters (Fig. 3(a)) with the digital code-word combinations given in Table 4 are shown in (Fig. 19). Different gains are accurately achieved at a constant cut-off frequency of 100 KHz (Figs. 19(a) and 19(c)). Moreover, the cut-off frequency is programmed separately — at a unity

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Table 3(a). Transistor aspect ratios for the DPCCII with gain K −1 . Transistors

W (µm)

L (µm)

M1–M2 M3–M4 M5–M6 M9 M11–M12 M13–M14 M15–M16 M19

0.5 0.5 75 15 0.5 0.5 75 15

0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25

Table 3(b). Biasing voltages for the DPCCII with gain K −1 . Biasing source

Value

VB1 VB2

− 217 mV 141 mV

Table 4(a).

Programming matrix of the HP filter.

HPF tuning element Gain from 1–7 Doubled cut-off frequency Halved cut-off frequency

Table 4(b).

a

b

c

d

e

001–111 001 001

001 100 001

010 001 100

001–111 010 010

001–111 010 010

Programming matrix of the LP filter.

LPF tuning element Gain from 1–7 Doubled cut-off frequency Halved cut-off frequency

a

b

c

d

e

001–111 010 010

001 100 001

010 001 100

001–111 001 001

001–111 010 010

gain — to its doubled and halved values (Figs. 19(b) and 19(d)). The simulation parameters and transistor aspect ratios were optimized for R = 1 kΩ, and C = 1.12 nf. Besides, the linearity of the proposed tunable LP filters is evaluated by calculating the in-band third order intercept point (IIP3). Two in-band sinusoidal signals of frequencies 30 KHz and 45 KHz are applied to the filter. The intermodulation distortion (IM3) is evaluated for various amplitudes. The results are then plotted and a third order intercept point (IIP3) of 28 dBm is obtained (Fig. 20). Finally, the response of the second-order BPF (Fig. 3(b)) is verified using the digital code-word combinations given in Table 5. The BPF was programmed to provide accurate gain values from 1 to 7 at f0 = 390 KHz and Q = 7 (Fig. 21(a)). Thereafter, the value of Q was scanned from 7 to

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Fig. 19(a).

Programmable voltage gain of the HP filter for gains 1–7 [dB].

Fig. 19(b).

Fig. 19(c).

Programmable cut-off frequency of the HP filter [Hz].

Programmable voltage gain of the LP filter for gains 1–7 [dB].

893

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Fig. 19(d).

Programmable cut-off frequency of the LP filter [Hz].

Fig. 20.

The IIP3 of the proposed tunable LP filter.

49 (in steps of 7) at constant f0 = 390 KHz and gain = 7 (Fig. 21(b)). Finally, at a constant gain = 7 and Q = 7, the center frequency was moved to 1/3f0, 1/2f0, f0 , 2f0 , and 3f0 (Fig. 21(c)), where f0 = 390 KHz. The simulation parameters and transistor aspect ratios were optimized for R = 1 kΩ, and C = 0.4 nf.

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Fully Programmable Universal Filter with Independent Gain-ω0 -Q Control Table 5.

Programming matrix of the BP filter.

BPF tuning element


Gain from 1–7 Q from 7–49 (in steps of 7) Center frequency ω0 , 2ω0 , 3ω0 Center frequency ω0 , 1/2ω0 , 1/3ω0

Fig. 21(a).

Fig. 21(b).

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a

b

c

d

e

001–111 001 001–011 001

111 001–111 001 001–011

111 001–111 001–011 001

001–111 001 001 001–011

001–111 111 111 111

Programmable voltage gain of the BP filter for gains 1–7 [dB].

Programmable quality factor of the BP filter for Q 7–49 (in steps of 7).

5. Conclusion In this paper, a second-order fully programmable universal filter based on novel ± 0.75 V CMOS digitally programmable current conveyors has been presented. Two filter structures have been proposed, the first for maximally flat LP and HP

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Fig. 21(c).

Programmable cut-off frequency of the BP filter [Hz].

responses with independently controllable gain and cut-off frequency, while the other proved itself suitable for a BP response with independently programmable ω0 , gain, and Q. Owing to its digital programmability, this filter can find application in many of today’s mixed analog/digital VLSI systems, in which the predominant channel is digital in nature. The use of merely grounded passive elements makes this filter furthermore attractive for simple IC layout and processing. The proposed fully programmable filter and its based DPCCII circuits have been verified using PSPICE simulations. The response of the filter has been evaluated for different programming values, which were achieved via the code-word combinations applied to the DPCCII blocks. The DPCCII itself has exhibited digital controllable current gain with the aid of a current summing network. It is worth mentioning that the aspect ratios used in all proposed CMOS circuits are of minimum size. While these aspects ratios can be scaled up in order to reduce mismatching effects, the impact on the frequency response of the overall circuit should be kept into consideration. In fact, the trade off between the mismatching effect and the frequency response sets an upper limit for such scaling. References 1. S. A. Mahmoud, Digitally controlled CMOS balanced output transconductor and application to variable gain amplifier and GM-C filter on field programmable analog array, J. Circuits Syst. Comput. 14 (2005) 667–684. 2. S. H. Mahmoud, M. A. Hashiesh and A. M. Soliman, Low-voltage digitally controlled fully differential current conveyor, IEEE Trans. Circuit Syst. I 52 (2005) 2055–2064. 3. A. H. Madian, S. A. Mahmoud and A. M. Soliman, New 1.5-V CMOS second generation current conveyor based on wide range transconductor, Analog Integr. Circuits Signal Process. 49 (2006) 267–279. 4. A. Sedra and K. Smith, A second-generation current conveyor and its applications, IEEE Trans. Circuit Theory CT-17 (1970) 132–134.

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FULLY PROGRAMMABLE UNIVERSAL FILTER WITH

FULLY PROGRAMMABLE UNIVERSAL FILTER WITH

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