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Functionally Complete Boolean Logic in 1T1R Resistive Random Access Memory Zhuo-Rui Wang, Yu-Ting Su, Yi Li, Ya-Xiong Zhou, Tian-Jian Chu, Kuan-Chang Chang, Ting-Chang Chang, Senior Member, IEEE , Tsung-Ming Tsai, Simon M. Sze, Life Fellow, IEEE , and Xiang-Shui Miao Abstract — Nonvolatile stateful logic through RRAM is a promising route to build in-memory computing architecture. In this letter, a logic methodology based on 1T1R structure has been proposed to implement functionally complete Boolean logics. Arbitrary logic functions could be realized in two steps: initialization and writing. An additional read step is required to read out the logic result, which is in situ stored in the nonvolatile resistive state of the memory. Cascade problem in building larger logic circuits is also discussed. Our 1T1R logic device and operation method could be beneficial for massive integration and practical application of RRAM-based logic. Index Terms — 1T1R RRAM, Boolean logics, nonvolatile, logic in memory.
I. I NTRODUCTION RADITIONAL von Neumann architecture is now facing two severe challenges. One is the data-transfer bottleneck due to the separation of computing and storage units and the performance mismatch between the two. The other is the Moore’s law which is approaching the physical limit with CMOS logic devices [1]. Resistive random access memory (RRAM), ascribing its capability of in-memory computing, has attracted extensive attention as a potential candidate for the non-von Neumann computing device [2]–[4]. It performs logic functions and in situ stores the results in a nonvolatile manner. In this way, the first challenge of high throughput communication between computing and storage units is circumvented. Moreover, the RRAM shows the prospect of extending the life of Moore’s law by its excellent scalability,
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Manuscript received December 14, 2016; accepted December 22, 2016. Date of publication December 28, 2016; date of current version January 24, 2017. This work was supported in part by the National Natural Science Foundation of China under Grant 61674061 and Grant 61504045 and in part by the National Key Research and Development Plan of MOST of China under Grant 2016YFA0203800. The review of this letter was arranged by Editor B. Govoreanu. (ZhuoRui Wang, Yu-Ting Su, and Y. Li contributed equally to this work.) Z.-R. Wang, Y. Li, Y.-X. Zhou, and X.-S. Miao are with the Wuhan National Laboratory for Optoelectronics, and School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, China (e-mail:
[email protected]). Y.-T. Su and T.-C. Chang are with the Department of Physics, National Sun Yat-Sen University, Kaohsiung 80424, Tawan (e-mail:
[email protected]). T.-J. Chu, K.-C. Chang, and T.-M. Tsai are with the Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan. S. M. Sze is with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2016.2645946
sub-ns operation speed, ultra-low power consumption, high endurance and potential of 3D integration [3], [5]. On the roadmap towards building up a RRAM-based logic system, the first step is the realization of a complete set of Boolean logic. Currently several approaches are under development for this goal. One is the material implication and FALSE (always output logic value 0) operations, which form a computationally complete logic set to realize a total of 16 possible binary Boolean functions. However, the lengthy iteration processes for certain logic functions and the lack of signal restoration may be hurdles for practical application, since the temporal computational complexity is significantly increased [2]. Another strategy, the so-called sequential logic, has been proposed to realize all 16 Boolean logic within 3 cycles [6]–[11]. This method is commonly based on bipolar (BRS) or complementary RRAMs (CRS). Yet, the leakage current through sneak-path in crossbar array with sole BRS often leads to logic errors, whereas the destructive read operation for CRS leads to extra initialization cycles and excess power consumption. Furthermore, essential logic methods for high density structure, such as 1TnR, are also on demand [12]. In this letter, we adopt a one transistor one resistive memory (1T1R) configuration for the sake of preventing the crosstalk between adjacent cells and building large-scale arrays [13]. We propose a functionally complete Boolean logic scheme in a single 1T1R structure. Arbitrary logic functions could be realized in two steps: initializing and writing. An additional read step is required to read out the logic result which is in situ stored in the nonvolatile resistive state of the memory. Our optimized RRAM-based universal logic device and operation scheme could be beneficial for future massive integration and practical application of RRAM based logic circuits. II. E XPERIMENT The 1T1R RRAM was integrated with NMOS transistor fabricated by standard 40 nm CMOS processes. The 1T1R cell and DC operation conditions are shown in Fig 1(a). After the standard processes for the transistor, the RRAM cell was fabricated on the drain-side. 10 nm HfOx layer was grown by atomic layer deposition on TiN bottom electrode, followed by the deposition of Ti top electrode by sputtering. Fig. 1(b) is the equivalent circuit of the 1T1R structure. The top electrode of the RRAM, the source and the gate of the transistor are defined as terminal T1 , T2 , and G, respectively. Electrical characterizations were performed by B1500A semiconductor parameter analyzer, B1530A fast measurement unit and M150 probe station. The transient current is in situ monitored.
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TABLE I VARIABLE A SSIGNMENT FOR 16 B OOLEAN L OGIC O PERATION
Fig. 1. (a) Schematic of 1T1R RRAM structure and operation conditions during DC sweeping. The RRAM is integrated on the drain-side of an NMOS transistor. Different voltage biases are applied to each terminal during electroforming, set and reset operations. (b) The equivalent circuit of a single 1T1R structure. The top electrode of the RRAM, the source and the gate of the transistor are defined as terminal T1 , T2 , and G, respectively.
Fig. 2. (a) Id − Vd transfer characteristics of the transistor in the 1T1R structure. (b) 100 consecutive DC I − V curves of the 1T1R RRAM. The inset shows the electroforming process. (c) Endurance tests under pulse switching up to 107 cycles. (d) Retention characteristics for over 104 seconds at 85°C.
III. R ESULTS AND D ISCUSSION Fig. 2(a) shows the Id − Vd transfer characteristics of the transistor, which serves as a current limiter to prevent unexpected hard breakdown. When the gate voltage (VG ) increases, a larger saturation drain current could be obtained. The red curves indicate two gate voltages that we chose in the forming (0.8V), set (0.8V) and reset (1.7V) processes. An electroforming process is required to activate the reversible resistive switching behaviors of a pristine memory device to a low resistive state (LRS), as shown in the inset of Fig. 2(b). In this forming process, the source is grounded, and a positive voltage of about 2.6 V is applied to the top electrode of RRAM. Fig. 2(b) shows the typical bipolar resistive switching characteristics of the 1T1R structure with 100 consecutive DC sweeping cycles. In the reset process, a positive voltage is applied to the source sweeping from 0 to 1.5 V with the top electrode of RRAM grounded, whereas VG is set up to 1.7 V to provide an Isat of∼ 50 μA. In the set process, a positive voltage is applied to the top electrode sweeping from 0 to 1 V with the source grounded. In contrast to a relative distributed high resistive state (HRS) on the order of 100 k, the device shows stable LRS of ∼9 k. Regarding the variation of the
HRS, it is related to the stochastic disruption of conducting filaments in HfOx layer. Pulse mode is more commonly adopted for practical operation. Here, to set the device from HRS to LRS, positive voltage pulses (1.5 V, 500 μs; 0.8 V, 500 μs) are applied to terminal T1 and G with terminal T2 grounded. To reset the device, positive voltage pulses (1.5 V, 500 μs; 1.7 V, 500 μs) are applied to terminal T2 and G with terminal T1 grounded. The endurance characteristic in Fig. 2(c) shows that the resistance ratio of HRS/LRS is kept above 10 for up to 107 cycles. The retention plotted in Fig. 2(d) shows no obvious degradation for over 104 seconds at 85 °C. Next, we turn to the implementation of Boolean logic. In our logic concept, the resistive state of the memory, which can be determined by an initialization step, is the first logic variable (I) involved in computation. “0” represents the HRS and “1” refers to the LRS. Besides, for each logic function, three voltage pulses are applied to the three terminals (G, T1 , and T2 ) of the 1T1R structure, respectively, serving as other three logic variables. The low voltage potential (0 V or grounded) is represented by logical “0”, and the high voltage potential by “1” (1.5 V for terminal T1 , T2 , and 0.8 V or 1.7 V for terminal G). Based on the definition above, all 16 Boolean logics can be realized with two sequential steps: initializing and writing. Initializing step: by appropriate positive or zero potential at terminal G, T1 , and T2 , the structure is pre-operated to a required state, which could be 0, 1, logic input p or q, according to the executing function in Table I. Writing step: three voltage pulses are simultaneously applied to corresponding terminals. The final resistive state of the memory, i.e. the logic result, is determined by four variables together: the initial state and three voltage potentials. Note that the variable assignment in Table I for each logic function is not unique. For instance, p¯ can be realized by an alternative variable combination: (I = 1, G = 1, T1 = 0, T2 = p). After the logic computing processes, the logic outputs are directly stored in the RRAM, achieving the so-called in-memory computation. The results (R) can be read out by a small voltage pulse across the device. The relation between the logic result (R) and the input variables (I, G, T1 , T2 ) is defined by the equation below: R = I G¯ + I GT1 + I G T¯1 T¯2 + I¯GT1 T¯2
(1)
WANG et al.: FUNCTIONALLY COMPLETE BOOLEAN LOGIC IN 1T1R RESISTIVE RANDOM ACCESS MEMORY
TABLE II O PERATION S TEPS F OR NAND L OGIC
Fig. 3. Experimental results of NAND logic implemented by 1T1R RRAM. In step 1, the RRAM is initialized to a LRS of ∼10 kΩ (I = 1). In step 2, three variables are simultaneously applied: T1 = 0, G = p, T2 = q. Among the four variable combinations, only “p = q = 1” switches the device to a HRS of ∼93 kΩ within 200 ns, as shown by the in situ monitored transient current. The HRS is readout by a 50 mV voltage and represents a logic output of 0.
NAND is a functionally complete logic, which means any Boolean logics can be constructed through topologically connected NAND gates. Hence, the function of NAND is experimentally demonstrated to verify the validity of our method. The detailed variable assignments and operation steps are summarized in Table II. As shown in Fig. 3, to ensure an initial LRS of ∼10 k (I = 1) for the RRAM cell in the first step, positive voltage pulses (0.8 V, 500 μs; 1.5 V, 500 μs) are applied to terminal G and T1 (G = 1; T1 = 1), respectively, with terminal T2 grounded (T2 = 0). Subsequently, we simultaneously input logic signals p and q to terminal G (G = p) and T2 (T2 = q), respectively, with terminal T1 grounded (T1 = 0). Finally, the logic result is read out through a small voltage (Vread = 50 mV) with the transistor turned on (G = 1). The output is “0” only in the case of “ p = q = 1”. In other words, inputting positive voltage pulses to terminal G and T2 at the same time can switch the device to a HRS of ∼ 93 k. The experimental results for four possible combinations of input variable p and q in Fig. 3 indicate the successful realization of NAND. By specific interconnection of logic gates, it is also possible to construct complex combinational logic circuits,
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TABLE III C OMPARISION OF RRAM B ASED L OGIC M ETHODOLOGIES
which could be the next critical step forward for practical application of RRAM based nonvolatile logic. For example, a one-bit full adder can be built with two XOR, two AND, and one OR gates [14]–[20]. Yet, herein variable G, T1 , and T2 are voltages, and variable I and output are resistive states. The cascading problem which is induced by the heterogeneous set of input and output and faced by other logic schemes [6]–[10], could be partially addressed: 1) The logic results of all logic can act as input of four logic gates (i.e. p, OR, NIMP, RNIMP), according to Table I. The rest 11 logic functions could be realized by combination of these 5 logics, for instance, ( p NAND q) NIMP p can realized p. ¯ 2) By introducing a read-out circuit, consisting of an inverting amplifier and a buffer, the stored resistance value can be converted into a voltage potential for the next gate. Meanwhile, the signal restoration can be realized. The read-out circuit could be shared by several 1T1R structures in a common horizontal row, just like the load resistor in IMP logic circuit [2]. This design will not significantly increase the complexity and area consumption of a large-scale chip. Our method has shown its feasibility to implement basic Boolean algebra and logic gates, low computation complexity with only one 1T1R structure in two logic steps, and the compatibility to the existing large-scale commercial integration process of CMOS transistor and nanoscale RRAM. In Table III we compared several key performances of different RRAM based nonvolatile logic methodologies. IV. C ONCLUSION In summary, we have proposed a method to implement functionally complete Boolean logic in 1T1R RRAM structure. Our 1T1R device has shown highly uniform of resistive switching behaviors with excellent endurance and retention performances. 16 arbitrary Boolean logic functions can be implemented with two sequential steps. Logic computation result is in situ stored as the nonvolatile resistive state of the memory, and can be read out by an additional step. The realization of in-memory computation in the commercial 1T1R structure is an important step forward in the practical application of RRAM-based nonvolatile logic.
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