XbarGen: a Memristor Based Boolean Logic Synthesis tool - IEEE Xplore

2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

1

XbarGen: a Memristor Based Boolean Logic Synthesis tool Marcello Traiola1 , Mario Barbareschi1 , Antonino Mazzeo1 , Alberto Bosio2 1

DIETI, University of Naples Federico II Naples, Italy [email protected] {mario.barbareschi, mazzeo}@unina.it

Abstract—The shrinking process of CMOS technology is reaching its physical limits, thus impacting on several aspects, such as performances, power consumption and many others. Alternative solutions are under investigation in order to overcome CMOS limitations. Among them, the memristor is one of the promising technologies. Several works have been proposed so far, describing how to implement boolean logic functions employing memristors in a crossbar architecture. In this paper, we propose a tool able to automatically map any boolean function to a memristor based crossbar implementation. The proposed tool helps to perform a design space exploration to identify the best implementation w.r.t. performances and area overhead. Index terms—Memristor crossbar, Design Space Exploration, Boolean Functions. Circuit Synthesis I. I NTRODUCTION Today’s computing devices are based on the CMOS technology, that is the subject of the famous Moore’s Law [1] predicting that the number of transistors in an integrated circuit will be doubled every two years. Despite the advantages of the technology shrinking, we are facing the physical limits of CMOS. Among the multiple challenges arising from technology nodes lower than 20 nm, we can highlight the high leakage current (i.e., high static power consumption), reduced performance gain, reduced reliability, complex manufacturing process leading to low yield and complex testing process, and extremely costly masks [2], [3], [4], [5]. Additionally, the expected never-ending increasing of performances is indeed no longer true. Looking in more detail, the classical computer architectures, either von Neumann or Harvard, divide the computational element (i.e., CPU) from the storage element (i.e., memory). Therefore, data have to be transferred inside the computational element in order to be processed and then transferred back to be stored. The main problem of this paradigm is the bottleneck due to the data transfer time limited by the bandwidth. For example, transferring one TeraByte at the rate of 1Gbit/second requires more than two hours. Many new technologies are under investigation, among them the memristor is a promising one [9]. The memristor

978-1-5090-3561-8/16/$31.00 ©2016 IEEE

2

LIRMM, Université Montpellier Montpellier, France [email protected]

is a non-volatile device able to act as both storage and information processing unit that presents many advantages: CMOS process compatibility, lower cost, zero standby power, nanosecond switching speed, great scalability, high density and non-volatile capability [10], [11]. Thanks to its nature (i.e., computational as well as storage element), the memristor is exploited in different kind of applications, such as neuromorphic systems [12], non-volatile memories [13], computing architecture for data-intensive applications [6]. A fundamental component of any kind of computing architecture is the implementation of boolean logic functions. In [14], the authors proposed a methodology for the synthesis of boolean logic function on a memristor crossbar. Their work showed that is possible to implement any kind of boolean function on a memristor crossbar. However, the experimental results have been carried out on a couple of small circuits only due to the lack of an automated synthesis tool. In this paper, we aim to extend the work of [14] by presenting a tool able to automatically map any boolean function to a memristor based crossbar implementation. Moreover, we investigate the impact of different synthesis optimization parameters on the memristor crossbar to evaluate area and performances. The remainder of the paper is structured as following. Section II presents the state of the art and provides the required background on the memristor based computation. Section III details the proposed memristor and crossbar model as well as the synthesis methodology, while the Section IV gives the experimental results. Finally, the Section V draws the conclusions. II. BACKGROUND AND S TATE OF THE A RT In this section we provide the basics about the memristor modeling, as well as the way how the memristor can be exploited to implement a given boolean function. A. Memristor model A memristor is a non-linear electrical component whose electrical resistance is not constant but depends on the history of the charge flowed through the device itself. Since we intend to implement a digital circuit, we refer to the memristor Voltage-Current relation depicted in Figure 1, detailed in [8],

2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

as the best solution for modeling the memristor’s behavior (i.e., thanks to the ideal response to a pulse-wave). Thus, as the Figure 1 shows, the voltage applied to the memriristor’s terminals does not change its resistance until it crosses a threshold. In the adopted ideal model, the upper and the lower thresholds have the same absolute value. We resort to the Snider Boolean Logic (SBL) [8] convention whereby a lower resistance (steeper curve denoted as RON ) represents a logic ‘0’ while an higher resistance (lower slope curve denoted as ROFF ) represents a logic ‘1’. Two basic operations can be performed, defined as SET and RESET. The first one allows to program the memristor to RON and thus at logic ‘0’, while the second one programs the memristor to ROFF that corresponds to logic ‘1’. The Figure 1 depicts SET and RESET operations as described by Xie et al. in [14]

IN

. . .

-Vth

V Vth

ROFF = 1

Memristor ideal Voltage-Current relation [8]

—

-

RON

I

ROFF

+

+

Vx = GND

OL

0

— F

1

EVM

RI CMF

F

(b)

(a)

Figure 2. Fast Boolean Logic Circuit

Below, the description of the blocks: • •

input block, where inputs are stored during the RI step; minterms block, where minterms are configured during CFM and evaluated during EVM; AND block, where results of EVM are stored and AND operation is performed during EVR; output block, where results of EVR are stored and inversion operation is performed during INR;

For the purpose of realizing each step of the FSM, the authors proposed some primitive operations that we summarize in Figure 3. Each of these operations can be performed using as many input and output memristors as desired.

Vx = GND

Vw

RESET

Vw

GND

-

-

VR +

GND

-

-

ROFF

-

ROFF

SET

EVR

INA

I +

+

RON

Vw

-

ROFF

INR

-

Vw

A N D

Mn

•

RON = 0

SO

— M1

•

I

2

+

Vx = GND

RON

ROFF +

RON +

+ Vx = Vw

VR +

Vw +

ROFF Vx = GND

ROFF

Vw + RON

RON -

ROFF -

Vx = VR

Figure 1. Set and Reset operations [14]

RON -

ROFF

NOT

Then, as Figure 2-a shows, FBLC is divided in blocks, useful to accomplish FSM’s steps (fig 2-b) which are:

Vx = VR

-

-

+

AND

Vw

GND ROFF

ROFF

[

RON

Vw

Vx = Vw

RON +

ROFF

AND (all input 1)

Vw +

RON +

VR +

-

NAND

Vx = GND

NAND (all input 1) VR +

ROFF

ROFF

-

-

ROFF

-

[[

ROFF

+

Vx = GND

GND

+

f = M1 + M2 + ... + Mn = M1 · M2 · · · · · · Mn

-

Vw

+

Snider proposed in [8] a design methodology for memristor crossbar that aimed to implement boolean functions. This design was then improved by Xie et al. in [14]. Let us briefly recall their proposition referring to it as Fast Boolean Logic Circuit (FBLC). First, the logic circuit requires that the Boolean function is expressed in the SOP format:

ROFF

Invert0

Vw

-

ROFF

Invert1

Vw +

-

B. Fast Boolean Logic Circuits

Copy0 VR +

-

Copy1 VR +

NAND (at least one input 0) AND (at least one input 0) Figure 3. FBLC primitive operations

INA: RI: CFM EVM: EVR: INR: SO:

initialize all the memristors to ROFF ; the input block receives the inputs; configure all minterms simultaneously, in parallel; evaluate all minterms simultaneously (NAND); evaluate results: f is calculated (AND); invert results: f need to be inverted to achieve f send outputs: the result captured in OL is sent out.

By driving the crossbar’s nano-wires with the right voltages during each step, it is possible to calculate a boolean function in a constant number of steps. We report below in Figure 4 an example of crossbar for a simple 2 inputs / 1 output function, built following the FBLC approach.

2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

A

B

—

A

—

—

B O

3

O n8

V1 M01

V2 M02

n9

IN

H0

— AB — AB — AB

a

—

H0 M11

M12

H1

— —

H2

o1

O

n5

n6

H3

—

b

n7

H1

c

H4 V0

V1

V2

V3

V4

V5

O = AB + AB + AB = AB · AB · AB

Figure 6. Function’s levels

Figure 4. FBLC example

III. T OWARDS AUTOMATIC CROSSBAR SYNTHESIS

Due to the lack of an automated process of translation from a given boolean function to a memristor based crossbar architecture, deeply investigating about memristor based crossbar circuits turns out to be really hard to accomplish. Therefore, in order to overcome these problems, we developed XbarGen.

Second, the tool performs a mapping to one or more crossbars depending on how many levels it finds. Mapping to a crossbar means that inputs, outputs and related minterms of each level are translated into a FBLC, as explained in [14] and briefly reminded above. It is worth noting that, when more crossbars are produced, they must be connected together in series, as proposed by Snider in [8] and depicted in figure 7. Consequently, the latency of the circuit grows proportionally to the number of serially connected crossbars. data flow CMOS Control Logic

control wire B

XbarGen is a command line tool written in C++ which, starting from a boolean function described in the Synopsys equation format - EQN - (fig 5), executes the mapping to a memristor based crossbar architecture and produces a schematic view of the crossbar(s).

—

C N5 N7 N5 N7 H0 H1

—

H2

N5

—

N7

—

A

H3 H4 V1

V2

V3

V4

V5

V6

V7

— — — — — N5 N7 A N5 N7 N8 N6 N8 N6

IN

—

H0

— —

N5 N7

H1

— AN —

H2

5

INORDER = a b c ; OUTORDER = o1 ; o1 = ! a ∗ b ∗ ! c + ! a ∗! b∗c + a ∗! c + a∗b ;

Figure 5. Synopsys equation format (EQN)

—

N8

H3

—

N6

Latch

H4 V0

—

—

First, the tool operates an analysis of the given function. As the figure 5 shows, it is possible either that a function’s output depends directly on its inputs either that it depends on “intermediate values”, which indeed depends on inputs. Thus, we will call level a set of inputs and outputs such that: inputs are independent from one another each output depends only on inputs

In this way we are able to describe a boolean function as a set of levels each one dependent from one another (figure 6)

V1

V2

V3

—

——

H1

8

—

N9

H2 V0

V1

V2

V3

V4

V5

V6

V7

—

V8

V9

—

N6 N9 N6 N9 O1 O1 H0

— AN

V4

—

A N8 A N8 N9 N9 IN

V5

Latch

•

— —

—

Latch

•

B

— CB — CB

Input Latch

V0

INORDER = a b c ; OUTORDER = o1 ; n5 = ! b ∗ c ; n6 = a ∗ ! n5 ; n7 = b ∗ ! c ; n8 = ! n5 ∗ ! n7 ; n9 = ! a ∗ ! n8 ; o1 = n6 + n9 ;

—

C

IN

IN

H0

9

H1

— N N 6

—

O1

H2 V0

V1

V2

V3

V4

V5

Output Latch

Figure 7. Snider Boolean Logic Circuit

IV. E XPERIMENTS AND RESULTS This section provides the experimental results achivied by the proposed synthesis tool and the adopted crossbar model. We also compare the proposed approach with the state of the art.

2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

bmark

Inputs

rd53f1 rd53f2 rd53f3 xor5_d con1f1 con2f2 rd73f1 rd73f2 rd73f3 newill_d newtagd rd84f1 rd84f2 rd84f3 rd84f4 max46_d sao2f1 sao2f2 sao2f3 sao2f4 sym10_d t481_d 5xp1 alu2 alu4 apex1 apex2 apex4 apex5 apex6 apex7 b9 clip cm150a cm162a cm163a dalu e64 ex1010 ex4 frg2 misex1 misex3 misex3c parity pdc seq squar5 t481 table5 tcon term1 too_large vda x1 x2 x3 x4

5 5 5 5 7 7 7 7 7 8 8 8 8 8 8 9 10 10 10 10 10 16 7 10 14 45 39 9 117 135 49 41 9 21 14 16 75 65 10 128 143 8 14 14 16 16 41 5 16 17 17 34 38 17 51 10 135 94

Ms 7 8 7 7 8 9 8 7 7 11 7 8 7 7 10 28 9 9 9 9 11 5 14 12 8 12 10 11 16 22 28 19 21 21 14 8 13 24 11 7 22 18 14 10 7 17 11 18 11 14 7 10 14 11 11 11 22 39

Chakraborti et al. OPs Mp 58 15 59 17 41 11 41 11 59 17 47 18 84 18 57 13 106 25 104 33 63 14 99 21 63 15 62 14 135 33 456 150 187 46 179 46 149 34 159 32 196 40 137 26 283 84 1030 284 3634 642 7975 1626 1701 122 5727 2073 6630 806 3761 770 1937 290 634 125 485 120 199 56 198 46 176 42 4856 627 840 94 6606 1984 3076 256 8433 803 231 83 2969 444 2453 429 119 23 3658 507 10808 1566 224 93 137 26 4068 580 166 57 896 105 2866 282 3039 805 2810 230 206 60 3761 770 3042 401

[7] OPp 34 35 35 35 47 47 48 49 46 50 51 57 57 56 57 72 73 83 71 69 70 107 73 148 334 705 237 447 888 1169 437 298 89 127 102 116 470 456 396 928 1005 69 185 239 113 142 692 56 107 168 118 260 232 273 398 80 1169 642

Nmin 6 20 16 16 5 6 42 64 35 22 14 120 128 1 162 47 10 20 92 85 837 1547 70 257 1791 206 1035 438 1160 656 507 107 166 17 43 42 2224 65 1024 620 4159 18 1426 297 32768 2192 1066 30 481 158 32 257 1035 93 309 17 738 530

Nmem 48 132 108 108 37 38 330 528 275 177 107 1098 1170 27 1476 475 124 242 914 898 9229 21699 385 2282 19947 3018 15610 5489 8004 4926 4126 642 1078 142 230 229 26700 2470 18950 5220 35729 132 15559 2710 557090 61318 14502 261 5267 2566 154 2298 15610 1544 2624 118 5535 3431

Single Crossbar A C NC 96 7 1 264 7 1 216 7 1 216 7 1 98 7 1 96 7 1 704 7 1 1056 7 1 592 7 1 432 7 1 288 7 1 2196 7 1 2340 7 1 54 7 1 2952 7 1 980 7 1 264 7 1 484 7 1 2068 7 1 1914 7 1 18458 7 1 52666 7 1 2754 7 1 8448 7 1 79200 7 1 44000 7 1 85198 7 1 24678 7 1 495908 7 1 353808 7 1 93740 7 1 15996 7 1 4816 7 1 836 7 1 1862 7 1 2016 7 1 407862 7 1 34060 7 1 41400 7 1 124460 7 1 2424636 7 1 780 7 1 80696 7 1 18096 7 1 1114180 7 1 250096 7 1 167504 7 1 1014 7 1 16422 7 1 11136 7 1 3234 7 1 23584 7 1 85198 7 1 14896 7 1 59340 7 1 850 7 1 392184 7 1 198660 7 1

TXbG 4,40771 5,71666 7,27523 6,88398 4,11653 4,71909 10,9064 14,0526 9,78765 6,02758 5,35582 32,4858 28,5734 3,52854 42,7301 10,6472 5,7189 6,67963 23,0123 24,8451 592,392 2476,55 19,3511 106,399 4330,92 1471,98 1811,35 2875,89 1401,94 669,392 315,733 73,3105 41,0498 10,778 32,4292 23,054 5701 125,161 108896 359,811 13511,8 7,30883 2430,17 701,002 1,95466e+06 1,65169e+06 2323,22 15,6276 232,543 416,991 18,7235 88,2616 1389,22 376,691 156,096 7,6228 648,998 329,832

Nmin 16 27 22 22 13 16 113 34 59 51 24 188 40 7 176 185 41 60 130 137 639 657 140 404 740 2677 445 3466 1293 740 252 113 180 62 38 36 1387 1437 3350 478 1208 72 1582 734 46 1624 2413 68 1875 2001 48 313 827 955 400 60 841 470

Nmem 120 203 156 156 105 122 851 244 459 401 192 1418 288 63 1336 1379 323 474 1002 1051 4721 5033 985 3100 5706 19430 3627 24824 9630 5138 1769 861 1354 468 298 288 10169 12134 23952 3672 8712 504 11604 5380 346 11994 17877 484 13495 14648 298 2420 6375 6855 3007 428 6241 3378

Multiple Crossbars A C 492 56 1318 49 894 42 894 42 338 49 490 49 15232 98 1842 56 4186 91 3040 91 900 77 37746 119 2892 56 126 49 34468 119 37264 112 2320 91 5226 98 18000 126 19684 133 372748 154 292290 203 23218 70 74522 280 199562 294 5110198 189 134188 203 9858816 147 1239620 147 569256 105 53172 98 20768 70 33454 77 4502 91 2216 63 2148 56 879430 245 416608 448 8992430 168 299178 112 1265816 91 7314 49 1803240 161 483346 161 3956 56 1398822 182 3580692 203 6936 49 3463670 147 2370246 182 6034 21 107300 112 411848 210 640324 112 179366 91 5680 49 893392 105 207320 70

NC 8 7 6 6 7 7 14 8 13 13 11 17 8 7 17 16 13 14 18 19 22 29 10 40 42 27 29 21 21 15 14 10 11 13 9 8 35 64 24 16 13 7 23 23 8 26 29 7 21 26 3 16 30 16 13 7 15 10

TXbG 13,1694 17,8544 15,5731 14,4109 17,004 18,7644 92,7335 25,8204 39,1519 36,2447 18,9949 163,551 30,3401 12,4683 158,735 210,26 27,696 49,9699 105,365 111,094 887,967 878,071 171,619 4250,49 54801,5 11086,1 614,329 18019,5 3189,77 1405,3 279,106 117,437 175,761 50,1216 31,2726 30,6175 20674,4 2436,47 17142,5 735,931 3972,73 59,2965 4496,13 1188,36 51,0531 4124,41 9025,33 55,5393 7784,26 5730,48 35,5259 393,415 1394,65 2693,42 544,872 52,4899 1961,42 660,801

Nmin 11 25 13 13 9 10 80 19 40 23 10 144 22 7 142 156 39 45 80 83 466 427 101 363 657 2020 268 2744 832 674 197 92 111 47 33 32 1122 520 2616 408 728 61 1167 590 46 840 1775 48 803 1481 40 150 463 650 286 46 611 341

4

Multiple Crossbars Nmem A 87 378 191 1108 93 326 93 326 69 242 74 284 606 9354 139 706 312 2212 177 884 78 260 1082 26978 162 1028 63 294 1082 26504 1188 30628 309 2496 345 3974 628 9160 651 9810 3494 240148 3253 177764 740 13030 2767 71596 5061 191338 14817 3827274 2134 71438 19958 7830882 6213 629036 4678 505306 1404 36774 690 15366 829 14098 363 4102 257 1626 254 1810 8270 700910 3885 348982 19132 7027470 3124 248724 5142 518280 423 5740 8691 1280548 4340 405166 346 3956 6290 627542 13437 2541004 326 3928 5875 857962 11082 1841246 226 5218 1165 29526 3621 194054 4638 444516 2091 123350 314 3636 4527 550626 2403 112264

(optimized) C NC 35 5 49 7 42 6 42 6 28 4 28 4 70 10 42 6 63 9 70 10 35 5 84 12 42 6 21 3 84 12 98 14 70 10 63 9 84 12 84 12 119 17 161 23 63 9 217 31 238 34 119 17 140 20 119 17 84 12 98 14 91 13 56 8 63 9 63 9 56 8 49 7 217 31 70 10 119 17 98 14 77 11 42 6 140 20 126 18 56 8 147 21 154 22 42 6 91 13 154 22 14 2 84 12 168 24 70 10 70 10 42 6 77 11 63 9

TXbG 9,26288 17,5566 10,0649 10,9131 9,66641 9,93731 69,9187 12,7191 27,0125 16,5744 8,82142 126,552 14,4034 7,68629 130,351 141,284 26,6478 36,1185 65,3744 66,9386 625,83 508,84 86,1893 3192,4 39688,8 7804,18 315,608 15452,3 1863,43 1227,78 232,827 95,8065 107,43 48,2901 34,8671 34,41 15307,3 1088,73 15397,7 618,099 1768,91 46,7335 3152,18 1003,96 50,9398 1741,17 6382,24 34,2392 2170,26 4415,77 29,4298 162,668 699,077 1737,85 371,451 42,7509 1221,77 406,664

Table I C OMPARISON OF B ENCHMARKS

A. Experiments In order to investigate about the impact of different synthesis optimization parameters on the memristor crossbar in terms of area and performances, we carried out several experiments. Given a function expressed in BLIF format, we first used synthesis tools (i.e. ABC and SIS by Berkeley) in order to produce EQN format. Specifically we used: •

•

SIS to generate equations in which outputs depend directly on inputs, so they can be translated to a single crossbar ABC to generate equations in which outputs depend on intermediate values, so they can be translated to more crossbars. Also an “optimized” version has been produced using the resyn2 script [15]

An overview about achieved results is presented and discussed hereafter. In table II a legend of the used labels is reported.

B. Discussion Table I shows the synthesis results on a number of combinational benchmarks. We noticed that: 1) As the levels’ number of a function grows - thus the number of crossbars and, hence, the latency - the number of memristor grows instead of decreasing. 2) Given the number of crossbars, the response time of the circuit remains constant for any function. a) Therefore, in terms of both area and performances, is better to have only a single crossbar in order to obtain a tiny and constant time and use fewer memristors. 3) The number of minterms has an high impact on the memristors’ total number. a) At the current state of art, there is not any tool that makes possible to optimize a boolean function in terms of number of minterms. Maybe the next direction could be such.

2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) Symbol pij Nin (lj ) Nout (lj ) Nocc (mi , lj ) Nlit (mi )

Description Whether the i-th minterm is in the j-th level (boolean) Num. of input for the j-th level Num. of output for the j-th level Num. of occurrences of the i-th minterm in the j-th level Num. of literals of the i-th minterm

Nmem

No. of memristors in the circuit

Nmin

No. of minterms in the circuit

A

Total area

Expressed as Given Given Given Given Given   P P P 2 ∗ Nin (lj ) + (Nocc (mi , lj )) + (Nlit (mi ) ∗ pij ) + 2 ∗ Nout (lj ) i

j

Ms OPs Mp OPp

P

Memristor switching time Num. of steps of a Crossbar computation “Latency” of a Crossbar Num. of Crossbar in the circuit Needed Cycles to complete computation Time (in milliseconds) needed by XbarGen to execute Time (in milliseconds) for simulate VHDL design (50ns long) Chakraborti et al. [7] No. of memristors (serial) No. of memristor micro-operations (serial) No. of memristors (parallel) No. of memristor micro-operations (parallel) Table II L EGEND

In addition, with regard to feasability of translation and simulation of memristor crossbar behavioral circuits, we collected the time that XbarGen needs to translate a boolean function and produce the crossbar schematic view (table I). XbarGen experiments were run on a dual-core i7 MacBook Pro with 2,8GHz clock, 4 GB RAM and running OSX v10.11.4.

i

Given 

j

tM NSteps TC NC C TXbG Tsim

5

  P [2 ∗ Nin (lj ) + 2 ∗ Nout (lj )] ∗ 1 + (pij ) + Nout (lj ) i

Given Given tM ∗ NSteps Given TC ∗ NC Experimental Experimental

and, in this paper, we advanced the state-of-the-art with a comparison with the state-of-the-art of performances w.r.t. several benchmarks. Indeed, we developed XbarGen, a tool which is able to process boolean equations for the mapping over memristor crossbars.

R EFERENCES

C. Comparison Chakraborti et al. in [7] proposed an architecture based on material implication operation implemented using memristors. In brief, they came up with a realization of 2-to-1 multiplexer using memristors, and a synthesis methodology that represents a given Boolean function as a Reduced Ordered Binary Decision Diagram (ROBDD) and maps it to memristor implementation. They carried out some benchmarks too (table I), reporting interesting results: comparing experiments that exploit parallelism and those that do not, the inverse ratio time-area is respected; from our side, instead, it is not true. On the other hand, execution time of the architecture in [7] depends on the function under consideration; execution time of Snider architecture could be independent from the function, if it is translated to a single crossbar. This could mean that one would prefer an architecture such as proposed in [7] in case of area constraints and an architecture such as Snider proposed in [8] in case of time constraints. V. C ONCLUSION The memristor is one of the most promising technologies which is able to deal with the CMOS limitations. In particular, since the memristor is inherently able to behave also as a non-volatile device, it allows to overcome the bottleneck of the data transfer to the computational unit and back to storage elements. The research community is facing with the synthesis of boolean functions by exploiting memristor-based crossbars

[1] ITRS 2013 report. [Online]. Available: http://www.itrs.net/ [2] B. Hoefflinger, “Chips 2020: A Guide to the Future of Nanoelectronics”, The Frontiers Collection, Springer Berlin Heidelberg, 2012, pp. 421– 427 [3] J. McPherson, “Reliability trends with advanced CMOS scaling and the implications for design”, in IEEE Custom Integrated Circuits Conference, 2007, pp. 405–412 [4] S. Borkar, “Design perspectives on 22Nm CMOS and beyond”, in Proceedings of the 46th Annual Design Automation Conference, 2009, pp. 93-94 [5] G. Gielen, et al., “Emerging yield and reliability challenges in nanometer CMOS technologies”, in Proceedings of the Conference on Design, Automation and Test in Europe, pp. 1322-1327, 2008 [6] S. Hamdioui, et al., ‘Memristor based computation-in-memory architecture for data-intensive applications’, in Proceedings of the Conference on Design, Automation and Test in Europe, pp. 1718-1725, 2015 [7] S. Chakraborti, P. V. Chowdhary, K. Datta and I. Sengupta, "BDD based synthesis of Boolean functions using memristors," 2014 9th International Design and Test Symposium (IDT), Algiers, 2014, pp. 136-141. [8] G. Snider, “Computing with hysteretic resistor crossbars,” Applied Physics A, vol. 80, pp. 1165–1172, 2005. [9] L. Chua, ‘Memristor-the missing circuit element’, IEEE Transactions on Circuit Theory, vol. 18, no. 5, pp. 507–519, 1971 [10] R. Waser et al., “Redox-based resistive switching memories–nanoionic mechanisms, prospects, and challenges,” Advanced Materials, vol. 21, pp. 2632–2663, 2009 [11] J. J. Yang et al., “Memristive devices for computing,” Nature nanotechnology, vol. 8, pp. 13–24, 2013 [12] J. R. Burger et al., “Variation-tolerant computing with memristive reservoirs,” IEEE/ACM International Symposium in Nanoscale Architectures (NANOARCH), 2013, pp. 1–6. [13] K.-H. Kim et al., “A functional hybrid memristor crossbar-array/cmos system for data storage and neuromorphic applications,” Nano letters, vol. 12, pp. 389–395, 2011.

2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

[14] Lei Xie, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Said Hamdioui, Koen Bertels, “Fast Boolean Logic Mapped on Memristor Crossbar”, IEEE International Conference on Computer Design (ICCD), pp. 335342, 2015. [15] ABC User Guide. [Online]. Available: http://www.eecs.berkeley.edu/~alanmi/abc/

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