David Yu-Liang Wu. Department of Computer Science ... David Ihsin Cheng. Ultima Interconnect ... RAMBO â Automatic Test Pattern Generation. (ATPG)-based.
Further Further Improve Improve Circuit Circuit Partitioning Partitioning using using GBAW GBAW Logic Logic Perturbation Perturbation Techniques Techniques Ray Chak-Chung Cheung David Yu-Liang Wu Department of Computer Science & Engineering The Chinese University of Hong Kong David Ihsin Cheng Ultima Interconnect Technology
Motivation Due to design complexity, I/O limitation and some other reasons, a chip is normally partitioned into sub-chips. Each sub-circuit consists of modules and nets. Our goal is to minimize the connecting wires between partitions with balance constraints. An improved partitioning result can be achieved if we consider the logic relationship between modules.
Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
2
Outline Introduction
Circuit Partitioning Alternative Wiring
Application of Alternative Wiring GBAW – Graph-Based Alternative Wiring Circuit Partitioning using GBAW technique Experimental Results on Multi-way partitioning Conclusion & Future Work
Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
3
Introduction - Circuit Partitioning Objective: Given a circuit is divided into several clusters, such that the interconnecting wires between clusters is minimized with balance constraints. There are several applications:
Packaging, Synthesis, Optimization, …
Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
4
Introduction – Alternative Wiring What is Alternative Wire?
Add a wire into a circuit Another wire (target wire) becomes redundant Remove target wire. Without changing the circuit functionality.
2 Powerful Alternative Wiring Tools
RAMBO – Automatic Test Pattern Generation (ATPG)-based GBAW – Graph-based
Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
5
Alternative Wiring - Application 1 Useful in different areas
Logic Optimization
final circuit becomes smaller
c b d e c’
g4 g1
redundant g5 g2
g6
d a b
wa
alternative wire
wr
f target wire
Session 4F - Paper 2
e c’ O2
g7 g3
b d
O1
g8
g9
g1 g5 g2
O1
g6
c a b
g8
g9
O2
g3
f
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
6
Alternative Wiring - Application 2 Circuit Partitioning
the interconnect wire between partitions is reduced from 3 to 2.
e
f
a b
e O1
f
a b
O2 c d
O2 c d
(a) An alternative wire in an irredundant circuit
Session 4F - Paper 2
O1
(b) No gain for logic synthesis, but gain for partitioning
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
7
GBAW A graph-based alternative wiring scheme Search alternative wire by isomorphism between local sub-networks and the pre-defined patterns. Can do both forward and backward search. Use Configuration to denote a Boolean network. No need of Boolean knowledge. Powerful in finding alternative wire and Very Fast!
Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
8
GBAW – Configuration
A Boolean network G with its sub-network S. Below shows the mapping from network to configuration. Node y define as a triplet (op, d-(y), d+(y)) op is the Boolean operator (AND, OR, NAND, NOR) d-(y) is the in-degree of y, d+(y) is the out-degree of y. (AND, dc, dc) both fanins or fanouts are also don’t care.
G a
S
g1
f1
g2
b
g3
c d
f2
(a) Boolean network G
(AND,2,1) a
g1
g2
a
(AND,dc,dc)
g1
g2
b c
b c
Session 4F - Paper 2
(AND,dc,1)
(AND,2,2)
D1
D2
(b) A configuration of S
(c) Another configuration of S
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
9
0-local pattern Bold line target wire
Dotted line alternative wire 0-local means the edge distance between target and alternative wire is 0. (op1,k,dc) a1
(dc,dc,dc)
g1
g2
g3
g4
(op3,k,dc)
(dc,dc,dc)
a2
ak
Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
10
1-local patterns AND
AND (or NAND)
(op1,dc,1)
(op2,dc,dc)
g1
a
g2
(a) Case 1-1, op1=AND, op2 =AND (or NAND); or op1=OR, op2=OR(or NOR)
(op1,k,dc) a1
g1
a2 . . . ak
(op2,k,dc) g2
(b) Case 1-2, op1=AND, op2 =AND (or NAND); or op1=OR, op2=OR(or NOR) AND
AND (or NAND)
(op1,dc,1) a
g1
(op2,dc,dc) g2
(c) Case 1-3, op1=NOR, op2 =NAND (or AND); or op1=NAND, op2=OR(or NOR)
Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
11
2-local patterns (NOR,dc,1) a
(NAND,dc,1) g2
g1
(NOR,dc,dc)
NAND,dc,dc
NAND,dc,1
NAND,dc,1
NAND,dc,dc
g3
a
g1
g2
g3
(a) Case 2-1
a1
(OR,dc,1)
(AND,dc,1)
g1
g2
g2 (NOR,dc,dc) or (OR,dc,dc)
a2 . . . ak
g4
dc,dc,dc
NAND,dc,dc
NAND,dc,dc
g5
g4
g6
dc,dc,dc
NAND,dc,1
NAND,dc,1
NAND,dc,dc
a
g1
g2
g3
(AND,k,dc)
NOT,dc,dc
(b) Case 2-2 dc
1 . dc . . t-1
(OR,dc,h)
(AND,t,1)
(OR,dc,dc)
(OR,s,dc)
1 dc . . . dc s-1
(AND,s,dc)
NAND,dc,dc
dc,dc,dc
g6
g5
(AND,h,dc)
dc
g4
dc,dc,dc
NOT,dc,dc
dc,dc,dc
g5
g4
g6
!NOT,dc,dc
NAND,dc,1
NAND,dc,1
NAND,dc,dc
a
g1
g2
g3
(c) Case 2-3
Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
12
Circuit Partitioning – GBAW technique Modeling the circuit as graph
Methods for graph partitioning
No change to the graph – KL or FM algorithm Modify the graph by replications (more areas) Couples the graph domain (nodes and edges) and the logic domain (function performs by each node) Gate 1
Gate 1
Gate 2
Gate 2
Cut wire = 2 Session 4F - Paper 2
Cut wire = 1
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
13
Circuit Partitioning – GBAW technique Our approach
Obtain excellent partitioning result from state-ofthe-art HMETIS-Kway. Graph domain – choose ANY graph partitioning
Logic domain only applies GBAW technique
Choose FM for its simplicity and efficiency. Proposed by Fiduccia and Mattheyses in 1982. Apply GBAW (GP) to search for another better partitioning result
fast and reduce the cut cost
Key: Even optimum graph partitioning results can still be improved Experiments were conducted on 2 to 5 way partitioning on MCNC benchmark circuits. Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
14
Overview Flow circuit modeled as a graph Optimized by hMETIS-Kway graph partitioning (GD)
by FM
a partition (local optimal solution)
logic perturbation (LD)
by GBAW
equal, better, or worse solution
different graph (same circuit) Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
15
HMETIS-Kway – state-of-the-art Increasing complexity of Physical Design, use multilevel approach to break down the problem size Phase 1 – Coarsening
Merge vertices to form a new vertex Size of new graph / hypergraph reduce fast
Phase 2 – Initial Partitioning
Apply k-way partitioning algorithm on a small problem
Phase 3 – Uncoarsening and Refinement Phase
Project back to the original graph More degree of freedom in finer graph, refinement scheme is necessary to improve final solution
Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
16
Multi-level Partitioning – 3 phases
Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
17
Pre-process the benchmarks There are totally 26 benchmarks.
Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
18
Cut wire and Cut cost Cut wire is the wire connecting between different partitions. Cut cost is the number of partition the hyper-edge connecting with. Cut wire = 2 Cut cost = 4
Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
19
Cut wire and Cut cost Cut wire is the wire connecting between different partitions Cut cost is the number of partition the hyper-edge connecting Cut wire = 2 Cut cost = 2
Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
20
Pin gain after rewiring
(a) gain = 2
(b) gain = 0
(c) gain = 0
(d) gain = -2
Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
21
GP algorithm Run hMETIS-Kway a very good initial solution heuristically select a cut wire wt wa ={w’s alt. wires} by GBAW yes wa empty ? k times
no rewiring
GP
Graph Domain improvement (by FM) Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
22
Alternative wiring statistics of RAMBO and GBAW 350 300 250 RAMBO alt. Wire GBAW Alt. Wire RAMBO CPU GBAW CPU
200 150 100 50 0
5xp1 C1355
Session 4F - Paper 2
alu2
duke2 term1
ttt2
30% more than RAMBO + 75 times speedup
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
23
Experimental Results Circuit 5xp1 C2670 C432 … C7552 alu4 des rot Total Average
HMETIS-Kway Area #lits Cut cost 61:71 235 30 516:527 1444 42 119:119 392 44 … … … 1281:1141 4105 18 428:357 1470 140 1727:2112 6655 236 441:383 1251 54 45506 1850
Area 73:63 517:531 118:130 1286:1142 438:360 1565:2282 442:384
GP #lits 239 1449 402 … 4111 1481 6663 1253 45656 +0.33%
Cut cost 28 34 36 … 18 120 146 46 1576 -14.48%
Comparison of 2-way partitioning by using hMETIS-Kway & GP
Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
24
Experimental Results by GP
hMETIS-Kway #lits Cut cost 45506 1850 45506 3339 45506 4250 45506 5185
2-way 3-way 4-way 5-way
GP #lits 45656 (+0.33%) 45748 (+0.53%) 45784 (+0.61%) 45828 (+0.71%)
Cut cost 1576 (-14.48%) 2999 (-10.18%) 3864 (-9.08%) 4706 (-9.24%)
Partitioning comparison between hMETIS-Kway & GP
Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
25
Conclusion & Future Work Presented a framework which integrates GBAW to multi-way circuit partitioning. We can apply any graph domain partitioner to GP and experimental results showed GP is able to reduce the cutcost over excellent results. Future Work
Apply GBAW on the timing optimization of FPGA routing and other physical design problems.
Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
26
The End Please feel free to ask any question !
Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
27
Further Further Improve Improve Circuit Circuit Partitioning Partitioning using using GBAW GBAW Logic Logic Perturbation Perturbation Techniques Techniques
Session 4F - Paper 2
Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques
28
