Golomb Coding Implementation in FPGA - CiteSeerX

Faculty of Electrical Engineering Universiti Teknologi Malaysia

VOL. 10, NO. 2, 2008, 36-40

ELEKTRIKA http://fke.utm.my/elektrika

Golomb Coding Implementation in FPGA G. H. H’ng, M. F. M. Salleh and Z. A. Halim School of Electrical and Electronic Engineering, Universiti Sains Malaysia, Seri Ampangan, 14300 Nibong Tebal, Pulau Pinang, Malaysia. *

Corresponding author: [email protected] (M. F. M. Salleh), Tel: 604-5996058, Fax: 604-5941023

Abstract: Golomb coding for data compression is a well known technique due to its lower complexity. Thus, it has become one of the favourite choices for lossless data compression technique in many applications especially in mobile multimedia communication. In this paper, the development of Golomb Coding compression and decompression algorithms in the Field Programmable Gate Array (FPGA) is presented. The coding scheme development in FPGA utilises the Verilog HDL. In order to prove its validity, the developed algorithm is simulated using the ALTERA Quartus II software. Keywords: Field Programmable Gate Array (FPGA), golomb coding, lossless coding. The remainder of the paper is organised as follows. Section 2 presents the details of Golomb Coding and the basic compression and decompression method. Section 3 presents the modified version of the Golomb coding compression and decompression methods in practical FPGA implementation. Section 4 presents the simulation results of the algorithms generated in order to prove their validity. Lastly, Section 5 concludes the paper.

1. INTRODUCTION The rapid widespread growth of digital technologies such as digital television, internet access, video and video calls have increased the demand for high storage and transmission capacity in order to fit the growing needs [1]. This has called upon for the need of efficient data compression techniques, where the original data is compressed into a smaller data size. This process also reduces the transmission bandwidth needed for data transfer. There have been extensive research efforts in this field since the last 40 years. A review of those research activities can be found in [2]. Golomb coding [3] is one of the lossless data compression techniques. It is capable of compressing larger sized data into a smaller sized data while still allowing the original data to be reconstructed back after decompression. Besides, there is other high performance lossless compression algorithm such as arithmetic coding [4] etc. However, this algorithm involves higher design complexity and computational load. Another class of compression technique is lossy compression. In lossy data compression, the reconstructed data loses some of the information, results a lower quality data. Golomb coding has been used in the latest H.264 video standard [5] as part of its entropy coding. The hardware implementation of H.264 video codec baseline profile is presented in [6]. This includes the hardware implementation of the Exp-Golomb coding for its entropy coding. Other Golomb coding applications includes the use in system-on-chip (SoC) test-data compression system as presented in [7]. In [8] Jung and Chong also use Golomb coding for SoC test data compression, where the new algorithm developed can reduce the scan-in power and test data volume. In this paper, the development of Golomb coding algorithms for data compression and decompression and their implementation in Field Programmable Gate Array (FPGA) is presented. In order to have simplicity in development and testing, the Golomb coding parameter m is set to 4. The algorithm is developed using the ALTERA Quartus II software [9].

2. BACKGROUND This section covers the details regarding Golomb Coding basic background information. In Golomb Coding, the group size, m, defines the code structure. Thus, choosing the m parameter decides variable length code structure which will have direct impact on the compression efficiency [3]. Once the parameter m is decided, a table which maps the runs of zeros until the code is ended with a one is created. Determination of the run length is shown as in Figure 1. A run length of multiples of m are grouped into Ak and given the same prefix, which is (k – 1) number of ones followed by a zero. A tail is given for each members of the group, which is the binary representation of zero until (m – 1). The codeword is then produced by combining the prefix and the tail. An example of the table is in Figure 2. Data set

01 0000001 0001 000001 001 1

Subset

01

0000001

0001

000001

001

1

Run-

1

6

3

5

2

0

length Figure 1. Determination of run-length Using Figure 2, binary strings can be divided into subsets of binary strings and replacing the subsets with the equivalent codeword as shown in Figure 3.

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G.H. H’NG, M.F.M. SALLEH, Z.A. HALIM / ELEKTRIKA, 10(2), 2008, 36-40

Group

Run-length

Group prefix

0 1 2 3 4 5 6 7 8 9 10 11

A1

A2

A3

0

10

110

Tail

Codeword

00 01 10 11 00 01 10 11 00 01 10 11

000 001 010 011 1000 1001 1010 1011 11000 11001 11010 11011

detected, the system will acknowledge that the end of prefix has been met and detects the value of the first tail bit. If the value of the first tail bit is ‘1’, the system will generate another 2 ‘0’s, otherwise, wait for the next tail bit. If the last tail bit is ‘1’, another extra ‘0’ will be generated and followed by a ‘1’ which marks the end of a subgroup of the original data. The system will then return to the status of waiting for the next subgroup prefix data. Begin 0 Data value? 1 Generate 4 ‘0’s

Figure 2. Golomb coding example with parameter m = 4 Data set

0 Data value? 1

01 0000001 0001 000001 001 1

Subset

01

0000001

0001

000001

001

1

Encoded

001

1010

011

1001

010

000

Generate 2 ‘0’s 0

Figure 3. Golomb coding example with parameter m = 4

1 Generate 1 ‘0’

Begin

Generate 1 ‘1’

Reset tail count 1

Figure 5. Golomb decoder algorithm (parameter m = 4)

Data value? 0 Increase tail count tail = 4?

Data value?

3. FPGA IMPLEMENTATION The Golomb encoder algorithm shown in Figure 4 is not yet a complete design for hardware implementation. Few modifications must be made in order to allow the algorithm to function properly. The encoded binary data will not necessarily be in multiples of bytes, thus padding bits must be placed to make the encoded binary data to be in multiples of 8. Other than that, the previous design of the algorithm was made with the assumption of that the input data string will be terminated with a ‘1’ but however in reality, this will not always be the case because the input data string may also be terminated with a ‘0’. In order to overcome this problem, the algorithm must be capable of detecting the end of data and if the last bit is a ‘0’, then additional ‘1’ must be added in order to complete the encoding process. However this will also cause another problem of original data being modified due to the additional ‘1’ added, and the decoding process will not work properly, resulting in different set of data being reproduced after the decoding process. In order to solve this matter, header bytes will be added in the beginning of the encoded data which will give the information of the original file size, thus allowing the decoding process to be done correctly by terminating the decoding process after the data size of the original file size was reached during decoding process. The modified Golomb encoder algorithm is shown in Figure 6.

False True

Generate ‘1’ Generate ‘0’ Generate tail Figure 4. Golomb encoder algorithm (parameter m = 4) The Golomb encoder model can be described in the flow chart as shown in Figure 4. The tail count is controlled by the number of ‘0’s in the input data. If ‘0’s are read, then the tail count will be increased proportionally until it reaches the m parameter where a ‘1’ will be generated as its output data. If the input data is ‘1’, the algorithm will generate a ‘0’ which acts as the divider between the prefix and the tail, and output the current tail count as the tail of the encoded string. The algorithm will then reset the tail count and waits for the next input data. The Golomb decoder model can be described in the flow chart as in Figure 5. The system will firstly detect the value of the prefix, if it is a ‘1’, the system will generate 4 ‘0’s and wait for the next value. If a ‘0’ is 37

G.H. H’NG, M.F.M. SALLEH, Z.A. HALIM / ELEKTRIKA, 10(2), 2008, 36-40

Reset State 1 • Output = original file

data = 1

• output = 0

data = 0 • tail ++ • if (tail = 4), output = 1

State 2

Total encode bytes not reached State 3 • output = tail[1]

Reset State 1 • Read original file size

Total encode bytes reached

State 5 • Finish encode with extra ‘1’ if needed • Pad byte with ‘0’

State 3

End Original file size reached

State 2

Original file size not reached

Data = 1 Output = 4 ‘0’s

If data = 0 State 4 • If data = 1, output = 2

Total encode bytes reached State 4 • output = tail[0]

byte of the encoded data may be padded with ‘0’s, thus will give wrong decoding output. However, this had been solved by introducing original file length header into the encoded data as in discussed previously. By knowing the original file size before encoding, the decoder will decode the encoded data until the encoded data reaches the original file size and terminate the decoding process. The modified Golomb decoder algorithm is as shown in Figure 7.

End

State 5 • If data = 1, output = 1

State 6 • Output = 1

Figure 6. Golomb encoder algorithm on FPGA with parameter m = 4 Figure 7. Golomb decoder algorithm on FPGA with parameter m = 4

After the system has been reset, the system will move into State 1, generating the original file size as its output, and move into State 2 where the system will wait for input. If the system detects that the total encoded bytes is already reached, the system will proceed to State 5. If the data input is ‘0’, the tail count will increase and return back to State 2. If the tail count reaches the value 4, the system will generate an output of ‘1’. On the other hand, if the data input is ‘1’, the system will generate an output of ‘0’ which is the separator between the prefix and the tail and move on to State 3. At State 3, the system will generate the first tail bit and continued by second tail bit at State 4. If the total encoded byte is met, the system will move to State 5, otherwise, back to State 2 where the system will wait for the next input data. At State 5, if the system detects that there is a need to finish the encode with an extra ‘1’ due to the input binary string did not terminate with a ‘1’, then extra encoding will be done with the extra ‘1’ added and then pad the last byte of data with ‘0’ if the encoded data is not in bytes (multiples of 8). The system will then stop handling any process until a Reset signal is given. The Golomb decoder algorithm shown in Figure 5 is not yet a complete design for hardware implementation, like its Golomb Encoder algorithm counterpart. The last

After the system reset, the system will move into State 1 unconditionally where the system will retrieve the original file size from the encoded data and store it in memory before proceeding to State 2. State 2 will always check whether the total decoded data size has already met the target of the original file size or not. If the target is met, the process will terminate and the system will be idle until Reset signal is given. If the target is not met, the system will move to State 3 where the system will wait for incoming data. If the data received is a ‘1’, the system will generate 4 ‘0’s and return back to State 3. If a ‘0’ is received, the system will acknowledge that the marker between prefix and tail has already been met and proceed to tail decoding process. For the first tail bit at State 4, if the ‘1’ is received, the system will generate 2 ‘0’s as the output and move to State 5 where the system will decode the second tail bit. If a ‘1’ is received, the system will generate 1 ‘0’ as the output and move to State 6 where the system will generate a ‘1’ to mark the end of a subgroup. The system will then return back to State 2 to check whether the total decoded size has already reached the original file size or not and the process cycle continues.

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G.H. H’NG, M.F.M. SALLEH, Z.A. HALIM / ELEKTRIKA, 10(2), 2008, 36-40

Figure 10.

4. RESULTS In this section, the designed Golomb encoder and decoder algorithms implementation on FPGA are simulated and verified for their validity. Firstly, the implementation of Golomb encoder shown in Figure 6 was simulated using ALTERA Quartus II software with 10 bytes sample data, 0x00, 0x01, 0x10, 0xA0, 0x50, 0x88, 0x10, 0x00, 0xAB and 0x10. The simulated result is shown in Figure 8. Extra four bytes of data size header were added. From the observation of the simulation diagram of Figure 8, input data signal of data_in will only be accepted by the system if data_in_enable signal is asserted HIGH. Data will only be accepted when the system is not busy, in other words, the signal busy is asserted LOW. This is to avoid the system from being flooded with data when the system is not ready for the next data. Output data signal of data_out is only valid when the data_out_enable signal is asserted as HIGH. The output data of data_out are colour marked in multiple of 8 bits for the ease of observation. The expected output is shown in Figure 9 and the expected output is compared with the simulated output. It is shown that the simulated conforms to expected output, thus showing the design is valid. Note that the last subset of the input is encoded with an extra ‘1’ to complete the encoding process and the last byte of the output in Figure 9 is padded with ‘0’s as shown in Figure 8 where the last output byte is padded with extra five ‘0’s to complete a byte. The output result generated by the Golomb encoder which are 0xED, 0xC1, 0xA3, 0x0E, 0xB8, 0x24, 0x87, 0x00 were than being used as the input of the Golomb decoder to determine whether the original test data will be managed to be obtained back after the decoding process. The simulated result is shown in Figure 10. The first four bytes of the input data is the original file size header bytes. From the observation of the simulation diagram of Figure 10, like the Golomb encoder algorithm, input data signal of data_in will only be accepted by the system if data_in_enable signal is asserted HIGH. Data will only be accepted when the system is not busy, in other words, the signal busy is asserted LOW. This is to avoid the system from being flooded with data when the system is not ready for the next data. Output data signal of data_out is only valid when the data_out_enable signal is asserted as HIGH. The output data of data_out are colour marked in multiple of 8 bits for the ease of observation. The simulation output of the Golomb Decoder shows that the system managed to regenerate the original data set using the encoded data. The data size regenerated matches the total size of the original data set of 10 bytes as shown in

5. CONCLUSION Through simulation of the Golomb Coding, it can be concluded that the algorithm of Golomb Coding on FPGA had been successfully developed. This had been proven by comparing the results generated using simulation of the Golomb Encoder with the expected results which showed both of the results were identical. The use of encoded data as the input data for Golomb Decoder managed to generate back the original data proved that the Golomb Decoder System was also successfully developed. Hence, the whole system of Golomb Coding was completed. ACKNOWLEDGMENT The authors are grateful to the Universiti Sains Malaysia for funding this work via short term grant. REFERENCES [1] M. Ghanbari, Video Coding an Introduction to Standard Codecs. London: The Institution of Electrical Engineering, UK, 2003. [2] T. Sikora, “Trends and perspectives in image and video coding,” Proceedings of IEEE, vol. 93, no. 1, pp. 6-17, Jan 2005. [3] S. W. Golomb, “Run Length Encodings,” IEEE Transactions on Information Theory, vol. 12, pp. 399-401, 1966. [4] I. H. Witten, R. M. Neal, and J. G. Cleary, "Arithmetic Coding for Data Compression" CACM Journal, vol. 30, no. 6, pp.520–540, June 1987. [5] J. Ostermann, J. Bormans, et al, “Video coding with H.264/AVC: Tools, Performance, and Complexity,” IEEE Circuits and System Magazine, Vol. 4, No. 1, pp. 7-28, First Quarter 2004. [6] T. Silva, et. al., FPGA based design of CAVLC and Exp-Golomb coders for H.264/AVC baseline entropy coding,” Proc 3rd IEEE Southern Conference on Programmable Logic, pp. 161-166, Feb 2007. [7] A. Chandra and K. Chakrabarty, “System on-a-chip test data compression and decompression architectures based on Golomb codes,” IEEE Trans. Computer-Aided Design, vol. 20, pp.355-368, Mar. 2001. [8] J. M. Jung, and J. W. Chong, “Efficient test data compression and low power scan testing in SoCs,” ETRI Journal, vol. 25, no. 5, pp. 321- 327, Oct 2003. [9] Quartus II development software literature, available at http://www.altera.com/literature/lit-qts.jsp.

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Figure 8. Simulated waveform of Golomb encoder 00000000 00000001 00010000 10100000 01010000 10001000 00010000 00000000 10101011 00010000 Input Subset Expected Output 0000000000000001 111011 0001 011 00001 1000 01 001 0000001 1010 01 001 00001 1000 0001 011 0000001 1010 0000000000001 111000 01 001 01 001 01 001 1 000 0001 011 0000(1) 1000 11101101 11000001 10100011 00001110 Output 10111000 00100100 10000111 000 Input

Figure 9. Expected output of simulation

Figure 10. Simulation waveform of Golomb decoder 40