Grid-Synchronization Methods for Power Converters - IEEE Xplore

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Grid-Synchronization Methods for Power Converters Francisco D. Freijedo, Jesus Doval-Gandoy, Oscar Lopez, Carlos Martinez-Pe˜nalver, Alejandro G. Yepes, Pablo Fernandez-Comesa˜na, Jano Malvar, Andres Nogueiras, Jorge Marcos and Alfonso Lago. . Department of Electronic Technology, University of Vigo, ETSEI, Campus Universitario de Vigo, 36200, Spain. Email:[email protected]

Abstract—Grid synchronization is an important part in the control of grid-connected power electronic converters. The fundamental phase-angle at the point of common coupling should be tracked on-line in order to control energy transfers. Digital implementation allows to implement high performance algorithms, which are robust in the presence of power quality phenomena. However, different kinds of distortion cause a reduction of the effective bandwidth, and hence, affects to the transient response of the equipment. This paper reviews some of the highest performance algorithms for grid synchronization: phase locked loops (PLL), schemes based on synchronous reference frames (SRF) and digital filtering and finally, stochastic filtering based methods. The pros and cons of each one are assessed and some interesting techniques to enhance the dynamics are provided. The assessment in the presence of frequency deviations is analyzed in detail. The most significant techniques to provide a better frequency adaptation are enumerated and analyzed in the last section of this paper.

vi

vo

Fig. 1.

Loop Filter

Voltage Controlled Oscillator Zˆ1 Z1n  K vco vco

T1 Z1t  M1

PD +-

vco

T1e

Loop Filter

Tˆ1 Zˆ1t  Mˆ1

'Zˆ1

VCO

Z1n

+ +

S

³

Zˆ1

S

(b) Linear model of a PLL.

Basic conceptual models of PLLs.

The fundamental frequency and phase-angle of vi are ω1
and θ1 ; they are related by θ1 = ω1 t + ϕ1 where ϕ1 is an offset dc constant. In the same way, the output signal vo parameters are the estimated values of vi : ω ˆ 1 , θˆ1 and ϕˆ1 . The PLL scheme is composed by three basic functional blocks: the phase detector (PD), the loop filter (LF) and the VCO. The role of each block could be summarized as follows:

I. I NTRODUCTION

• •

The PD is a circuit for which the average value of its output, averaged each cycle of the fundamental component of the input, is zero only when the input signals are in-phase, that is, they are synchronized both in phase ω1 = ω1 ). (θˆ1 = θ1 ) and frequency (ˆ The LF supplies a filtered control signal (vco ) to the VCO. It sets the dynamics of the system. The VCO generates a signal of frequency ω ˆ 1 from its central frequency, which, in grid-applications is usually adapted to the nominal (ω1n ) 1 , and vco ; Kvco is a VCO constant, so that ω ˆ 1 = ω1n + vco · Kvco .

PLLs should be linearized in order to study the dynamics and tune the LF. This process is done assuming that the PLL ˆ 1 and θi ≈ θˆ1 [4], [5]. is near locked state, that is, ω1 = ω Under such a situation, the equivalent system is the linear PLL (LPLL) of Fig. 1b. The LPLL is a typical closed loop servo system. The instantaneous phase-angle error at the fundamental component is θ1e = θ1 − θˆ1 and θ¯1e its average value 2 . The LF path provides a frequency correction around the nominal (central) frequency (∆ˆ ω1 ) and hence, establishes the dynamics. When designing a PLL, the most important features are: 1) Stability: the LPLL stability margins should be high. 2) The “type” of the PLL: it is set by the number of poles at the origin of the equivalent LPLL. A type 2 PLL

II. P HASE L OCKED L OOPS Fig. 1a shows a simplified PLL scheme. A PLL is a nonlinear circuit which synchronizes its output signal (vo ) with a reference or input signal (vi ) in frequency as well as in phase. 978-1-4244-4649-0/09/$25.00 ©2009 IEEE

ve

(a) Block diagram of a PLL.

•

To control energy transfers between a grid-connected power converter and the ac-mains requires an on-line tracking of the fundamental component voltage (or current) phase-angle. This estimation is needed to calculate suitable firing signals. The very first proposed synchronization schemes were zerocross detectors; the presence of power quality phenomena, specially in weak-grids, led to malfunctions in zero-cross based controllers [1]. The use of voltage controlled oscillators (VCOs) resulted in more robust controllers such as the Phase Locked Oscillator [1] system and the Charge-Pump PLLs [2]. With the suitability of discrete devices such as microcontrollers the number of synchronization algorithms and filtering techniques have grown drastically, in parallel with the appearance of high performance applications (high bandwidth) and new technical requirements in fields such as renewable energy applications, traction systems and power line conditioners. Digital PLLs and other algorithms implementing stochastic and/or FIR filters, which are reviewed in this paper, are clear examples of the high performance offered by digital implementations.

Phase Detector

522

1 E.g. 2 The

in Europe ω1n = 2π50 rad/s [3]. accent¯refers to average values.

(two origin poles) is necessary to assure θ¯1e = 0 when frequency deviations are considered [4], [5]. 3) The LPLL bandwidth sets: • The transients response. The higher the bandwidth, the faster the PLL re-tracks the phase-angle. • The harmonic/noise filtering. The presence of noise and harmonics in the inputs affects the PLL measurements. The term “phase jittering” is employed by Best and Gardner to refer to the effect of noise in the phase estimation: phase jittering (θ1ej ) is the error in the value of θ1e during zero crosses due to noise 3 . In a general way, the average value 2 2 (θ¯1ej ) is inversely proportional to the PLL of θ1ej bandwidth [4], [5].

vb vc

     vα cos (θˆ1 ) sin (θˆ1 ) vd1+ · = , vβ vq1+ − sin (θˆ1 ) cos (θˆ1 )         



+ vdq1

B+ 1

(1)

vαβ

where ⎞ ⎛   va 1 1  − 1 − 2 vα √2 √2 · ⎝ vb ⎠ . = 3 vβ 3 0 − 23 2 vc          vαβ C

vD

C

B1

vE

Tˆ1

vd1  f (hZ1 ) LOOP FILTER

'Zˆ1

³ Zˆ t  Mˆ 1

Fig. 2.

Zˆ1

³S



SRF-PLL of [6] block diagram.

PD

va vb vc

C

vE

vd1  f (hZ1 )

vD

vD

Q

vE

B

vq1  f (hZ1 ) LOOP FILTER

Tˆ1 Zˆ1t  Mˆ1 DCO

Fig. 3.

Z1n

+ +

S

1

DCO

A. Synchronous Reference Frame-PLL (SRF-PLL or dq-PLL) Fig. 2 shows the basic SRF-PLL, proposed in [6]. The main feature of the SRF-PLL is that it estimates the phase-angle of + + + + = [va1 , vb1 , vc1 ]): the fundamental positive-sequence (vabc 1 + ˆ the estimated phase-angle (θ1 ) corresponds with va1 phaseangle. The Park’s transformation is employed as PD:

PD

va

'Zˆ1

Z1n

+ +

S

³S

Zˆ1



SRF-PLL with pre-filters, as proposed in [14]–[17].

systems could not have a physical neutral connection. This is not a problem, but an advantage: phase to phase voltages can be employed in order to reduce the number of voltage sensors (from 3 to 2) and components of C matrix (only 3 non-zero coefficients): eq. (1) can be rewritten as:efficients): eq. (1) can be rewritten as:



⎞ ⎛  va − vc vα = C · ⎝ vb − vc ⎠ , vβ vc − vc = 0       vαβ

(2)



vabc

The estimated phase-angle θˆ1 is employed to generate B+ 1. + The whole Park’s matrix is P+ 1 = B1 · C. The SRF-PLL is implemented in a digital device: a digital controlled oscillator (DCO) substitutes the VCO circuit. For the SRF-PLL linearization, the system is considered ˆ 1 and θ1 ≈ θˆ1 , and around the tracking point, that is, ω1 = ω also balanced inputs [6]. Under such a situation: vd1+ = va1max sin(θi − θˆ1 ) ≈ va1max · θ1e ,

(3)

+ + + + (= vb1 = vc1 ) being the peak value of va1 , va1 max max max + which is usually rearranged so that va1max = 1 p.u.; this eases the tuning [7]. It is expected v¯d1+ , which represents θ¯1e , to be zero in steady-state. It should be noticed that SRF-PLL implementation, that is P+ 1 matrix, is not unique. Depending on the initial theoretical approach, d or q components can be employed as error signal [6], [7]. The other component, q or d, can be employed to + . estimate va1 max + is It should be noticed that the zero-sequence of vabc eliminated in (2). In fact, several three-phase and three-wire 3 Even though in electric power applications a difference is made between harmonics and noise, in terms of PLL theory they are the same.

978-1-4244-4649-0/09/$25.00 ©2009 IEEE

(4)

Line to line voltages

being the implemented PD optimized accordingly. The field of application of the SRF-PLL, and equivalent implementations, is very wide and, hence, its optimization has been approached in several works [8]–[14]. The SRF-PLL should be tuned taking into account the level of distortion since there is a trade-off between filtering and transient response. A very interesting feature of the SRF-PLL is that, under non distorted conditions, the SRF-PLL can be tuned with a very high bandwidth, which implies almost instantaneous retracking (after a transient) [6]. The tuning of the SRF-PLL taking into account the distortion and how to deal with it by discrete filters is approached in [7]. 1) Pre-filters for the SRF-PLL: In order to improve the whole dynamics of the SRF-PLL some authors have proposed the use of “pre-filters”, which act in a rotating reference frame (vabc or vαβ ), as shown in Fig. 3. In this manner, the input of the SRF-PLL is cleaner and therefore, it can be tuned with a higher bandwidth [14]–[17]. From symmetrical components theory, the fundamental positive-sequence is obtained through the Q+ matrix as

523

va ( p.u.)

PD

T1e

X

+ +

LOOP FILTER

Z1n DCO

cos(Tˆ1 ) sin(Tˆ1 ) Fig. 4.

cos(u)

Tˆ1

S

Zˆ1

³

S

sin(u)

Tˆ1

Single-phase PLL with multiplier as PD.

     1 vα+ vα 1 −j = · . vβ+ vβ j 1 2      



+ vαβ

(5)

Q+

Equivalent implementations in the abc frame (S matrices) are provided in [14], [15]. The advantage of αβ frame is the lower size of involved matrices. The technical difficulty in the implementation of Q+ (and S) is to implement the complex unit j, which corresponds with a +90 deg shift. All-pass filters, pure delays (delayed cancellation (DSC) method) and damped generalized integrators (GI) can be designed to lag exactly 90 deg at ω1n [15]–[17]; GIs offer a better filtering than the others but their transient lags around a cycle of ω1n [17], [18]. Due to the linear-phase of delays, the DSC method also results in cancellation of some harmonic sequences. On the other hand, several cascaded DSC matrices can be implemented. De Souza et al generalized the DSC method to provide a selective harmonic sequence cancellation [14]. A problem of pre-filters in rotating frames appear when frequency deviations are taken into account, which is dealt with in section V. B. Digital Single-phase PLL The suitability of digital implementation allows to implement PDs better than Charge-Pumps. From PLL theory [4], [5], the “linear multiplier” PD seems to be the most intuitive option [13], [19]–[21]. Fig. 4 shows a simple single-phase PLL scheme based on linear multiplier as PD. Other interesting alternatives for single-phase PLL implementation have been proposed, such as: • The adaptation of the SRF-PLL to single-phase systems [22]–[25]. • The implementation of more complex PDs [26], [27]. However, all single-phase PLLs for grid applications need of a drastic bandwidth reduction due to the PD non-linearities, more specifically the internal generation of harmonics at 2ω1 . Therefore, grid-connected single-phase PLLs should not be considered “fast”, so that they are “low-gain” PLLs. In fact, their typical settling times are not lower than 1 cycle of ω1n [13], [20], [25]–[28]. C. Single-phase PLLs Vs SRF-PLLs As said, in a three-phase system the SRF-PLL estimates + the phase-angle of va1 . On the other hand, a single-phase PLL connected in the a-phase tracks the phase-angle of va1 . 978-1-4244-4649-0/09/$25.00 ©2009 IEEE

Therefore, it seems that SRF-PLLs are more reliable when SRF controllers (e.g. dq current controllers [29]) are employed. That is, the use of single-phase PLLs in the presence of negative/zero sequences may result in θ¯1e = 0 when tracking the positive-sequence, which may lead to a non efficient energy transfer control. Some works have proposed the use of single-phase PLLs instead of SRF-PLLs, since a SRF-PLL cannot detect individual phases [20], [27]. Even though this assessment could be right, SRF controllers do not seem the most suitable to work together with single-phase PLLs. This point should have been clarified by those authors. It could be said that single-phase PLLs are more suitable for single-phase circuits and, perhaps, for some three-phase circuits with perphase controllers. Other authors suggest a per-phase estimation of va1 , vb1 and vc1 phase-angles and amplitudes in order to calculate the + [26]. Even though this is feasible, there is phase-angle of va1 no apparent reason to use individual single-phase PLLs, since the phase-detector of the SRF-PLL (P+ 1 ) totally decouples the + + only depends on vabc . positive-sequence: the dc value of vdq1 1 D. Amplitude Compensation in Digital PLLs When considering amplitude variations such as voltage sags and swells, the drawback of amplitude dependence in PLLs appears: e.g. from (3), it is clear that the dynamics of digital PLLs depends on the amplitude of the tracked signal. In practice, the most reported problem is due to the slow dynamics in the presence of voltage sags [14], [20], [30]. This amplitude dependence can be avoided in part by compensating the PLL input with an amplitude estimation. However, the range of improvement achieved with this technique could be considered quite small: the bandwidth is limited by the first harmonic, usually the one at 2 · ω1 . Other problems due to non-linearities may appear: e.g. division by zero [30]. E. Alternatives to Digital PLLs The main drawback of PLLs is their transient response speed, specially in the presence of distorted conditions, which reduces the effective bandwidth (transient response) of power electronic converters [31]. The amplitude-dependent dynamics is also a drawback of PLLs. Digital implementation allows to implement very high performance synchronization algorithms without a DCO inside a closed-loop. The next sections deal with some significant alternatives to PLLs. III. F ILTERING IN S YNCHRONOUS R EFERENCE F RAMES Digital devices allow to handle electrical variables in SRFs. The main advantage of SRFs is the suitability of controlling oscillating waves as dc signals. This is a big advantage under the designer point of view, since low order infinite impulse response (IIR) filters (Chebishew, Butterworth), Proportional Integrator (PI) and lag/lead controllers, etc, perform much better with dc signals [29], [32]. In this section the basics of SRF synchronization schemes are reviewed (open loop operation). Frequency adaptation is dealt with in section V.

524

Z1

 vq1

S

Z srf

³

sin(u)

S

T srf

³Z

srf

v

d

t  M srf

Open Loop Synchronous Reference Frame generation

X

X

2·H(z)LPF

f (dc,2Z1 ,4Z1 ,...) f (dc)

X

cos(u) q

2·H(z)LPF 

Ȉ

+ + vq1 , vˆd1 ), θˆ1 = θsrf + atan2(ˆ   

vˆ1

β (relative angle)

and

X

vd 1 + vˆa1 = max

Fig. 5. Single-phase SRF synchronization algorithm: ωsrf = ω1 to decouple v1 . SRF-MAF1 when the LPFs are MAFs.

f (dc, Z2 , Z4 ,...)

va

H(z)LPF

vb

P1+

vc

T srf

S

Z srf

³

S

Z1

H(z)LPF

vˆd1 vˆq1 P + (-1) 1

(10)

vˆa1 vˆb1 vˆc1



2

2

+ + vˆd1 + vˆq1 .

(11)

The phase-angle estimation can also me made by using the + angle transform B+(−1) to get vα1 and vβ+ [34], so: + + θˆ1 = atan2(ˆ vα1 , vˆβ1 ) ∈ [−π, π].

(12)

B. Harmonics and Negative-sequences Extraction in SRFs

Zsrf t  M srf

Open Loop Synchronous Reference Frame Generation

Fig. 6. Three-phase SRF synchronization algorithm; ωsrf = ω1 to decouple + . SRF-MAF3 when the LPFs are MAFs. vabc 1

Previous approaches showed how to decouple the fundamental component of single-phase signals and the fundamental positive-sequence of three-phase systems. In the same way, higher harmonic components can be decoupled using the expression ωsrf = hω1 , where h is the order of the selected harmonic. Negative-sequences can be decoupled by means of P− and its inverse. [33]. C. Moving Average Filters (MAFs) for SRF based schemes

A. Single-phase SRF Synchronization Algorithms Fig. 5 shows a generic SRF scheme suitable for v1 reconstruction [33]. The goal of the SRF algorithm is to estimate v1d and v1q . The frequency of the implemented SRF (ωsrf ) sets the component to reconstruct, so ωsrf = ω1 should be set in order to track v1 . In such a situation, vd1 and vq1 are dc coefficients, which can be obtained with no ripple by means of LPFs; the system dynamics only depends on the LPFs. The estimated phase-angle of v1 (θˆ1 ) is: vq1 , vˆd1 ) , θˆ1 = θsrf + atan2(ˆ   

As shown, the LPFs set the dynamics of SRF based schemes; therefore, the LPFs set the amplitude versus frequency response trade-off. MAFs have been implemented in electric power applications because of their excellent behavior canceling for harmonics and fast transient response [35]. With regard to grid-synchronization, MAFs together SRF have been proposed in [33], [34]. SRF-MAF1 and SRF-MAF3 refers to Figs. 5 and 6 with MAFs, respectively. Even though MAFs have finite impulse response (FIR) they can be implemented as an IIR structure by

(6) H1 (z) =

β (relative angle)

where β is a relative phase-angle in the SRF and θsrf the SRF waves phase-angle. The explicit dependence in θsrf can be made by reconstructing with 90 deg leading v1 : vˆ1+90 = −ˆ vq1 · sin(θsrf ) + vˆd1 · cos(θsrf ),

(7)

v1 , vˆ1+90 ). θˆ1 = atan2(ˆ

(8)

so

v1max is estimated by: vˆ1max =

2 +v 2 . vˆd1 ˆq1

(9)

1) Three-phase SRF Synchronization Algorithm: Fig. 6 shows a SRF based synchronization scheme for three-phase systems [33]. P+ is implemented with a random phase-angle offset; ωsrf = ω1 should be chosen in order to decouple the fundamental positive-sequence. LPFs are employed to cancel + + and vq1 ; again the dynamics ripple from the dc coefficients vd1 only depends on them. + The phase-angle and amplitude of vabc are estimated by 978-1-4244-4649-0/09/$25.00 ©2009 IEEE

1 1 − z −n . n 1 − z −1

(13)

The magnitude versus frequency response of H1 (z) is mathematically described by the Fourier transform of a rectangular pulse of amplitude 1/n and duration n samples in the time domain: 

n sin( πf fs ) , (14) M ag [H1 (f )] = M ag n · sin( πf fs ) where f is defined in the range [0, fs /2] [36]. In grid applications, a cancellation of the even harmonics of f1 = f1n = 50 Hz is expected (100, 200, ... Hz). From (14), the n value canceling all the even harmonics is derived: n=

fs , 2f1n

(15)

n being an integer number, since it sets the order of a digital filter; hence, fs should be integer multiple of 2f1n . A MAF with fs = 10 kHz and n = 100 is very suitable for synchronization, specially compared with IIR LPFs, since it cancels the even harmonics of the SRF and its settling time is ≈ 0.01 s [33], [34].

525

Magnitude (dB)

10

response does not seem an important issue in those works. However, for electric power applications, the performance of FIR based implementations results in a much better filtering versus transient response trade-off.

0 n=100 n=200

-10 -20 -30

IV. S TOCHASTIC F ILTERS FOR S YNCHRONIZATION : W EIGHTED L EAST-S QUARES E STIMATION (WLSE)

-40 -50

Phase (deg)

180

90

0 -90

-180 0

50

100

150

200

250

300

350

400

450

500

Frequency (Hz)

(a) SRF-MAF1 with n = 100 and n = 200 (=RDFT of [37]); ωsrf = ω1n .

Fig. 7.

DCT based implementation figures.

D. Equivalent Implementations It should be commented that, even though the theoretical approach proposed by McGrath et al in [37], based on a Recursive Discrete Transfer Function (RDFT) and SRF-MAF1 are different, their implemented schemes could be considered equivalent (Fig. 5 vs Fig. 2 of [37]). It can be checked analytically that, even though both schemes (for reconstruction of v1 ) seem to be non-linear, they could be also implemented as linear filters based on the Discrete Cosine Transform (DCT): n−1 2 cos(ω1 · k · Ts ) · z −k . HDCT (z) = n

Stochastic filters can be implemented to synchronize with fundamental and harmonics [40]–[44]. Song et al proposed the implementation of a recursive least squares (RLS) adaptive filter, named Weighted Least-Squares Estimation (WLSE), adapted to the synchronization problem both for single-phase and three-phase systems [42]–[44]. The WLSE algorithms approach the problem of synchronization in an elegant way, so that the dynamics of the system mainly depends on the socalled forgetting factor λ. The WLSE has been chosen in this work as a representative algorithm in stochastic filtering. In [42], the problem of phase-angle estimation of a three-phase input signal (vabc ) is posed relating the SRF with the αβ frame as follows. Considering only the fundamental component of vabc , it can be expressed in the αβ frame T vαβ = C · vabc .

vαβ has information of positive and negative sequences. In order to decouple negative from positive-sequence of the fundamental component the angle transformations are employed: the matrix H is implemented:   −(−1) , (18) H = B+(−1) B 1 1 so

(16)

+−T vαβ = H · vdq1 ,

k=0

HDCT (z) taps can be also obtained through the impulse response of SRF-MAF1 (or RDFT-based). Fig. 7a shows the frequency response of the DCT filters obtained from SRFMAF1 with n = 100 and n = 200, which is equivalent to the RDFT based scheme of [37]. As expected, the double window length provides a better filtering at the cost of doubling the transient time. It is a common practice to neglect even harmonics in system voltages/currents, which is accurate for the most of practical electric circuits [38]. Therefore, it could be said that SRFMAF with n = 100 seems to be a more efficient alternative. Indeed, it takes advantage of the potential DCT half-cycle window, which is the main advantage of the DCT over the DFT. Another advantage of the DCT (half cycle) over DFT appears when frequency deviations are considered : as can be observed in Fig. 7a, when the input wave is not rotating at nominal frequency DFT (or DCT with n = 200) phase error doubles the DCT one. On the other hand, several works in other signal processing fields (image, speech, communications,...) proved that the IIR equivalent implementation to a DCT are GIs, as the ones of section II-A1 [39]. The main advantage of such IIR over FIR filters appears mainly when considering very large scale integration (VLSI) implementations; the transient 978-1-4244-4649-0/09/$25.00 ©2009 IEEE

(17)

(19)

where +− = vdq1 + + − vd1 , vq1 , vd1



+ vd1

+ vq1

− vd1

− vq1



,

(20)

− vq1

and being the components of vabc1 in the positive and negative SRFs. The sequential recursive computation steps (k = 1, 2, ...) for +− the WLSE estimation of vdq1 , and hence the phase-angle from vabc1 are detailed below. A initial error covariance (p(k = 0)) is set for the first sample (k = 1). 1) Compute of vαβ with eq. (17). 2) Update H. 3) Compute of r Matrix:

526

r = I + H · p(k − 1) · HT .

(21)

4) Compute of K gain: K = p(k − 1) · H · r(−1) .

(22)

5) Update the error covariance matrix p(k): p(k) = λ−1 · p(k − 1) · (1 − K · H).

(23)

+− : 6) Update the estimation of vdq1 +− +− +− ˆ dq1 ˆ dq1 ˆ dq1 (k) = v (k − 1) + K · (vαβ − H · v (k − 1)). v (24)

1

Vb

1

Va

1

VĮ

1 Va Amplitude (p.u.)

Amplitude (p.u.)

Amplitude (p.u.)

Amplitude (p.u.)

0

0

0

Vc 0.03

0.04

0.05 Time (s)

0.06

Vc 0.07

0.08

0.09

0.1

0

0.01

^ Vd1+

Amplitude (p.u.)

0.01

0.02

0.03

0.04

Amplitude (p.u.)

^ Vq1-

^ Vd10

0.05 Time (s)

0.06

0.05 Time (s)

0.07

0.06

0.07

0.08

0.09

0.1

0.01

0.02

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0.09

0.1

^ Vq1-

^ Vd1-

0.01

0.02

0.03

0.04

0.05 Time (s)

Phase-angle (rad)

1

^ ș1 0 -1

0.08

0.06

0.07

0.08

0.09

+(-1)

-1 0

0.1

^ ș1

Fig. 8.

0.02

0.03

0.04

0.05 Time (s)

0.06

0.07

0.08

0.09

0.1

-3 0

-(-1)

0.02

0.03

0.05 0.06 Time (s)

0.04

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0.07

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-0.5

0.02

0.05 0.06 Time (s)

0.03

0.04

+(-1)

0.07

0.08

0.09

0

0.1

0.01

0.02

3

-(-1) 1

1

+(-1)

^ ș1

-1

-(-1) 1

1 0.03

0.05 0.06 Time (s)

-(-1) 1

1

-(-1) 5

0.04

+(-1) 1

2

+(-1) 5

+(-1) 5

0.07

0.08

0.09

0.08

0.09

0.1

-(-1) 5

^ ș1

0 -1

-2

0.01

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0.03

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0.06

0.07

0.08

0.09

0.1

-3

0

0.01

0.02

0.03

0.04

0.05 0.06 Time (s)

0.07

0.1

Fig. 9. WLSE Simulation Results at fs = 10 kHz. Effect of adding extra sequences to H.

WWLSE Simulation Results at fs = 10 kHz for different λs.

+ + Once estimated vd1 , vq1 , phase-angle and amplitude are assessed. Fig. 8 shows simulation results of the WLSE algorithm obtained by Matlab. It can be noticed that the transient response is very good and it does not have ripple under unbalanced conditions. The transient response could be even improved by the covariance reseting technique proposed in [42]. Fig. 9 shows simulation results of adding extra sequences to H when dealing with harmonics in the input, since the simple implementation identifies the 5th harmonic as noise and λ should be reduced in order to filter it. The second option is to add positive and negative sequences of the 5th harmonic to H: positive and negative sequences of 5th harmonics are decoupled and a big λ value can be kept. In general, big H matrices have been proposed for harmonic extraction [40], [41]. As shown, it is also an interesting option in synchronizations when a high bandwidth working in a distorted environment is desired. The effect of frequency deviations in stochastic filters is considered in the next section.

V. F REQUENCY A DAPTATION OF S YNCHRONIZATION A LGORITHMS The study of the linearized model of PLLs provides an accurate assessment of dynamics. However, studies of the dynamics provided for other schemes are not as deep and accurate as the provided by PLL theory. Section II revised the criteria followed to assess the performance of PLLs. Following the same criteria, any synchronization algorithm should have: 1) high stability margins, 2) a fast transient response, 978-1-4244-4649-0/09/$25.00 ©2009 IEEE

0.05 Time (s)

-1

0

0

0.1

0.04

^ Vq1+

0

-1.5

-3 0.01

0.03

0.5

^ Vq1-

^ Vd1-

1

1

2

0.02

^ Vd1+

1

-2 0.01

0.01

1.5

-2

0.01

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3) zero steady-state average phase error (θ¯1e = 0), and 2 ), 4) low phase jittering (low θ¯1ej in order to be considered a high performance algorithm. Alternative synchronization algorithms have a better performance on the whole than PLLs when working around nominal frequency (ω1 ≈ ω1n ). However, this assertion should be reconsidered in practical operation. Faults on the bulk power transmission system, a disconnection of a large load or of a large source of generation cause frequency deviations (from ω1n ). These frequency shifts are larger in equipment powered by isolated generators. The European Standard UNE-EN 50160, which sets f1n = 50 Hz, establishes limits in maximum allowable frequency deviations. For interconnected systems the mean value of f1 , estimated each 10s should not exceed ±1% ([49.5, 50.5] Hz) during the 99.5% of a week, but exceptional deviations between +4% and −6% are permited. For isolated systems, normal operation of ±2% and exceptional deviations of ±15% are specified [3]. The IEC-61000 Standard sets the normal limit operation in ±2% for interconnected system and extends these limits for isolated systems [18]. When ω1 = ω1n , it should be noticed that:

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• •

•

Digital PLLs using a lag/lead filter, as proposed e.g. in [9], would not have θ¯1e = 0 (type I PLLs) [4], [5]. SRF-PLL pre-filters could lead to θ¯1e = 0 in steady-state when ω1 = ω1n : some of these filters (e.g. D(z)) do not delay exactly 90 deg at f1 = f1n . SRF and filtering, and WLSE algorithms do not have θ¯1e = 0 when ωsrf = ω1 because of the filtering delay. This phase error is:

θˆ1e = (ω1 − ωsrf ) · td (f1 ),

(25)

where td (f ) is function of the input frequency (phase response), except for linear phase filters [34], [37]. In the case of the WLSE td is lower as faster is the system (e.g. in the WLSE algorithms, the lower λ the faster the system, so the lower td ). • FIR filters such as numeric delays (e.g. D(z)) and MAFs do not achieve complete harmonic cancellation, which causes phase jittering. The issue of frequency adaptation has been posed by most of the authors proposing novel synchronization algorithms: • The use of PLLs to get frequency adaptation has been proposed to work SRF schemes [33], [45]. These hybrid schemes enhance their whole performance using the frequency estimation from PLLs to adapt internal signal and/or filter coefficients. • The update of the sampling rate of the digital device was proposed in the RDFT algorithm of [37] and also in the single-phase PLL of [21]. Zero steady-state phase error and low jittering is achieved. However, technical problems could appear, since the frequency response of discrete filters is changing continuously [37]. An alternative phase-offset correction technique is provided in [37]. In the case of a PLL, a closed loop system, this limitation seems to be very important and the PLL should have a very low bandwidth, and hence, a slow transient time, as shown in Fig. 14 of [21]. • GI discrete-time implementation can be updated using ω ˆ1 as proposed in [46] for PR current controllers. This has been applied in synchronization algorithms to avoid phase error and/or jittering [17], [18]. • Svensson and Bongiorno have studied the frequency adaptation of DSC filters. The choice of the device sampling rate is very dependent on the grid frequency [47]. In [48] a very similar technique to the phase-offset correction of [37] is provided for DSC implementation. The choice of the sampling frequency is also very critical in the generalized DSC [14]. • A purely open loop frequency adaptive SRF system working open loop is provided in [34]. The combination of MAF and predictive filter compensating for delays results in a no-delay filtering stage. With this technique, the settling time is kept in half a fundamental cycle.

From Figs. 8, a large λ provides very good filtering but slow dynamics. Song et al solved this problem by the so-called “covariance resetting technique”, which resets the covariance p to initial values when a grid fault is detected. In this manner, it is achieved an excellent transient and steady-state (filtering) responses. However, this approach has a drawback considering frequency deviations: even though the WLSE in the form proposed by Song et al has a fast transient response (when fault condition is correctly detected), in steady-state the WLSE is tuned with slow dynamics. Frequency deviations do not reset the covariances so the system dynamics remains very slow. Therefore, it could be said that the “covariance resetting” technique does not seem a good choice when considering considerable frequency deviations. The trade-off between frequency resolution and transient response in stochastic based synchronization methods has also been reported in [41]. VI. C ONCLUSION This article provides an in-depth review in grid synchronization, summarizing some of the most significant works existing in the literature. Digital PLLs are the most widespread synchronization algorithms due to its simplicity, good frequency adaptation and acceptable filtering versus transient response, specially when taking advantage of discrete-time implementation (discrete filters for harmonics). The limitations of PLLs tracking distorted signals may appear in applications requiring a fast transient response, such as Dynamic/Series Voltage Restorers, Uninterruptible Power Supplies and monitoring in Distribution Generation Systems. SRF-MAF and WLSE algorithms, implemented at fs inside the range [5 − 20] kHz, optimize the filtering versus transient response trade-off: after a grid fault, SRFs implemented with MAFs can re-track completely in half a cycle of the fundamental frequency. The settling time can be even reduced by means of WLSE. However, SRF-MAF and WLSE algorithms have a worse frequency adaptation than PLLs. The different techniques to provide a better frequency adaptation in discrete implementations have been reviewed in section V: hybrid systems using PLLs to track frequency, update of coefficients on-line and use of predictive FIR filters.

A. Frequency Adaptation in WLSE Schemes Dealing again with the WLSE synchronization algorithm, Song et al proposed a PI based controller to correct the estimated frequency. The input of that PI was the phase offset error between two consecutive samples. It should be noticed that the frequency adaptation of the WLSE results in a very slow dynamics (≈ 2 s) when compared with phase-jump and amplitude-change transients (≤ 1 ms) [42], [43]. This problem has also been reported in [12]. The main reason of this slow response is the very big forgetting factor (λ = 0.9999) employed in the implementation. 978-1-4244-4649-0/09/$25.00 ©2009 IEEE

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