Grounded-capacitor SRCOs using a single differential difference complementary current feedback amplifier S.S. Gupta and R. Senani Abstract: The usefulness of a new active building block, the ‘differential difference complementary current feedback amplifier’ (DDCCFA) in realising single resistance controlled oscillators (SRCO) employing grounded capacitors has been demonstrated and using a state-variable methodology, a number of new single DDCCFA-based SRCOs have been derived. It is shown that the new SRCOs possess features, all of which are not available simultaneously in any single active building block-based SRCOs known earlier. The workability of the proposed circuits has been varified by SPICE simulations using a DDCCFA implementable in 0.35 micron CMOS technology.
1
Introduction
There has been considerable interest shown in realising canonic single resistance controlled oscillators (SRCO) using a single active building block (ABB) due to the advantages of lower cost and lower power consumption [1– 26]. Consequently, single ABB-based canonic SRCOs have been devised using a variety of building blocks, such as opamps [1–5], various forms of current conveyors (CC) [6–11], four terminal floating nullors (FTFN) [12–16], operational transresistance amplifiers (OTRA) [17], current feedback operational amplifiers (CFOA) [18–21], current differencing buffered amplifiers (CDBA) [22], differential voltage complementary current conveyors (DVCCC) [23], differential voltage current feedback amplifiers (DVCFA) [24], operational transconductance amplifiers (OTA) [25] and fully differential second generation current conveyors (FDCCII) [26]. Apart from their usual applications as variable frequency sine wave generators, SRCOs may also be employed in voltage-controlled oscillators (by employing a voltage-controlled resistor in place of the frequency controlling resistor) and in some measurement systems as transducer oscillators along with a resistive transducer. A very often sought after feature of such single ABB-based canonic SRCOs has been the possibility of employing both grounded capacitors (GC), which are desirable from the viewpoint of IC implementation and easy absorption of parasitic capacitances into these external GCs [27]. However, only the SRCOs [4, 12, 13, 16, 23–26] fulfil this requirement. Furthermore, in view of recent interest in current mode (CM) signal processing [28–30], another sought-after property is the availability of an explicit CM output. This feature is available only in the circuits r IEE, 2005 IEE Proceedings online no. 20040976 doi:10.1049/ip-cds:20040976 Paper first received 24th February and in revised form 19th July 2004 The authors are with the the Analog Signal Processing Research Laboratory, Division of Electronics and Communication Engineering, Netaji Subhas Institute of Technology (formerly, Delhi Institute of Technology), Sector-3, Dwarka, New Delhi 110 075, India E-mail:
[email protected]
38
presented in [12, 14, 23, 26]. Note that, although several authors have emphasised frequency control through a grounded resistor with the argument that this offers ease of electronic control by replacing such a resistor with an FETbased voltage-controlled resistor (VCR) circuit, the recent emergence of a number of CMOS floating VCRs has established that a grounded or floating frequency-controlling resistor can be practically implemented in CMOS (as well as in discrete designs) by almost the same amount of hardware [31–34]. Thus, having the frequency-controlling resistor grounded is no additional advantage or conversely, having the frequency-controlling resistor floating is not a disadvantage. Thus, what is needed is a SRCO possessing the following desirable features: (a) use of a single ABB; (b) employment of two GCs along with a minimum number (only three) of resistors; (c) non-interacting controls of condition of oscillation (CO) and frequency of oscillation (FO); (d) a simple CO (i.e. not more than one condition); and (e) availability of CM and voltage mode (VM) outputs both explicitly. From a critical inspection of the earlier literature [1–26], it is found that none of these previously known single ABB-based SRCOs is capable of providing all the above features simultaneously. Based upon our earlier experience with SRCO-synthesis through state-variable methodology using a variety of active devices [23, 35–40], we found that if we postulate a new ABB namely a ‘differential difference complementary current feedback amplifier’ (DDCCFA) [Note 1] (symbolic notation shown in Fig. 1a) characterised by ivk ¼ 0; k ¼ 1–3, v1 ¼ vy1vy2+vy3, iz1 ¼ +ix, iz2 ¼ ix, vw1 ¼ vz2 and vw2 ¼ vz2 this would be capable of achieving all the intended desirable properties. In this paper, we demonstrate that, a single DDCCFA is sufficient to generate the intended class of SRCO circuits possessing desirable properties (a)–(e) quite easily and that using a state-variable methodology [35–37], a number of
Note 1: The state-variable approach of SRCO-synthesis published earlier by the present authors [35–37] has been extended for the case of single CFOA and single DVCFA-based oscillator circuits by Gunes and Toker in [24]. However, our conceptualisation of the DDCCFA and the derivation of the SRCOs proposed here (excluding the specific CMOS implementation outlined here) was carried out concurrent with the developments reported in [35–37]. IEE Proc.-Circuits Devices Syst., Vol. 152, No. 1, February 2005
z2 y1 w2
y2
DDCCFA
y3
w1
x z1 a + VDD M32
M24
M33 M5
M16
M6 M12
M10 IA
M17
Y3 M1
M7
M2 M8
Y1
CC2 X
CC1 M4
M14 M11
M9
w1
Z1
M13
M19
M25
Z2
M23
M22
M15
M28 M29 RC3
M21
RC2
RC1 Y2
M27
M18
CC3 w2 M26
M30
M20
M31
− VSS b
Fig. 1
Symbolic notation and implementation of the DDCCFA
a Symbolic notation of the DDCCFA (ivk ¼ 0; k ¼ 13; vx ¼ vy1vy2+vy3; iz1 ¼ +ix; iz2 ¼ ix; vw1 ¼ vz1; vw2 ¼ vz2) b CMOS implementation of the DDCCFA
Table 1: Realising different building blocks from a single-DDCCFA Sl
Building blocks to be realised
Procedure to realise the building block Terminals to be grounded
Terminals to be left unused
Terminals to be interconnected
1.
Second generation current conveyor (CCII+)
y2, y3, z2
w1, w2
-
2.
Second generation current conveyor (CCII)
y2, y3, z1
w1, w2
-
3.
First generation current conveyor (CCI )
y2, y3
w1, w2
y1, z1
4.
Dual output current conveyor (DOCC)
y2, y3
w1, w2
-
5.
Differential voltage current conveyor (DVCC+) [41]
y3, z2
w1, w2
-
6.
Differential voltage current conveyor (DVCC) [41]
y3, z1
w1, w2
-
7.
Differential voltage complementary current conveyor (DVCCC) (extension of [41]) [23]
y3
w1, w2
-
8.
Current feedback operational amplifier (CFOA)
y2, y3, z2
w2
-
9.
Differential difference complementary current conveyor (DDCCC) (extension of [41]) [39]
-
w1, w2
-
10.
Differential voltage current feedback amplifier (DVCFA) [24]
y3, z2
w2
-
+
11.
Inverting voltage second generation current conveyor (IVCCII ) [42]
y1, y3, z2
w1, w2
-
12.
Inverting voltage second generation current conveyor (IVCCII) [42]
y1, y3, z1
w1, w2
-
13.
Third generation current conveyor (CCIII+) [43]
y2, y3
w1, w2
y1, z2
+
-
With more than one DDCCFA, other building blocks such as CCI , CCIII [43], CDBA [44], FTFN [45, 46], OTRA [47] and FDCCII [48] can also be realised.
new single DDCCFA-based GC-SRCOs can be systematically derived. 2 Generation of GC SRCOs employing a single DDCCFA From the terminal characterisation of DDCCFA, it is easily visualised that a DDCCFA would be much IEE Proc.-Circuits Devices Syst., Vol. 152, No. 1, February 2005
more generalised and versatile than all previously known building blocks, such as CCII, DOCC, CFOA, differential difference current conveyor (DDCC), differential voltage current conveyor (DVCC), DVCFA etc., since all these can be easily obtained from a DDCCFA as special cases by appropriate grounding, non-utilisation or interconnection of some terminal(s) (see Table 1). 39
A CMOS implementation of the DDCCFA is shown in Fig. 1b, which has been obtained by appropriate augmentation and modification of the DVCFA architecture of [24].
2.1
Synthesis
For the synthesis of the SRCOs, we adopt the state-variable methodology [35–37], which has been tailored to take advantage of the specific terminal characteristics of the DDCCFA to create circuits with the intended properties (a)–(e) outlined in the Introduction. A canonic second-order (i.e. employing only two capacitors) oscillator can, in general, be characterised by the following autonomous state equation: a11 a12 x1 x_ 1 ¼ ð1Þ a21 a22 x2 x_ 2 From the above, the characteristic equation (CE) s2 ða11 þ a22 Þs þ ða11 a22 a12 a21 Þ ¼ 0 gives the CO and FO as ða11 þ a22 Þ ¼ 0 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi o0 ¼ ða11 a22 a12 a21 Þ
ð2Þ ð3aÞ ð3bÞ
The method applied involves the following steps: (i) selection of an appropriate [A] matrix satisfying certain desired requirements (e.g. use of only two capacitors and three resistors and non-interacting controls of CO and FO, (ii) Conversion of the resulting state equations into node equations (NE); and, finally (iii) Constitution of a physical circuit from these NEs such that it becomes possible to obtain the other intended features (e.g. employment of GCs, explicit availability of the outputs etc.).
already met in the selection of the matrix itself. Use of single ABB, employment of both GCs and explicit availability of both CM and VM outputs will be considered while constituting a physical circuit from NEs. The replacement of (6) in (1) leads to the following NEs: x1 x2 x2 ð8aÞ C1 x_ 1 ¼ R1 R2 x1 x2 ð8bÞ R3 For the employment of both GCs (intended property (b)) let us choose the state variables x1 and x2 as voltages across the grounded capacitors C1 and C2 respectively. Keeping in mind that one z-terminal needs to be left open to facilitate explicit current output, the location of one of the grounded capacitor is fixed at either of two z-terminals. Note that, this also helps to represent capacitive parasitics of the z-terminal by an external capacitor. The second grounded capacitor can now be placed at either x-terminal or at any of the yterminals. The obvious choice would be to connect it at any of the y-terminals so that capacitive parasitics of the yterminal could be represented with an external capacitor. Let us choose C1 to be connected at terminal z2 and C2 to be connected at terminal y1. Now the terms on the left-hand side of (8) can easily be seen as currents flowing into grounded capacitors C1 and C2 connected at the z2 and y1 terminals of the DDCCFA, respectively (see circuit 1 in Fig. 2). With y2 and y3 terminals grounded, the voltage x2 becomes available at terminal x (through vx ¼ vy1vy2+vy3). Now, in order to implement the NE C2 x_ 2 ¼
1 C1R1
−
1
1
1 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2p C1 C2 R2 R3
40
FO:
R3
=
R1 k
1 2
f0
C1C2R2R3
(x1− x2) R3 C1x˚1
C1 R3 x2
y1
Z2
y3 x R2 (x1−x2) R1
x1
W2
y2
W1 Z1
x − 2 R2 circuit-1 (k=1)
C2
R3
R3
y1 z2 w2 y2 y3 w1 x z1 R2
R1
C1
ð7bÞ
from which it is seen that CO and FO both would be noninteractively controllable by R1 and R2, respectively. It is clear that intended properties (c), (d) and (b) (partially) are
C2
C2 R3
R1
C1
CO:
1
C2x˚2
The corresponding CO and FO of the SRCO (to be synthesised from the above), would be C1 R1 ¼ C2 R3 ð7aÞ fo ¼
k R2
C2
One of the several possible choices of the parameters aij, i ¼ 1, 2; j ¼ 1, 2, implied by the above equation by matching (3) and (4) is 1 1 1 1 ; a12 ¼ þ ; a11 ¼ C1 R1 C1 R1 R2 ð5Þ 1 1 ; a22 ¼ a21 ¼ C2 R3 C2 R3 The above choice of the parameters aij, gives the following [A] matrix: 2 3 1 1 1 1 6C R C R þ R 7 1 1 1 1 2 7 ½A1 ¼ 6 ð6Þ 4 1 5 1 C2 R3 C2 R3
+
R1 −
C2R3
To have CO controlled by a resistor (say R1) and FO controlled by another resistor (say R2), the required oscillator should have a CE of the form 1 1 1 2 ¼0 ð4Þ s þ sþ C2 R3 C1 R1 C 1 C 2 R2 R3
1
C1
circuit-2 (k=1)
C2
y1 y2 y3 x
R2
R1
z2 w2 z1
w1 C1
circuit-3 (k=1)
Fig. 2 New SRCOs resulting from state-variable synthesis based upon matrix [A]1 of (6) IEE Proc.-Circuits Devices Syst., Vol. 152, No. 1, February 2005
(8a), one should be able to create the currents ((x1x2)/R1) and (x2/R2) flowing into terminal x (as iz2 ¼ ix). This is achieved by connecting a grounded resistor R2 at terminal x and a floating resistor R1 between terminal w2 (which already is at voltage x1) and terminal x. To satisfy the NE (8b) a resistor R3 is connected between terminal w2 and terminal y1 so that the current in this resistor is equal to ((x1x2)/R3), which is the right-hand side of (8b). Various current components of (8) have been marked in circuit 1 to make the synthesis clear. The resulting oscillator circuit, thus synthesised, is shown as circuit 1 in Fig. 2. Note that circuit 1 provides both CM and VM outputs explicitly from the same circuit and that intended properties (a), (e) and the remaining part of (b) are also met. We now show how different ways of connecting passive components at the terminals of the DDCCFA give other GC SRCO realisations meeting all the intended properties (a) to (e) discussed above.
2.1.1 Same NEs, different realisations: A
configuration with grounded R1 is shown as Circuit 2 in Fig. 2.
2.1.2 Same type of [A] matrix, different realisations: It may also be noted in circuit 2 that R2 is connected between terminals x and w1. This resistor can also be connected between terminals x and z1 making the effective value of R2 half of its earlier value. In this operation, the CO and FO of the circuit change but the nature of the circuit does not change, and it still remains an
1
1
C1 R1 1
−
1
1
R3
C1
−
C2 R3
1 R1
−
R2 1 − C2 R3
close look at (8) reveals that by creating voltage x2 at terminal x there may be a possibility of obtaining R2 as a grounded resistor in the circuit. Similarly, creation of voltage (x1x2) might give us a circuit with grounded R1. Consider now the following: (a) Mechanism of grounding R2: In circuit 1 of Fig. 2 it may be observed that by connecting the terminals y2 and y3 to ground, the grounding of capacitors C1 and C2 is achieved by connecting them to terminals z2 and y1, respectively. This makes available the voltage x2 at terminal x and voltage x1 at terminal w2. Now connecting resistor R2 from terminal x to ground and R1 between terminals x and w2 facilitates satisfaction of (8a). Finally, the remaining passive component R3 connected between terminals y1 and w2 satisfies (8b) also. The resulting configuration, thus, ensures grounding of R2. (b) Possibility of grounding R1: To achieve this objective, the required strategy is as follows: connect the grounded capacitor C2 at terminal y2 and C1 at terminals y1 and z1 tied together to generate voltage (x1x2) at terminal x. Now, connect resistors R1 from terminal x to ground and R2 between terminals x and w1 to satisfy (8a). Finally, by connecting the remaining passive component R3 between terminals y2 and w1 (8b) is also satisfied. The resulting
k
CO:
1
+
C1 C2
R3 FO:
C2
f0 =
R3
+1=
R1 1 2
k C1 C2 R2R3
C1
R3
y1 z2 w2 y2 y3 w1 x z1 R1
R2
circuit-4 (k=1)
C2
R3
C2
y1 z2 y2 w2 y3 w 1 x z 1 R1
R2
C1
circuit-5 (k=1)
R3
y1 z2 w2 y2 y3 w1 x z 1 R2
R1
C1
circuit-6 (k=2)
Fig. 3 New SRCOs resulting from state-variable synthesis based upon matrix [A]2 of (9)
Table 2: Effect of the current and voltage tracking errors of the DDCCFA Circuit
Non-ideal expressions for CO and FO CO
1
C1R1 ¼ a5b2C2R3
2
b1 a1 a1 a4 1 þ ¼ C2 R3 C1 R1 R2
3
b1 a1 2ða1 1Þ 1 þ ¼ R2 C2 R3 C1 R1
4
a5 b2 1 1 ¼ þ C1 R1 C1 R3 C2 R3
5
b1 a1 ða1 a4 Þ 1 1 1 þ þ ¼ R2 R3 C1 C2 C1 R1
6
a1 b1 ða1 1Þðb1 þ 1Þ 1 1 1 þ ¼ þ C1 R2 R3 C1 C2 C1 R1
IEE Proc.-Circuits Devices Syst., Vol. 152, No. 1, February 2005
FO (o0) rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi a1 a5 b2 a5 b2 ða1 1Þ þ C1 C2 R1 R3 C1 C2 R2 R3 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi b1 a2 a4 a1 a2 a4 þ a4 a1 þ C1 C2 R3 R1 R2 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi b1 a2 a4 a1 2ða2 a4 þ 1 a1 Þ þ R2 C1 C2 R3 R1 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi b2 a1 a1 a5 þ C1 C2 R3 R2 R1 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi b1 a2 a1 þ a4 a2 a1 þ C1 C2 R3 R2 R1 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi 1 ðb1 þ 1Þða2 a1 þ 1Þ ða2 a1 Þb1 þ C1 C2 R3 R2 R1
41
oscillator with the same properties. The resulting configuration (along with its CO and FO) is shown as circuit 3 in Fig. 2.
synthesis of GC SRCOs with the intended properties using a single DDCCFA:
2.1.3 Different types of generic [A] matrix: It
ð9Þ
has been found that apart from the matrix [A]1 considered above in (6), the following matrix [A]2 is also suitable for the
2
1 1 1 6C R R3 1 1 ½A2 ¼ 6 4 1 C2 R3
3 1 1 1 1 þ C1 R1 R2 R 3 7 7 5 1 C2 R3
Table 3: Effect of the internal poles of the DDCCFA Circuit
Non-ideal expressions of CO and FO (o00 )
Approx. % error
0 o0 o0 100 with Rx{(R1, o0
R2){(Rz1, Rz2) 1
1 1 Rx 1 1 C0 ¼ 1 þ R1 Rz2 AR1 R1 R2 C2 R3 s ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi 1 R2 Rx Rx R2 R2 R2 þ o00 ¼ o0 þ þ þ A Rz2 AR1 AR12 AR1 R1
1 Rx R2 AR2 R2 AR2 Rx þ þ 100 2 2 R1 Rz2 R1 R1 R2
where C10 ¼ C1 þ Cz2 , A ¼ 1 þ RR1x þ RR2x and o0 ¼
2
1 1 1 1 C0 1 1 þ Rx þ ¼ 1 A R2 R1 R2 R2 Rz1 C2 R3 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi R2 Rx Rx 1þ o00 ¼ o0 Rz1 AR2 AR1 where C10 ¼ C1 þ Cz1 , A ¼ 1 þ
3
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 C10 C2 R2 R3
Rx Rx þ and o0 ¼ R1 R2
1 Rx Rx R2 R2 þ þ 100 2 R1 Rz2 R12 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 C10 C2 R2 R3
C10
Rx Rx ¼ C1 þ Cz1 , A ¼ 1 þ þ and o0 ¼ R1 R2
1 R2 Rx Rx 100 2 Rz1 AR2 AR1 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 C10 C2 R2 R3
1 Rx 1 2 2 1 1 C0 1þ þ ¼ 1 A R1 R2 R2 Rz1 R3 C2 R3 R2 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi R2 Rx Rx 1þ o00 ¼ o0 2Rz1 AR2 2AR1 where
42
Rx Rx þ and o0 ¼ R1 R2
1 R2 Rx Rx 100 2 2Rz1 AR2 2AR1
1 Rx 1 1 1 1 1 C0 1þ þ ¼ 1 A R1 R2 R2 Rz1 R3 C2 R3 R2 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi R2 Rx Rx 0 1þ o0 ¼ o0 Rz1 AR2 AR1 where
6
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 C10 C2 R2 R3
1 1 1 Rx 1 1 C0 þ ¼ 1 R1 R3 Rz2 AR1 R1 R2 C2 R3 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi 1 R2 Rx Rx R2 R2 R2 0 þ o0 ¼ o0 þ þ þ A Rz2 AR1 AR12 AR1 R1 where C10 ¼ C1 þ Cz2 , A ¼ 1 þ
5
Rx Rx þ and o0 ¼ R1 R2
1 R2 Rx Rx 100 2 Rz1 AR2 AR1
1 Rx 1 2 2 1 C0 1þ þ ¼ 1 A R1 R2 R2 Rz1 C2 R3 R2 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi R2 Rx Rx 0 1þ o0 ¼ o0 2Rz1 AR2 2AR1 where C10 ¼ C1 þ Cz1 , A ¼ 1 þ
4
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 C10 C2 R2 R3
C10
Rx Rx ¼ C1 þ Cz1 , A ¼ 1 þ þ and o0 ¼ R1 R2
1 R2 Rx Rx 100 2 2Rz1 AR2 2AR1 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 C10 C2 R2 R3
IEE Proc.-Circuits Devices Syst., Vol. 152, No. 1, February 2005
When we convert the above matrix into NEs, oscillator circuits with the intended properties can be constituted from these NEs. When we synthesise the matrix [A]2 of (9) in conjunction with the same NEs, different realisation and same type of [A] matrix, the different realisations as explained in Sections 2.1.1 and 2.1.2 and three more SRCO configurations are obtained, which are shown as circuits 4–6 in Fig. 3.
2.2
mentioned circuits, terminal y3 is grounded and terminals z2 and w2 are not used. In view of the above, the variants of circuits 2, 3, 5 and 6 obtained in the aforementioned manner would be analogous to DVCFA-based SRCOs A1-B3, A1B4 (Table 3a) and A2-B3, A2-B4 (Table 3b) respectively of [24] on the one hand, but in contrast to the quoted circuits of [24], these variants would be superior in terms of the availability of both CM and VM outputs explicitly.
Other variants of derived SRCOs
It may be noted that many variants of the derived SRCOs can be generated due to the particular characterisation of the building block employed. These variants can be generated as follows: (a) Circuits with grounded y2 and y3 terminals: Circuits in which terminals y2 and y3 are grounded (see circuits 1, 4), have three variants in each case, obtained by connecting the junction node of terminals y2 and y3 to any one of the terminals y, z or w, where either voltage x1 or voltage x2 is available. Similarly, if terminals y1 and y3 are swapped and then the above operation is performed with the grounded junction node of terminals y1 and y2, again the same number of additional realisations are available. (b) Different ways to transfer voltage x1 and/or voltage x2: Note that in circuits 2, 3, 5 and 6 the voltage x1 has been brought to terminal y1 by shorting y1 to terminal z1. New variants of these circuits (one in each case) would be available by shorting y1 to terminal w1 (keeping other connections and elements intact) such that none of the node equations are disturbed. Also note that in the above-
2.3 Effect of current/voltage tracking errors of DDCCFA Since the practical realisations of DDCCFA will have some current/voltage tracking errors (although usually quite small), it is worthwhile to examine their effects on the performance of the new SRCOs. Active and passive sensitivities of the oscillation frequency are other figures of merit of interest. To evaluate these, we denote the voltage tracking error as a and the current tracking error as b. Now, the characteristic equations of the DDCCFA can be rewritten as iyk ¼ 0; k ¼ 1–3, vx ¼ a1vy1a2vy2+a3vy3, iz1 ¼ +b1i, iz2 ¼ b2iv, vw1 ¼ a4vz1 and vw2 ¼ a5vz2. By a re-analysis, the CO and FO of circuits 1–6 are determined and are detached in Table 2. It may be observed from Table 2 that even after consideration of the voltage/current tracking errors of the DDCCFA, the oscillators of circuit 1 and circuit 4 remain SRCOs with independent control of FO by R2. Therefore, these two are the best structures from this viewpoint.
40
300 200 voltage, mV
current, µA
20
0
100 0
−100
−20
−200 −40
0
100
200
300
400
500
−300
time, µs
0
100
a
80
100
140
120 frequency, kHz
frequency, kHz
500
160
140
100 80 60
120 100 80 60
0
20
40
60
80
R2, kΩ
100
40
0
20
c
Fig. 4
400
b
160
40
200 300 time, µs
40 60 R2, kΩ d
Transient responses and oscillation frequencies for SRCOs of circuits 1 and 4
a Transient response for the CM output of the SRCO of circuit 4 b Transient response for the VM output of the SRCO of circuit 1 c Variation of f0 with R2 for the SRCO of circuit 1 d Variation of f0 with R2 for the SRCO of circuit 4 IEE Proc.-Circuits Devices Syst., Vol. 152, No. 1, February 2005
43
Table 4: Level 7 SPICE parameters for 0.35 lm CMOS process Model parameters MODEL CMOSN NMOS (LEVEL ¼ 7 MOBMOD ¼ 1.000e+00 CAPMOD ¼ 2.000e+00 NLEV ¼ 0 +NOIMOD ¼ 1.000e+00 K1 ¼ 6.044e-01 +K2 ¼ 2.945e-03 K3 ¼ 1.72e+00 K3B ¼ 6.325e-01 NCH ¼ 2.310e+17 +VTH0 ¼ 4.655e-01 VOFF ¼ 5.72e-02 DVT0 ¼ 2.227e+01 DVT1 ¼ 1.051e+00 DVT2 ¼ 3.393e-03 +KETA ¼ 6.21e-04 PSCBE1 ¼ 2.756e+08 PSCBE2 ¼ 9.645e-06 DVT0W ¼ 0.000e+00 DVT1W ¼ 0.000e+00 +DVT2W ¼ 0.000e+00 +UA ¼ 1.000e-12 UB ¼ 1.723e-18 UC ¼ 5.756e-11 U0 ¼ 4.035e+02 DSUB ¼ 5.000e-01 +ETA0 ¼ 3.085e-02 ETAB ¼ 3.95e-02 NFACTOR ¼ 1.119e-01 EM ¼ 4.100e+07 PCLM ¼ 6.831e-01 +PDIBLC1 ¼ 1.076e-01 PDIBLC2 ¼ 1.453e-03 DROUT ¼ 5.000e-01 A0 ¼ 2.208e+00 VSAT ¼ 1.178e+05 AGS ¼ 2.490e-01 B0 ¼ 1.76e-08 B1 ¼ 0.000e+00 +DELTA ¼ 1.000e-02 PDIBLCB ¼ 2.583e-01 W0 ¼ 1.184e-07 DLC ¼ 4.000e-09 LW ¼ 0.000e+00 LWL ¼ 0.000e+00 LLN ¼ 1.000e+00 LWN ¼ 1.000e+00
A1 ¼ 0.000e+00
DWB ¼ 0.000e+00
+A2 ¼ 1.000e+00
PVAG ¼ 0.000e+00
+DWG ¼ 0.000e+00
LL ¼ 0.000e+00
+WL ¼ 0.000e+00 WW ¼ 0.000e+00 WWL ¼ 0.000e+00 WLN ¼ 1.000e+00 WWN ¼ 1.000e+00 AT ¼ 3.300e+04 +UTE ¼ 1.80e+00 KT1 ¼ 3.30e-01 KT2 ¼ 2.200e-02 KT1L ¼ 0.000e+00 UA1 ¼ 0.000e+00 UB1 ¼ 0.000e+00 +UC1 ¼ 0.000e+00 PRT ¼ 0.000e+00 CGDO ¼ 1.120e-10 CGSO ¼ 1.120e-10 CGBO ¼ 1.100e-10 CGDL ¼ 1.350e-10 +CGSL ¼ 1.350e-10 CKAPPA ¼ 6.000e-01 CF ¼ 0.000e+00 ELM ¼ 5.000e+00 XPART ¼ 1.000e+00 +CLC ¼ 1.000e-15 CLE ¼ 6.000e-01 RDSW ¼ 6.043e+02 CDSC ¼ 0.000e+00 CDSCB ¼ 0.000e+00 +CDSCD ¼ 8.448e-05 PRWB ¼ 0.000e+00 PRWG ¼ 0.000e+00 CIT ¼ 1.000e-03 TOX ¼ 7.700e-09 +NGATE ¼ 0.000e+00 NLX ¼ 1.918e-07 ALPHA0 ¼ 0.000e+00 BETA0 ¼ 3.000e+01 AF ¼ 1.400e+00 +KF ¼ 2.810e-27 EF ¼ 1.000e+00 NOIA ¼ 1.000e+20 NOIB ¼ 5.000e+04 NOIC ¼ 1.40e-12 LINT ¼ 1.67e-08 +WINT ¼ 2.676e-08 XJ ¼ 3.000e-07 RSH ¼ 8.200e+01 JS ¼ 2.000e-05 CJ ¼ 9.300e-04 CJSW ¼ 2.800e-10 +CBD ¼ 0.000e+00 CBS ¼ 0.000e+00 IS ¼ 0.000e+00 MJ ¼ 3.100e-01 N ¼ 1.000e+00 MJSW ¼ 1.900e-01 +PB ¼ 6.900e-01 TT ¼ 0.000e+00 PBSW ¼ 6.900e-01) MODEL CMOSP PMOS (LEVEL ¼ 7 MOBMOD ¼ 1.000e+00 CAPMOD ¼ 2.000e+00 NLEV ¼ 0 +NOIMOD ¼ 1.000e+00 K1 ¼ 5.675e-01 K2 ¼ 4.39e-02 K3 ¼ 4.540e+00 K3B ¼ 8.52e-01 NCH ¼ 1.032e+17 +VTH0 ¼ 6.17e-01 VOFF ¼ 1.13e-01 DVT0 ¼ 1.482e+00 DVT1 ¼ 3.884e-01 DVT2 ¼ 1.15e-02 +KETA ¼ 2.56e-02 PSCBE1 ¼ 1.000e+09 PSCBE2 ¼ 1.000e-08 DVT0W ¼ 0.000e+00 DVT1W ¼ 0.000e+00 +DVT2W ¼ 0.000e+00 UA ¼ 2.120e-10 UB ¼ 8.290e-19 UC ¼ 5.28e-11 U0 ¼ 1.296e+02 DSUB ¼ 5.000e-01 +ETA0 ¼ 2.293e-01 ETAB ¼ 3.92e-03 NFACTOR ¼ 8.237e-01 EM ¼ 4.100e+07 PCLM ¼ 2.979e+00 +PDIBLC1 ¼ 3.310e-02 PDIBLC2 ¼ 1.000e-09 DROUT ¼ 5.000e-01 VSAT ¼ 2.000e+05 AGS ¼ 3.482e-01 B0 ¼ 2.719e-07 B1 ¼ 0.000e+00
A0 ¼ 1.423e+00
+DELTA ¼ 1.000e-02 PDIBLCB ¼ 1.78e-02 W0 ¼ 4.894e-08 DLC ¼ 4.000e-09 LW ¼ 0.000e+00 LWL ¼ 0.000e+00 LLN ¼ 1.000e+00 LWN ¼ 1.000e+00
A1 ¼ 0.000e+00+A2 ¼ 1.000e+00
DWB ¼ 0.000e+00
PVAG ¼ 0.000e+00
+DWG ¼ 0.000e+00
LL ¼ 0.000e+00
+WL ¼ 0.000e+00 WW ¼ 0.000e+00 WWL ¼ 0.000e+00 WLN ¼ 1.000e+00 WWN ¼ 1.000e+00 AT ¼ 3.300e+04 +UTE ¼ 1.35e+00 KT1 ¼ 5.70e01 KT2 ¼ 2.200e-02 KT1L ¼ 0.000e+00 UA1 ¼ 0.000e+00 UB1 ¼ 0.000e+00 +UC1 ¼ 0.000e+00 PRT ¼ 0.000e+00 CGDO ¼ 7.420e-11 CGSO ¼ 7.420e-11 CGBO ¼ 1.100e-10 CGDL ¼ 1.290e-10 +CGSL ¼ 1.290e-10 CKAPPA ¼ 6.000e-01 CF ¼ 0.000e+00 ELM ¼ 5.000e+00 XPART ¼ 1.000e+00 +CLC ¼ 1.000e-15 CLE ¼ 6.000e-01 RDSW ¼ 1.853e+03 CDSC ¼ 6.994e-04 CDSCB ¼ 2.943e-04 +CDSCD ¼ 1.970e-04 PRWB ¼ 0.000e+00 PRWG ¼ 0.000e+00 CIT ¼ 1.173e-04 TOX ¼ 7.700e-09 +NGATE ¼ 0.000e+00 NLX ¼ 1.770e-07 ALPHA0 ¼ 0.000e+00 BETA0 ¼ 3.000e+01 AF ¼ 1.290e+00 +KF ¼ 1.090e-27 EF ¼ 1.000e+00 NOIA ¼ 1.000e+20 NOIB ¼ 5.000e+04 NOIC ¼ 1.40e-12 LINT ¼ 8.14e-08 +WINT ¼ 3.845e-08 XJ ¼ 3.000e-07 RSH ¼ 1.560e+02 JS ¼ 2.000e-05 CJ ¼ 1.420e-03 CJSW ¼ 3.800e-10 +CBD ¼ 0.000e+00 CBS ¼ 0.000e+00 IS ¼ 0.000e+00 MJ ¼ 5.500e-01 N ¼ 1.000e+00 MJSW ¼ 3.900e-01 +PB ¼ 1.020e+00 TT ¼ 0.000e+00 PBSW ¼ 1.020e+00)
Table 5: Aspect ratios of the MOSFETs used in CMOS implementation of the DDCCFA MOSFET
W/L, mm
M1, M2, M3, M4, M14, M15, M26, M27
24/0.35
M7, M8, M9, M11, M13, M19, M20, M24, M30, M31, M32, M33
10/1.5
M5, M6, M10, M12, M16, M17, M18, M21, M22, M23, M27, M28, M29
15/1.5
44
On the other hand, from the non-ideal expressions of o0 for the various SRCOs as given in Table 2, it is found that all passive and active sensitivities (with respect to a1; i ¼ 1–5 and bj; j ¼ 1, 2) of o0 for all the circuits are given by 0 jS o0 j 1 under the condition R2{R1 and thus, all the new circuits enjoy low sensitivities.
2.4
Effect of internal poles of DDCCFA
Analogous to a normal CFOA pole [49], the finite input resistance Rx of the x terminal and the parasitic output resistance Rz and output capacitance Cz of the z terminals will constitute the internal poles of the new building block IEE Proc.-Circuits Devices Syst., Vol. 152, No. 1, February 2005
DDCCFA. Therefore, the effect of the internal poles can be estimated by a re-analysis of the new SRCO circuits taking into account these parasitic impedances. The resulting
expressions for the non-ideal CO and the non-ideal FO are shown in Table 3. It is, thus, observed that the CO as well as the FO both deviate from their nominal values. Since the complex nature of the expressions does not appear to give a clear insight, to estimate the error in the realised frequency quantitatively, we have worked out expressions for the percentage error caused by these parasitics impedances. The resulting approximate expressions for the percentage error are shown in Table 2. The difference between the PSPICEobserved values of f0 and their theoretical values (as in Figs. 4c and 4d) is attributed to these errors. It is clear from the last column of Table 2 that by judicious selection of " the parameters Rx, Rz1, Rz2 of values of R1 and R2 vis-a-vis the chosen DDCCFA architecture, the errors in the realised frequency can be kept small.
Table 6: Aspect ratios of the MOSFETs used in CMOS VCR MOSFET
W/L, mm
M1, M2
0.5/5
M3, M4
1.3/5
M5, M6
7/1
M7
1/5
M8, M9
8/1
20
VDD M9
M8
Vc
M2
M1
I in, µA
10
M4
M3
−10
Vin Vb
Vb
M7
−20 −500
M6
M5
0
−250
0 Vin, mV
VSS a 100
120
90 frequency, kHz
R2, kΩ
100 80 60 40
2
500
b
140
20
250
80 70 60 50
4
3 V c, V
40
2
3 Vc, V
c
d linear range of VCR V0 (circuit 4)
1
voltage, V (p-p)
4
0.8 VVCR (circuit 4) V0 (circuit 1)
0.6 VVCR (circuit 1)
0.4 0.2 0
2
3
4
Vc, V e
Fig. 5
Results for CMOS VCR of Wilson and Chan [50]
a CMOS VCR of Wilson and Chan b v–i characteristic of the VCR c Variation of resistance with Vc d Variation of f0 with Vc for the VCO mode of circuit 1 e Variation of V0 and VVCR with the controlling voltage VC IEE Proc.-Circuits Devices Syst., Vol. 152, No. 1, February 2005
45
Table 7: Comparison of single-ABB-based canonic SRCOs Explicit outputs** Canonic SRCOs and the active building block employed therein
Yr
CA
N
SRC
S
E
CM
VM
CM & VM
Senani’s oscillator using op-amp (Fig. 1 of [1] with resistor R6 deleted)
1979
O
5
both
O
O
Prem Pyara, Dutta Roy and Jamuar’s oscillators using op-amp [2]
1983
O
5
both
O
O
Bhattacharyya and Darkani’s oscillators using op-amp (Fig. 10 of [3])
1984
O
5
both
O
O
Darkani and Bhattacharyya’s oscillators using op-amp (Fig. 5 of [4])
1985
O
6
both
O
O
Senani and Bhaskar’s oscillators using op-amp (Fig. 1 of [5])
1991
O
7
both
O
Soliman’s oscillator using CCII+ [6]
1978
O
4
FO
Senani’s oscillator using CCII+ (Fig. 1 of [7])
1979
O
5
both
+
Abuelma’atti and Humood’s oscillator using CCII (Fig. 6 of [8])
1988
O
3
both
O
Celma, Martinez and Carlosena.s oscillator using CCII+ (Fig. 1 of [9])
1992
O
3
both
O
Celma, Martinez and Carlosena’s oscillator using CCII+ (Fig. 4, oscillator 11 of [11])
1994
O
3
both
O
Abuelma’atti and Khan’s oscillator using OTA (Fig. 2b of [25])
1996
2
FO by R1, CO by gm
O
Abuelma’atti and Khan’s oscillator using OTA (Fig. 3 of [25])
1996
O
2
FO by R1, CO by gm
Liu, Shih and Wu’s oscillators using CFOA (Figs. 3, 6 of [18])
1994
O
3
both
O
O
Senani and Singh’s oscillators using CFOA (Figs. 5, 6 and 7 of [19])
1996
O
3/4
both
O
O
Abuelma’atti and Al-Shahrani’s oscillator using CFOA (Fig. 1 Oscillator 1 of [20])
1997
O
3
both
O
O
Toker, Cicekoglu and Kuntman’s oscillators using CFOA (Oscillators m, n, o in Fig. 6 of [21])
2002
O
3/4
both
O
O
Senani’s oscillator using FTFN (Fig. 4a in [12])
1994
5
both
O
O
Senani’s oscillator using FTFN (Fig. 4c in [12])
1994
5
both
O
O
Liu and Liao’s oscillator using FTFN (Fig. 2 of [13])
1996
5
both
O
O
Cam, Toker, Cicekoglu and Kuntman’s oscillator using FTFN (Fig. 2, Oscillator 1 of [14])
2000
5
both
O
O
Lee and Wang’s oscillator using FTFN+ (Fig. 1 of [15])
2001
3
both
O
Bhaskar’s oscillator using FTFN+ (Fig. 1 of [16])
2002
4
both
O
O
Ozcan, Toker, Acar and Kuntman’s oscillators using CDBA (Oscillators 1-4, 6 in Table 1 of [22])
2000
3
FO
O
O
Cam’s oscillator using OTRA (Fig. 1 of [17])
2002
3
FO
O
O
Gupta and Senani’s oscillator using DVCCC (Fig. 1 of [23])
2000
3
both
O
O
O
Gunes and Toker’s oscillators using DVCFA (Oscillators A1-B3, A1-B4, A2-B3, A2-B4 in Table 3a of [24])
2002
3
both
O
O
O
Chang, Al-Hashimi, Chen, Tu and Wan oscillators using FDCCII (Figs. 1 and 2 of [26])
2002
3
both
O
O
O
New SRCOs using DDCCFA
new
3
both
O
O
O
O
O
‘Canonic’ refers to the circuits using only two capacitors * * explicit CM with ideally N output impedance and explicit VM with ideally zero output impedance Yr: year of publication; CA: commercial availability of the ABB; N: number of resistors used; SRC: SRC of CO/FO; S: simple CO (no more than one condition); E: employment of two GCs
3
PSPICE simulation results
For PSPICE simulation of the circuits, the DDCCFA was realised by the CMOS implementation shown in Fig. 1b. 46
Compensating resistors and capacitors were taken as RC1 ¼ 30 kO, RC2 ¼ RC3 ¼ 20 kO and CC1 ¼ CC2 ¼ CC3 ¼ 0.45 pF. The level 7 MOSFET model parameters for the 0.35 mm CMOS process were employed, which are shown in IEE Proc.-Circuits Devices Syst., Vol. 152, No. 1, February 2005
Table 4. The aspect ratios of the various MOSFETs are given in Table 5. The DC supply voltages were 71.65 V, the DC bias current was chosen as 50 mA. All the SRCO circuits were designed with passive component values as C1 ¼ C2 ¼ 100 pF, R2 ¼ 10 kO, R3 ¼ 10 kO and R1 was adjusted to fulfil the CO. In the simulations, all the SRCOs behaved as predicted by theory. The sample transient responses, for the CM output of the SRCO of circuit 4 and the VM output of the SRCO of circuit 1, are shown in Fig. 4a and 4b, respectively. The plots of variation of f0 with R2 for the CM SRCOs of circuit 1 and VM SRCO of circuit 4 are shown in Figs. 4c and 4d, respectively. To check the high frequency operation, circuit 1 was designed with passive component values C1 ¼ C2 ¼ 39.8 pF, R2 ¼ R3 ¼ 4 kO thereby leading to foD1 MHz (simulation showing 0.96 MHz) and then R1 was adjusted to fulfil the CO. This confirms that the proposed circuits could work up to around 1 MHz with the chosen architecture of the DDCCFA, which exhibits a flat frequency response (with error in gains r2%) of the voltage gain and current gain up to around 2.3 MHz and 4 MHz, respectively. It is obvious that the operational frequency of the new circuits could be extended further with the availability of any new DDCCFA architecture exhibiting wider bandwidth than the one employed here. To realise voltage-controlled oscillator (VCO) forms of the new SRCO circuits, one needs a CMOS voltagecontrolled resistor (VCR) for which a number of options are available, such as the circuits in [31–33, 48], from which we have chosen the CMOS VCR of Wilson and Chan [48], reproduced here in Fig. 5a, to be used to replace R2. The v–i characteristics of the chosen VCR have also been generated from PSPICE simulations and are shown in Fig. 5b. The aspect ratios of the various MOSFETs in this circuit have been modified to suit the 0.35-micron process and are given in Table 6. The supply voltages were 75 V and bias voltage Vb was chosen as 3.8 V. Level 7 MOSFET model parameters taken in this case are shown in Table 3. Figure 5c shows the variation of the realised resistance with control voltage VC, which demonstrates that by varying VC from 2 to 4 V, the equivalent resistance realised by this VCR can be varied over the range 136–28.6 kO. Putting this VCR in place of R2, circuits 1 and 4 were converted into VCOs. The result of the VCO derived from the SRCO of circuit 1 is shown in Fig. 5d, which shows that f0 of circuit can be varied from 48 to 97 kHz by varying VC from 2 to 4 V. A question may arise as to how the nonlinearity of the CMOS VCR affects the performance of the proposed circuits. To this end, we have determined the signal voltage across the CMOS VCR for the oscillators of circuit 1 and circuit 4, which are plotted along with the peak-to-peak output voltage versus the controlling voltage in Fig. 5e. This also shows the peak-to-peak linear input voltage range of the chosen VCR as a dotted line. From inspection of this Figure it is clear that over the entire range of VC the voltage across the VCR continues to remain lower than its linear range (VVCRr1 V (p-p)). With an appropriate (additional) amplitude control circuitry incorporated, the output voltage of the proposed oscillators can always be kept at such a value that the resulting voltage across the CMOS VCR (grounded or floating) remains within its linear range of operation. Hence, the nonlinearity of the CMOS resistor does not affect the performance of the proposed circuits. It may be pointed out that in conjunction with MOS capacitors and CMOS VCRs (grounded or floating) [31–34, 50], all the proposed circuits, when realised with the DDCCFA of Fig. 1b, are suitable for IC implementation in 0.35-micron CMOS technology. IEE Proc.-Circuits Devices Syst., Vol. 152, No. 1, February 2005
The simulation results, thus, confirm the workability of the proposed SRCOs as well as the VCOs realised from them. 4
Concluding remarks
A state-variable methodology has been used to generate a class of canonic GC SRCOs employing a new active building block named the ‘differential difference complementary current feedback amplifier’ (DDCCFA). The salient features of the SRCO structures derived here can now be summarised as follows: (i) Employment of a single ABB. (ii) Employment of both GCs and a minimum number (only three) of resistors. (iii) Non-interacting control of CO as well as that of FO. (iv) A simple CO and unconstrained tuning law for FO. (v) Simultaneous availability of explicit VM output as well as explicit CM output. When a comparison is made with all previously reported canonic SRCOs employing only a single ABB (which may be an op-amp, a CCII, an OTA, a CFOA, an FTFN, a CDBA, an OTRA, a DVCCC, a DVCFA, or an FDCCII) it is found (Table 7) that none of these previously known circuits provide all the features simultaneously which are available in the new SRCOs presented here. Exploration of the applications of the building block DDCCFA, in other areas of analogue signal processing, such as realisation of voltage/current mode universal biquad filters appears worth investigating. 5
References
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