High Level Stream Processing with FPGA Hendarmawan, Mpho Gift Doctor Gololo, Qian Zhao, Masahiro Iida Graduate School of Science and Technology, Kumamoto University 2-39-1 Kurokami, Chuo-ku, Kumamoto 860-8555, Japan Email: {hendarmawan, doctor, cho}@arch.cs.kumamoto-u.ac.jp
[email protected]
Abstract—In recent years, Stream processing is becoming an emerging concept and applications for processing flow of streaming data to detect relevant information and providing necessary data for further steps. From previous research, Field-Programmable Gate Arrays (FPGA) are introduced in order to process real time continuous data stream. However, developers need months or years to develop FPGA which make development cost of FPGA very high. On the other hands, FPGA itself is offering high performance processing with high throughput, low latency, offering parallelism for scalability and low energy resources. In this paper, we try to simplify hardware accelerator development and how it can be implemented at low costs with high performance. Finally, we combine this approach with the heterogeneous Computing Oriented Development Environment (hCODE) Framework for easy Hardware and Software Integration. Experimental results show that the implemented hardware acceleration is faster than software implementation of regular expression for different sizes of data stream at low cost.
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Fig. 1: Shell-and-IP hardware framework.
Keywords: Regular Expression, FPGA, Stream Processing
(https://github.com/hCODE-FPGA/hCODE) for evaluation including shells and intellectual property (IP) for the case study. Fig 1 ilustrate hCODE shell and IP hardware framework.
I. I NTRODUCTION
II. R ELATED WORKS
Field-programmable gate arrays (FPGAs) have demonstrated great speed performance and power efficiency advantages over conventional computers in various domains, such as image processing, communication, and data analysis. In reality, design and implementation of hardware on FPGA normally take longer period of time. It is because it requires a developer much circuit design skills to use tools to work on FPGA. This disadvantageous attribute makes development cost on FPGA high. In our previous work, heterogeneous Computing Design (hCODE) Method [1] proposed a study to create a bridge between SW and HW design. In this work, based on the proposed hCODE, we show an efficient way to accelerate regular expression matching on FPGAs for streaming processing, which is an important component for feature extraction, intrusion detection system, etc. Yang and Prasanna [2] showed that high performance can be achieved using Regular Expression Matching (REM) on FPGA. However, development cost are too high for most current system to adopt. By benefited from hCODE, this paper intends to balance performance of hardware accelerators with hardware development cost as compared to prior works. This is achieved by using hCODE and HLS to develop a high performance stream accelerator on FPGA at low cost. The prototype of hCODE is currently open-sourced on Github
Regular expression matching is an important mechanism used by popular network intrusion detection system (NIDS) such as Bro [3] and Snort [4] to perform deep packet inspection against potential threats. However, the number of patterns to be scanned is increasing at a high rate as well as the bandwidth network traffic. As mentioned in [2], a design, implementation and evaluation of a high-performance architecture for regular expression matching (REM) is performed on field programmable gate array (FPGA) to counteract the problem of increasing number of patterns to be scanned and network bottleneck. The main objective of using FPGA to solve this problem is to accelerate the system to achieve high performance. The hCODE platform contains design method and tools in order to simplify the creation, sharing, and software integration of FPGA hardware accelerators and defines participant roles to reduce the design costs. III. R EGEX C ASE S TUDY In this section, we evaluate the proposed hCODE with a regular expression acceleration case study. Regular expressions (Regex) are patterns used to match that character combinations in strings or input text. Pattern matching algorithm and rules then be implemented in regular expression engine.
A. System design !"#"$ !"%& '()*+,+"*5671+8123419
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First, Xillybus can provide enough throughput for the implemented merge-tree. Second, the 32-bit FIFO is convenient for Int32 numbers operation. And last, we need the mem port for the ease of controlling. C. Evaluation results We used Enron email dataset [8] which contains emails generated by employees of the Enron Corporation. The size of file is 1.42 GB and after we collect all email it detect 6,934,002 email addresses.
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