High Level Synthesis for Partial Scan
M. L. Flottes, R. Pires, B. Rouzeyre, L. Volpe Laboratoire d'Informatique, de Robotique et de Micro-électronique de Montpellier, U.M. CNRS 9928 161 rue Ada, 34392 Montpellier Cedex 5, France
[email protected], TEL : (33) 4 67 41 85 27, Fax : (33) 4 67 41 85 00
Abstract In this paper, we present a High Level Synthesis method for partial scan designs. High level testability information are used to guide the synthesis process towards designs with a minimal number of scan registers. The maximal fault coverage is achievable for these designs. This method mainly lean on ad-hoc modifications of the register allocation process. Keywords : Partial scan selection, synthesis for testability.
1.
Introduction
"High Level Synthesis For Testability (HLSFT)" groups all the techniques used for synthesizing designs from behavioral to RT level but, conversely to standard High Level Synthesis (HLS), bearing testability the same importance as other parameters (area, latency ...). Some published works in HLSFT deal with partial scan designs. The proposed approaches essentially focus on loops since it is well known that the loops in a design increase the complexity of the ATPG process. In [LEE93], the number of scan registers being fixed, scheduling and allocation/binding solutions are explored to improve controllability and observability by generating design solutions with the minimal number of loops, the minimal sequential depth between input and output registers and the maximal number of registers directly connected to primary input/output ports. Another approach proposed in [DEY94] and [POT95] consists in using high level transformations and an adhoc assignment process in order to synthesize RTL designs such that all loops can be opened using a
minimal number of scan registers. In [FER96] the authors present allocation/binding methods for minimizing the number of scan registers required to open all loops. Testability criteria used in these methods tend to ease ATPG process but they do not explicitly target partial scan designs with high fault coverage (the same that could be achieved in full scan). Fig.1 illustrates this point: in this design, either register R2 or R4 can be selected to open the loop shown in bold line. For illustration purpose, we used a functional unit (shaded box) through which it is not possible to justify some test pattern (i.e. presenting a transparency problem). If register R4 is selected to be part of the scan chain, 97.67% of fault coverage is obtained for this design, whereas the full scan fault coverage (99.76%) is obtained when register R2 is selected (results from [SUN], test efficiency is equal to 100% in all experiments). In fact, in the first case some faults in R2 and FU1 remain non-testable due to the nontransparency of FU2. PI
R2
R1
FU1
R3
R4
FU2
PO
Fig.1: Scan selection for opening loops In this paper, we present a new method for generating partial scan designs that contain as few scan
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registers as possible and have the same fault coverage than their corresponding full scan implementation. Considered testability problems are not only loops but also the problems related to lack of transparency and to reconvergent fanouts. It must be stressed that conversely to related works, the easiness for a sequential ATPG to find out test patterns is not considered. In this sense, testability refers here as the existence of a test sequence and not to the time needed to find it (which it is not a recurrent cost). Next section motivates the advantage of using some knowledge on testability during the HLS for minimizing the number of scan registers rather than to take care about testability at lower level. In section 3, we present an overview of the proposed methodology. Algorithms are detailed in section 4. The results demonstrating the effectiveness of our method are presented in section 5. Section 6 concludes the paper.
2.
Motivation
In this section we show that a two-steps approach consisting in 1/ improving the testability of a design during HLS and 2/ scanning some registers at RT level may be inadequate to obtain the best partial scan structure. As a matter of fact, better results can be obtained by using high level scan information to guide the synthesis process. Let's first recall that a register inherits of all possibilities of control and observation from the variables that it implements. So the basic "trick" for improving testability during HLS is to assign registers in such a way that as many registers as possible contain a variable detected as being testable. Let's consider the scheduled Data Flow Graph (DFG) given in Fig.2. The three variables (A, C and D) present controllability problems because of the left-shift operations (denoted by "
