Low Cost Partial Scan Design : A High Level Synthesis ... - CiteSeerX

Low Cost Partial Scan Design : A High Level Synthesis Approach

M. L. Flottes, R. Pires, B. Rouzeyre, L. Volpe Laboratoire d'Informatique, de Robotique et de Micro-électronique de Montpellier, U.M. CNRS 5506 161 rue Ada, 34392 Montpellier Cedex 5, France Tel: (33) 4 67 41 85 27, Fax: (33) 4 67 41 85 00

Abstract: In this paper, we present a High Level Synthesis method for partial scan designs. High level testability information are used to guide the synthesis process towards designs with a minimal number of scan registers. The maximal fault coverage is achievable for these designs. This method mainly leans on ad-hoc modifications of the register allocation process.

1.

Introduction

"High Level Synthesis For Testability (HLSFT)" groups all the techniques used for synthesizing designs from behavioral to RT level but, conversely to standard High Level Synthesis (HLS), bearing testability the same importance as other parameters (area, latency ...). Some published works in HLSFT deal with partial scan designs. The proposed approaches essentially focus on loops since it is well known that loops increase the complexity of the ATPG process. In [1] scheduling and allocation/binding solutions are explored to improve controllability and observability. The number of scan registers is user-defined. Pre-selected scan variables are assigned to registers in order to generate design solutions with a minimal number of loops, a minimal sequential depth between input and output registers and a maximal number of registers connected to primary input/output ports. Another approach proposed in [2] and [3] consists in using high level transformations and an ad-hoc assignment process in order to synthesize RTL designs such that all loops can be opened using a minimal number of scan registers. In [4] the authors present allocation/binding methods for minimizing the number of scan registers required to open all loops.

Instead of using scan registers to enhance the testability of a datapath, Hsu et al. [5] propose several control modifications and the addition of test pins. The role of these pins is to ease the control of data-dependant loops during ATPG. Testability criteria used in these methods tend to ease ATPG process but they do not explicitly target partial scan designs with high fault coverage (the same that could be achieved in full scan). Fig.1 illustrates this point: in this design, either register R2 or register R4 can be selected to open the loop shown in bold line. For illustration purpose, we used a functional unit (shaded box) through which it is not possible to justify some test pattern (i.e. a functional unit presenting a transparency problem). If R4 is selected to be part of the scan chain, 97.67% of fault coverage is obtained for this design, whereas the full scan fault coverage (99.76%) is obtained only when R2 is selected (results from [6], test efficiency is equal to 100% in all experiments). In fact, in the first case some faults in R2 and FU1 remain non-testable due to the non-transparency of FU2. In this paper, we present a new method for generating partial scan designs that 1/ contain as few scan registers as possible and 2/ have the same fault coverage than their corresponding full scan implementation. Proposed approach focus on loops, but also on testability problems related to lack of transparency and to reconvergent fanouts. It must be stressed that conversely to related works, the easiness for a sequential ATPG to find out test patterns is not considered. In this sense, testability refers here as the existence of a test sequence and not to the time needed to find it (which it is not a recurrent cost).

equivalent in terms of testability and area, both of them may result from the first step of the two-steps approach (HLSFT + RT level scan selection).

PI

R2

R1

FU1

R3

R4

FU2

PO

Fig.1: Scan selection for opening loops Next section motivates the choice of a partial scan strategy where scan selection is performed at the very begining of the design process. Section 3 presents an overview of the proposed methodology. Algorithms are detailed in section 4. The results demonstrating the effectiveness of our method are presented in section 5. Section 6 concludes the paper.

2.

Motivation

In this section we show that a two-steps approach consisting in 1/ improving the testability of a design during HLS and 2/ scanning some registers at RT level may be inadequate to obtain the best partial scan structure.

Nevertheless, solution S1 requires reg1 and reg2 to be scanned, while conversely solution S2 requires only one register to be scanned in order to achieve the maximal fault coverage. In fact, transforming reg1 into a scan register in solution S2 makes reg3 controllable through the multiplier. The "good" solution -S2 in the previous example- can be obtained for certain if HLS is guided by the idea that the design will be scanned. It can be derived at behavioral level that, however synthesis is performed, the register that will implement variable A will be scanned. The reasons are that 1/ A can not share a register with another variable and 2/ no modification on its testability can be achieved by changing testability of other variables. Consequently, variable A can be considered as a new test point (I/O) during synthesis. This new feature impacts on the testability of other variables: D becomes controllable. On the basis of this new information, register allocation will be driven to solve the only remaining testability problem, namely the controllability on variable C, by assigning testable variable B with C into the same register (solution S2). This example shows that some additional information can be used to guide the HLSFT towards a low cost design solution and high fault coverage.

PI1

Let's first recall that a register inherits of all possibilities of control and observation from the variables that it implements. So the basic "trick" for improving testability during HLS is to assign registers in such a way that as many registers as possible contain a variable detected as being testable. Let's consider the scheduled Data Flow Graph (DFG) given in Fig.2. The three variables A, C and D present controllability problems because of the left-shift operations denoted by "