... of Carbon Nanotubes in CMOS Integrated Circuits. Philip C. H. Chan, Chai Yang, Min Zhang, Yunyi Fu*. Department ofElectronics and Computer Engineering.
The Application of Carbon Nanotubes in CMOS Integrated Circuits Philip C. H. Chan, Chai Yang, Min Zhang, Yunyi Fu* Department of Electronics and Computer Engineering The Hong Kong University of Science and Technology * Peking University
Abstract With the complementary metal-oxide-semiconductor (CMOS) technology approaching its scaling limit, many novel devices and material are being considered to enable further scaling of CMOS. Carbon nanotubes show unique properties and are currently considered as a potential alternative material for nano-CMOS building blocks. Performance of carbon nanotube field effect transistors (CNFET) can be competitive with Si MOSFET in the sub-20nm regime. With its superior material properties, CNT can also function as quantum wire and a critical material for the integrated circuit interconnection. In this talk, we shall present some of the works we have done on applying carbon nanotubes to the CMOS Integrated Circuits in our research group at the Hong Kong University of Science and Technology. Carbon Nanotube Field Effect Transistor (CNFET) The real-world applications of CNFET require the integration of the device into the CMOS platform. We demonstrated a new local silicon-gate CNFET by combining the in situ CNT growth technology and the SOl technology. Most of the processes except the CNT growth process are the standard CMOS front-end process. This enables the integration of CNTs to the CMOS platform for the first time. The proposed CNFET structure realized individual device operation, batch fabrication, low parasitics and better compatibility to the CMOS process at the same time. The transconductance is larger than 1530 JlS/Jlm, the ratio of Ion/lofT is larger than 105, the subthreshold slope is up to 101 mY/dec, the current per unit width is 2940 JlA/Jlm, and the current density is 2.2xl0 8 A/cm2. Scaling Land Tox, as well as optimizing the metal electrodes can further improve the working voltage and transconductance. The ambipolar conductance and the scaling effect of the CNFETs were analyzed based on the Schottky barrier (SB) modulated conductance. The SB plays an important role in the CNFET conductance. The configuration proposes a feasible approach to integrate the CNFET to CMOS platform, which makes CNT a step closer to application. We have demonstrated a functional carbon nanotube fieldeffect transistor (CNFET), but for it to be useful in integrated circuits, we need to selectively grow carbon nanotubes at a predetermined location in the integrated circuit. Hence, a more controllable and selective CNT growth technique must be developed to make CNFET a more practical device. We propose a new CNFET with controlled and selectively grown CNT using a novel carbon nanotube growth technique. In the existing approach, the carbon nanotubes grew semi randomly between the source and drain catalyst islands. Often, many
carbon nanotubes grew between the catalyst islands. This process is extremely difficult to control in a manufacturing environment. Hence, a more controllable and selective carbon nanotube growth technique must be developed to make CNFET into a practical device. We propose a CNFET with controlled and selectively grown CNT to form the conducting channels. We shall present some of our recent attempts to fabricate Carbon Nanotube Field-effect Transistors (CNFET) with Parallel Aligned Carbon Nanotube Channels. CNT Interconnect and High Frequency Performance of CNTs CNTs can also be used as the transmission lines and passive components in ICs. The radio-frequency characteristic of CNTs is not well understood. We have fabricated an array of single-walled CNTs in situ in a global-gate CNFET configuration. RF transmission characteristics of the gatedependent CNTs were measured up to 12 GHz using the full two-port S-parameter methodology for the first time. Multiple SWNTs on the CNT-array-device produced large enough signal to enable the RF measurements. The effect of gate bias change on the RF characteristics of CNTs is small. Subtracting the effect of the parasitics, the CNT signal transmission maintains constant and shows no degeneration even at frequency up to 12 GHz. An empirical RLC element model was developed to model the RF response of the CNT array. The equivalent circuit element parameters of CNT model were extracted. There are large capacitances connect between the CNTs and the metal electrodes, which provided a low impedance path for signal transmission at radio frequencies. The RF characteristics of the SWNTs have also been investigated. The DC/AC two-terminal resistances were measured and analyzed. We reported the experimental data for the two-port S parameters of the SWNTs up to 20 GHz. Using the local silicon-gate CNFET common-source configuration, we measured S21 and observed the signal transmission from the gate to the drain up to 100 MHz. The DC drain bias has significant effect on the HF signal transmission, while the DC gate bias has little effect on the HF signal transmission. CNT as Via and Contact Plug in ICs The feature size of integrated circuit will continue to scale down according to the international technology roadmap of semiconductor (ITRS). New technologies have been developed to shrink the feature size and increase the transistor density. However, the continued scaling in semiconductor industry leads to a discrepant performance between the active transistor and some passive components. For the copper
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interconnects in current IC technology, the scaling leads to the increase of the resistivity of the copper interconnect, resulting in increasing resistance-capacitance signal delay. The small feature size also increases the current density through the interconnection, which further aggravates the copper electromigration (EM). Roadmap projects for microprocessor chips the maximum heat dissipation chip power dissipation will exceed 300 W, the average chip heat flux will exceed 150 W/cm 2 and the local hotspots with heat fluxes approaches 1 kW/cm2 within the next few years. The chip performance, reliability and yield issues caused by these problems were proven to be more challenging than expected. If these problems cannot be addressed, the benefit from the transistor scaling will be offset.
with atomic layer deposition (ALD) to fill the high aspectratio contact holes. In addition, the increasing resistivity due to the size effect will result in unacceptably high contact resistance for future technology generations. To keep pace with the requirement of the ITRS roadmap, material with both high EM resistance and good conductivity are imperative to enable the continuing scaling of the interconnects. New material and process technology must be developed. Electroplated super-filling Rh and Cu with high conductivity were investigated as an alternative for W contact plug. However, the electroplating method will lead to a more complex process, including the deposition of the integrated barrier and seed layer, and increase the production cost.
The mean free path of the carriers in the CNT is much longer than that of metal. Transparent electrical contacts made to a single CNT have been reported to be ballistic. The carbon-carbon bonding between the neighboring atoms in the CNT is one of the strongest bonding reported. Migration of carbon atoms will not occur even under very high current density. The EM tolerance of CNT is much better than that of other traditional interconnect material, such as, copper and aluminum. The most serious and persistent reliability problem in interconnect metallization is contact and via voiding caused by EM, due to the current crowding effect. The contact and via are usually the smallest and most abundant features in an integrated circuit. The reliability of the integrated circuit depends heavily on the robustness of the contact and via technology.
CNT with high aspect ratio features excellent electrical properties and high EM resistance. This could be a possible long-term solution for the contact plug material. The carbon nanofiber grown directly on the silicon has been shown to Schottky barrier behavior. The Ohmic transport behavior is essential for the CNT contact plug application. The addition of a metal silicide layer eliminates the SB and turns the contact to Ohmic. The work function of the metal silicide is close to the Fermi level of the silicon. The metal silicide also showed better wetting behavior with the catalyst layer for the CNT growth. In this work, we formed a Ti silicide on the doped silicon firstly, and then grew the CNTs on the silicide. We shall present the detail of our work in the conference.
Researchers have developed methods to control the vertically aligned CNTs using CVD method. There are a number of works reported using the CNT bundles for via filling applications. A bundle of densely packed single-walled CNT would be an ideal candidate for replacing copper metallization. However, there are still significant engineering problems to overcome, such as, the contact resistance between nanotube and metal, the purity of the metallic nanotube in the densely packed nanotube bundles. Therefore, the use of SWCNT only as interconnect is still questionable at this time. It has been demonstrated both theoretically and experimentally that all shells within multi-walled CNT can conduct if proper connections are made to all of them.
We have presented some of the work we have done on the application of carbon nanotubes to the CMOS Integrated Circuits. The detailed results and discussions can be found in our recent publication listed in the Reference section. These works would have not been possible without the numerous contributions of scientists and engineers working in this field their works were referenced in our publications.
In our work, we filled the contact and via holes with MWCNTs using bottom-up PECVD growth method. Furthermore, we also proposed a copper/CNT composite via configuration with both high electrical conductivity and excellent EM resistance. Contact plug, which is also called local wiring or metal zero in interconnect metallization system is directly in contact with silicon transistors. In the current interconnect technology; CVD tungsten is used as the contact plug for both microprocessor and dynamic random access memory chip. As the feature size of the semiconductor industry scale down to the nanometer range, the aspect ratio of the contact holes is projected to be greater than 20:1 by 2010 according to the ITRS roadmap. It is difficult for CVD tungsten in conjunct
Summary
Acknowledgments The authors would like to acknowledge the support of RGC CERG grants: 611305, 611307 and Croucher Foundation grant: CAS-CF05/06.EGOI. References 1. Min Zhang, Xiao Huo, and Philip C. H. Chan, "Radiofrequency Characterization for the Single-walled Carbon Nanotubes", Applied Physics Letters Vol. 88, No. 16, pp.163109-1-3 17 April, 2006. 2. Min Zhang, Philip C. H. Chan, Yang Chai, Qi Liang and Z. K. Tang, "Local Silicon-Gate Carbon Nanotube Field Effect Transistors on Silicon-on-Insulator", Applied Physics Letters, vo1.89, no.2, pp. 23116-1-3,10 July 2006. 3. Min Zhang, Xiao Huo, Philip C. H. Chan, Qi Liang, and Z. K. Tang, "Radio-frequency Characterization of Carbon Nanotubes in a FET Configuration", IEEE Electron Device Letters, vo1.27, no.8, pp. 668-70, August. 2006
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4. Yang Chat, Jtngteng Uong, Kat Zhang, PhjJjp C. H. Chan,
and Matthew M. F. Yuen, "Flexible Transfer of Aligned Carbon Nanotube Films for Integration at Lower Temperature", Nanotechnology, 18, pp. 35-39, 7 August 2007. 5. Kai Zhang, Chai Yang, M. M. F. Yuen, D. G. W. Xiao and Philip C. H. Chan, "Carbon nanotube thermal interface material for high-brightness light-emitting-diode cooling", pp. 1-8, (19) 2008.
Conference, ECTC, May 29-June 1, 2007 at Reno, Nevada, USA. 14. Yang Chai, Philip C. H. Chan, Yun-Yi Fu, Zhuo-Qun Zhuang and Cheng-Yi Liu, "Copper/Carbon Nanotube Composite Interconnects for Enhanced Electromigration Resistance" to appear in 58!!! ECTC, June 2008.
6. Min Zhang, Philip C. H. Chan, Yang Chai, Qi Liang, and Z. K. Tang, "Novel Local Silicon-Gate Carbon Nanotube Transistors for Integration to Silicon-on-Insulator Technology", to appear in IEEE Transactions on Nanotechnology. 7. Min Zhang, Xiao. Huo, Qi. Liang, Zikang Tang, Philip C. H. Chan, "High Frequency Characterization for the SingleWalled Carbon Nanotubes Using S-parameter", 4th IEEE International Conference on Nanotechnology, Aug. 17-19, 2004, Munich, Germany. 8. Xiao Huo, Min Zhang, Philip C. H. Chan, Qi Liang, and Zikang Tang, "High Frequency S Parameters Characterization of Bottom-gate Carbon Nanotube Field-Effect Transistors" International Electron Device Meeting, IEDM, December 1215, San Francisco, USA 2004. 9. Kai Zhang, Guo-Wei Xiao, Cell K. Y. Wong, Hong-Wei Gu, Matthew M. F. Yuen, Philip C. H. Chan, Bing Xu, "Study on Thermal Interface Material with Carbon Nanotubes and Carbon Black in High-Brightness LED Packaging with Flip-Chip Technology", pp. 60-65, 55 th Electronic Components & Technology Conference, Lake Buena Vista, Florida, USA, May 31- June 3, 2005. 10. Min Zhang, P. C. H. Chan, Chai Yang, Zikang Tang, "Applying SOl technology on carbon nanotube transistors", pp. 147-8, IEEE International SOl Conference, October, 2006. 11. Yang Chai, Min Zhang, Jingfeng Gong and Philip C. H. Chan, "Reliability Evaluation of Carbon Nanotube Interconnect in a Silicon CMOS Environment", International Symposium on Electronic Materials and Packaging, EMAPS December 2006, Hong Kong. 12. Yang Chai, Kai Zhang, Min Zhang, Philip C. H. Chan and Matthrew M. F. Yuen, "Carbon Nanotube/Copper Composites for Via Filing and Thermal Management", pp.1224-1229, 57th Electronic Components and Technology Conference, ECTC, May 29-June 1, 2007, Reno, Nevada, USA. 13. Yang Chai, Jingfeng Gong, Kai. Zhang, Philip C. H. Chan and Matthrew M. F. Yuen, "Lower Temperature Transfer of Aligned Carbon Nanotube Films Using Liftoff Technique", pp. 429-434, 57th Electronic Components and Technology
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