International Conference on Inventive Communication and Computational Technologies (ICICCT 2017)
I2C Protocol and its Clock Stretching Verification using System Verilog and UVM Lakshmi Manasa Kappaganthu, Durga Prakash M
Avinash Yadlapati
Electronics and Communication Engineering K L University Guntur, India
[email protected],
[email protected]
SEMICON team Cyient Ltd Hyderabad, India
[email protected]
Abstract— Present day’s technology has reached a goal where an entire system can be implemented on a single chip which is nothing but called system on chip (SOC). It involves microcontrollers and various peripheral devices with each peripheral device having its own intellectual property (IP) named as IP cores. Serial Communication is established between these IP cores using various protocols like RS232, RS422 and UART etc. These protocols perform point to point communication which requires huge wiring connections, multiplexing of all the bus connections to deliver the information to the IP Cores. To overcome this I2C protocol is developed by Philips, which is a two line communication. Here only two pins i.e., SCL, SDA establish connection between various devices considering one as master and other as slave, as in [1]. These two pins communicate using particular commands like start, address, read/write, acknowledgement and stop commands. Both 7-bit and 10-bit addressing formats can be used, 10-bit addressing supports more addressing lines i.e., 1024 compared to 127 addressing lines in 7bit mode. Clock stretching case is explained here clearly i.e., when a slave needs to have control on the clock generated by the master. The advantage in this protocol is it has low wiring; data transfer rate can be improved using Ultra-Fast mode (UFm), as in [2]. In this paper they perform verification for the design of an I2C protocol between a master and a slave using system Verilog and UVM in the tool SimVision. Keywords—I2C (Inter Integrated Circuit); IP (Intellectual Property); SCL (Serial Clock); SDA (Serial Data); UFm (UltraFast mode); Clock Stretching;
I.
INTRODUCTION
I2C i.e., Inter Integrated Circuit is a popular serial data transfer protocol which is acquiring huge popularity with its implementation in more than 1000 I.C’s. As the size of an I.C is shrinking day by day, the demand to decrease wiring is increasing which prioritizes serial data transfer methodology [2]. There are various serial data transfer protocols like RS232, SPI, RS422, UART etc. These have the disadvantages like more wiring, speed limit, inefficiency to connect more devices between the pins, interference problems, as in [3]. To overcome these issues I2C protocol is developed by Phillips semiconductors (now named as NXP semiconductors) in 1982. It is best employed for serial communication as it has only two pins for data transfer of any rate, more than two devices can be
connected between these pins without collisions during data transfer, bus arbitration technique can be used when multiple masters are present and various speed modes are present depending on the requirement. Clock stretching case is clearly explained here, where it illustrates how slave hold the clock low when the data cannot be accepted or transmitted by it to the master. Once the slave becomes free it releases the clock line i.e., SCL is made high. II.
OVERVIEW OF THE IMPLIMENTATION
As an overview on the work to implementation System Verilog Verification environment, SimVision Tool is discussed below. A. Verification Environment in System Verilog x Slave is considered as the DUT with Master coding various test cases i.e., Test Bench [3]. DUT is coded using behavioral Verilog HDL, Test bench environment is created in S.V using UVM methodology, is tested for various test cases. S.V is based on OOPs concepts (i.e., polymorphism, inheritance etc., where the test bench runs around the code and is reusable) which make it advantageous to Verilog. x Test Bench environment involves various sub parts like Transaction, Generator, Driver, Environment, Test and Top. Each part of test bench related to individual blocks is separately executed and all are finally linked in the top module. Virtual interface is used for communication between DUT and Test Bench [3]. It is represented as below. B. SimVision Tool Results are simulated in SimVision tool, it is an integrated graphical debugging environment within Cadence which supports signal and transaction level flows across the design and the test bench. It is used for simulating for various languages like VHDL, Verilog, and System Verilog etc., [4]. It is advantageous i.e., DUT and Test Bench both can be analyzed anytime during the verification time.
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International Conference on Inventive Communication and Computational Technologies (ICICCT 2017)
III.
PROTOCOL DESCRIPTION
2
I C protocol has a basic format by which it transfers or receives data. Master and Slave basic functionality along with the extension modes are discussed in this section
Fig. 1.
Writing data into the slave 7-bit address.
Fig. 2.
Writing data into the slave 10-bit address.
A. Master It acts as a transmitter and a receiver [5]. It addresses the slave in both 7-bit and 10-bit addressing formats as follows. x
It generates the clock pulse.
x
It acts as a transmitter and a receiver.
x
It acknowledges when it acts as a receiver.
x
When a master also acts as a slave, its slave address is same as master address.
x
It performs clock synchronization when multiple masters send different clocks.
B. Slave It is addressed by the master and acts as a both transmitter and a receiver as mentioned below. x It acts as a transmitter and a receiver. x It acknowledges whenever it is addressed and when it acts as a receiver. x It can perform clock stretching to hold the SCL line low when it is taking more time to store data or start a new transaction. IV.
EXTENSION MODES
UFm mode can only make a write transaction, acknowledgment signal is not required in the UFm mode but to reserve the pattern of the protocol the ack bit is present, it is always set high. Clock stretching is a special case which is done only in simple mode, cannot be done in UFm as the slave cannot control the clock in UFm [5], [6]. It is done by the slave when its speed of operation does not match with the clock operation. In that situation slave stretches the clock before the acknowledgment signal, asking the master to wait until it gets free to accept next data. Once the slave releases the clock master can start making transactions with the slave [7]. A. (1) start bit is set’1’, (2-8) 7-bit address is transmitted, 8th bit indicating a write action, 9th bit is high ack, (10-18) 8-bit data is written into the slave address, 19th bit is an high ack signal after which repeated start action is done or stop can be done as shown in Fig. 1. B. (1) start bit is set, (2-7) first 7-bit slave address sent, 8th bit indicating write action, 9th bit is a low ack, (10-18) second byte address sent, 19th bit i.e., again slave sends an ack after which data can be written, (20-27) 8-bit data written to slave, 28th bit indicating ack from slave, 29th bit indicates stop or repeated start as shown in Fig. 2.
Fig. 3. “Wait State” indicating Clock Stretching in simple 7-bit write mode.
C. Clock stretching is done by the slave when its speed of operation does not match with the clock operation [7], [8]. In that situation slave stretches the clock before the acknowledgment signal, asking the master to wait until it gets free to accept next data. Once the slave releases the clock master can start making transactions with the slave. It is explained as below, where the wait state indicates clock stretching by the slave as shown in Fig. 3. V.
RESULTS
A. 7-bit and 10-bit write in Ultra-Fast mode. Fig.4 indicates write operation when considering 7-bit address; here acknowledgment signal is always set high, as there is no read action to be done. (1) Start bit, (2-8) 7-bit address sent to slave, (9) ‘0’ bit indicating write action, (A) high ack signal, (B-12) 8-bit data written into the slave address, (13) high ack signal sent by the slave to reserve the pattern. Fig.5 indicates write operation when considering 10-bit address, last two LSB bits of the first address become the MSB bits of the 10-bit slave address and second byte address are the remaining 8-bits of 10-bit address. (1) Start bit, (2-8) 7-bit address sent to slave, (9) ‘0’ bit indicating write action, (A) ack signal, (B-12) second byte slave address, (13) ack signal by the slave, (14-1B) 8-bit data written to the slave, (1C) ack signal sent by slave to make repeated start or stop action. B. Clock Stretching. Fig.6 indicates clock stretching in normal 7-bit write action, where the slave stretches the clock before the ack signal after the data is written into the slave. Once the clock is stretched, it indicates slave is busy in completing transaction and is asking the master to wait i.e., slave is slower than the master clock. After the 13th bit position clock is stretched and released at 14th bit. After the clock is released by the slave at 14th bit, start bit is set by the master
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International Conference on Inventive Communication and Computational Technologies (ICICCT 2017)
Fig.4. Master writing data into the 7-bit slave address.
Fig.5. Master writing data into the 10-bit slave address.
Fig.6. Clock stretching by the slave when master clock operates at high speed. [7]
ACKNOWLEDGMENT Heartfelt thanks to the SEMICON team [CYIENT ltd, Hyderabad] for giving us attention and their valuable time at peak times REFERENCES [1] [2]
[3]
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J. W. Bruce, “Personal Digital Assistant (PDA) Based I2C Bus Analysis,” IEEE Transactions on Consumer Electronics, Vol. 49, No. 4, Nov. 2003. [8] Peter Corcoran, “Two Wires and 30 Years,” U.S. Patent 4 689 750, Aug. 25, 1987. [9] S. Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”. Upper Saddle River, New Jersey: Prentice Hall, Jan. 1996. [10] Chris Spear , “System Verilog for verification: A Guide to Learning the test bench for Language Features : Springer, second edition”. [11] Vincet Himpe, “Mastering the I2C bus”. [12] Saikat Bandopadhyay: Simulation. In: Sanjay ChuriwalaNagel. (eds.) Designing with Xilinx FPGAs. LNCS, pp. 127--140. Springer, Switzerland, 2017.
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