IGBT Dynamic Loss Reduction through Device Level Soft ... - MDPI

energies Article

IGBT Dynamic Loss Reduction through Device Level Soft Switching Lan Ma 1,2 , Hongbing Xu 1, *, Alex Q. Huang 3 , Jianxiao Zou 1 and Kai Li 1 1

2 3

*

School of Automation Engineering, University of Electronic Science and Technology of China, West High-Tech District, Chengdu 611731, China; [email protected] (L.M.); [email protected] (J.Z.); [email protected] (K.L.) Department of Electrical and Computer Engineering, NC State University, Raleigh, NC 27695, USA Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX 78712, USA; [email protected] Correspondence: [email protected]; Tel.: +86-138-800-17160

Received: 30 March 2018; Accepted: 7 May 2018; Published: 8 May 2018







Abstract: Due to its low conduction loss, hence high current ratings, as well as low cost, Silicon Insulated Gate Bipolar Transistor (Si IGBT) is widely used in high power applications. However, its switching frequency is generally low because of relatively large switching losses. Silicon carbide Metal-Oxide-Semiconductor Field-Effect Transistor (SiC MOSFET) is much more superior due to their fast switching speed, which is determined by the internal parasitic capacitance instead of the stored charges, like the IGBT. By the combination of SiC MOSFET and Si IGBT, this paper presents a novel series hybrid switching method to achieve IGBT’s dynamic switching loss reduction by switching under Zero Voltage Hard Current (ZVHC) turn-on and Zero Current Hard Voltage (ZCHV) turn-off conditions. Both simulation and experimental results of IGBT are carried out, which shows that the soft switching of IGBT has been achieved both in turn-on and turn-off period. Thus 90% turn-on loss and 57% turn-off loss are reduced. Two different IGBTs’ test results are also provided to study the modulation parameter’s effect on the turn-off switching loss. Furthermore, with the consideration of voltage and current transient states, a new soft switching classification is proposed. At last, another improved modulation and Highly Efficient and Reliable Inverter Concept (HERIC) inverter are given to validate the effectiveness of the device level hybrid soft switching method application. Keywords: dynamic switching loss; Si IGBT; SiC MOSFET; hybrid switching method; zero voltage hard current (ZVHC); zero current hard voltage (ZCHV); zero current zero voltage (ZCZV)

1. Introduction The Si IGBT is one of the most important power semiconductor devices and is found in widespread high power applications, like medium voltage motor drives, EV traction inverters, and grid-connected inverters for PV and wind. To obtain high efficiency, high power density, and low junction temperatures, the switching losses must be kept low by fast switching of the IGBT [1]. However, under hard switching condition, the IGBT voltage and current have a substantial overlap during the turn-on and turn-off events that introduce significant switching losses, especially the switching-off loss. It exhibits a current tail during turn-off period that causes high turn-off switching loss, since IGBT is a minority-carrier device [2]. To reduce the switching loss, the design and optimization of IGBT is a non-stopping effort by device manufacturers, resulting in improved performance from one generation to another. One of the most effective ways to reduce the switching loss is manipulating the voltage and current waveforms of IGBT during the turn-on or off transition periods to eliminate or to reduce the overlap.

Energies 2018, 11, 1182; doi:10.3390/en11051182

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There are two critical factors affects the voltage and current waveforms’ states of IGBT, which are the designs of gate driver circuit and the external circuit. A simple gate-boosting circuit is presented in [3], which achieved the reduction of current rise time and the turn-on loss. Moreover, based on the gate driver circuit, different open and closed loop control strategies have also been proposed. A multistage gate drive control concept has been proposed in [4,5] to realize the optimal turn-on and turn-off performance. According to the different feedback signals or constraints, adaptive feedback control [6] and dynamic gate current control [7] can also effectively reduce the IGBT switching loss with variable switching speed. By introducing the active voltage control technique and shaping the IGBT switching transient into a sophisticated ‘S’-shape, both switching loss reduction and acceptable Electromagnetic Interference (EMI) can be achieved in [8]. The main drawbacks that are associated with these methods are control complexity for accurate signals detection and limited switching loss reduction. Adding the auxiliary circuit is also a popular way to reduce the IGBT switching loss by achieving soft switching. A passive circuit, which is composed of an extra capacitor, inductor, and diode is one of the attractive ways to cut down the switching loss. By introducing an external capacitor that is paralleled with the IGBT, the voltage rise is softer during the turn-off transition, which results in the reduction of power loss [9,10]. In these papers, zero voltage switching ZVS is realized for the IGBT. However, the energy that is stored in the snubber capacitor is discharged through the IGBT, which causes a current spike during the turn-on transition. Adding an external inductor series with IGBT reduces the switching loss by achieving zero current switching [11,12]. However, it can result in an extra magnetic loss. There is also an active auxiliary circuit that includes the active switches to achieve IGBT soft switching. Varies approaches are proposed to reduce the switching loss of the main switches in the different application [13,14]. The cost of these active auxiliary circuits is higher when compared to the passive circuit. Also, to improve the efficiency of the application, the active switches should also operate under soft switching condition, which increases the control complexity [15]. With the help of the external circuit and various control strategies, the switching loss of IGBT can be efficiently reduced. However, there still a high cost for those solutions and the applicability is also limited. When compared to the IGBT, the MOSFET has excellent switching characteristic. By combining the advantages of the MOSFET and the IGBT, a hybrid switch is proposed in [16], which are composed of an IGBT and a MOSFET. Based on the parallel connection of these two devices, the hybrid switch achieved better performance for the higher frequency. It also can improve the efficiency when introducing to different applications [17,18]. In recent years, emerging wide bandgap (WBG) devices, such as silicon carbide (SiC) MOSFET, provide an attractive solution to improve power converter efficiency and power density by reducing semiconductor losses, operating at higher switching frequencies, and higher temperatures in many different applications. However, the price of SiC MOSFET is usually three to five times of the same rating Si IGBT device [19]. Moreover, SiC unipolar devices strongly suffer from oscillatory behavior during turn-off switching due to the lack of excess carriers. To overcome these drawbacks, hybrid switches, which connect Si IGBT and SiC MOSFET in parallel were studied in [20–22]. The characteristics of hybrid switches have been analyzed in detail. Furthermore, with a comprehensive consideration of device losses, reliable operation, and overload capability, a current-dependent switching strategy was developed in [23] that is based on the Si/SiC hybrid devices. Most of these papers are proposed based on the paralleled hybrid switches, which focus on the current sharing behavior, while the switching loss reduction of IGBT is still limited. In this paper, a new soft switching classification is carried out firstly with the consideration of voltage and current transient states. Then, a new hybrid switching method is proposed to achieve IGBT operating under ZVHC turn-on and ZCHV turn-off soft switching conditions. In this method, the IGBT is series with a SiC MOSFET. A dead time is given by the SiC MOSFET to provide soft switching conditions for Si IGBT turn-on and turn-off. Thus, the dynamic switching losses of IGBT can be efficiently reduced through the device level soft switching method. With smaller switching loss, IGBT can operate at a higher frequency, which helps to reduce the size of passive elements. Two different IGBTs’ test results are also provided to study the modulation parameter’s effect on the

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turn-off switching loss. Furthermore, another improved modulation is given in this paper to help IGBT to achieve ZCZV turn-off soft switching. At last, an improved HERIC inverter is also presented to show that it is easy to apply this hybrid switching method to the existing converters. This paper is organized as follows: to get the better understanding of soft switching, a detail IGBT soft switching classification is given in Section 2; the configuration and modulation of the hybrid switches are shown in Section 3, double pulse test simulation and experimental results for the hybrid switches are also analyzed. In Section 4, a different modulation strategy is also developed to achieve better performance. Furthermore, an application example—improved HERIC inverter is studied. The simulation results verify the effectiveness of hybrid switching method application. Finally, Section 5 concludes this paper. 2. IGBT Soft Switching Classification In hard switching, the IGBT voltage and current have a substantial overlap during the turn-on and turn-off events, resulting in large switching losses, as shown in Figure 1(a1,b1). To reduce the switching losses, the voltage and current waveforms can be manipulated in order to eliminate or minimize the overlap, which is the basic idea of soft switching. In the past, there are two typical soft switching types, which include zero-voltage switching and zero-current switching. Zero-voltage switching (ZVS) is defined as allowing the switching device to be turned on and off when the applied voltage across the device is effectively zero. Likewise, zero-current switching (ZCS) allows for the switching device to be turned off while the current conducted by the switching device is zero [2]. Also, a switching device, which is turned on under a zero-current switching condition, is also given in [9]. On the other hand, in recently, most of the papers specifically focus on the realization of ZVS condition for MOSFET and ZCS condition for IGBT based on the characteristics of the different switching device. ZVS is categorically used to describe the soft turn-on while ZCS is used to describe the soft turn-off. Both of these classifications are not very accurate for the IGBT device since the IGBT device dynamic loss depends on exactly how the voltage and current are applied, even if there is no ‘intended’ overlap. Detailed evaluation reveals that the classification must consider both the voltage transition and the current transient for both the turn-on and turn-off. A turn-on and turn-off switching classification are given in this paper, as shown in Figure 1. It is not only decided by if the voltage or current is zero before the switching device is turned on or off, but also take the states of the rising or falling edges of voltage and current into consideration. The turn-on and turn-off waveforms under hard switching condition are shown in Figure 1(a1,b1). The overlaps of voltage and current can be found in these switching transitions that cause the switching loss. To reduce the switching loss, various gate driver circuits, additional passive snubber, and active auxiliary circuits are proposed. For example, in Figure 1(a2), the turn-on is named ZVHC turn-on since the voltage is reduced to zero before a hard imposed current rise (current rises with a high dI/dt). Similarly, Figure 1(b2) is named ZCHV turn-off since the current is reduced to zero before a high dV/dt applied to the IGBT. In the ZVHC turn-on, the high dI/dt generates a voltage bump, so there is some additional overlapping; hence, the turn-on loss is not zero. The voltage bump is caused by the bipolar IGBT physics since conductivity modulation needs time and current to establish. Similarly, in the ZCHV turn-off, the high dV/dt generates a current bump because stored carriers need time to recombine. In the case of ZCHV turn-off, the delay time between the ZC edge and the HV edge is critical in determining the current bump. In the case of the ZVHC case, the delay between the two edges (ZV and HC) does not affect the voltage bump since the delay does not help the establishment of the conductivity modulation. The voltage bump is strongly related to the applied dI/dt. With the help of the snubber circuit, the current rise during turn-on transition period and the voltage rise during turn-off transition period can slow down. As shown in Figure 1(a3), the current rise edge is softer than hard switching’s. It is defined as Hard Voltage Zero Current (HVZC) turn-on, which also indicates effective loss reduction. Similarly, Figure 1(b3) is defined as Hard Current Zero Voltage (HCZV) turn-off because of the soft voltage rise edge [9]. In Figure 1(a4), Zero Voltage Zero Current

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Energies 2018, 11, FOR PEER REVIEW 16 (ZVZC) turn-on isx obtained since the voltage decreases to zero before the switching device4isof turned on, while the current also rises slowly [24]. In Figure 1(b4), ZCZV turn-off is achieved since the current Energies 2018, 11, x FOR PEER REVIEW 4 ofthe 16 is achieved since the current decreases to zero before the switching device is turned off, while decreases to also zerorises before the switching device is turned off, while the voltage also rises slowly. voltage slowly.

is achieved since the current decreases to zero before the switching device is turned off, while the voltage also rises slowly.

(a)

(b)

Figure 1. Turn-on and turn-off switching classification (a) Turn-on; and, (b) Turn-off. (a)turn-off switching classification (a) Turn-on; (b) and, (b) Turn-off. Figure 1. Turn-on and Figureturn-on 1. Turn-on andZCHV turn-offturn-off switching classification Turn-on; and,in (b)soft Turn-off. The ZVHC and are frequently(a)encountered switching IGBT

converters. Recently, suchand soft ZCHV switchingturn-off schemes are are also proposed encountered and are elegantly in a The ZVHC turn-on frequently in realized soft switching The ZVHC turn-on and InZCHV turn-off are frequently encountered in soft switching IGBT Si-SiC hybrid power switch. this paper, a hybrid switching method is proposed to reduce the IGBT converters. Recently, such soft switching schemes are also proposed and are elegantly realized converters. Recently,loss such soft switching schemes are alsoSiC proposed and are elegantly realized in a dynamic switching of IGBT. As shown Figure 2a, the MOSFET is in series with the Si IGBT. in a Si-SiC hybrid power switch. In this paper, a hybrid switching method is proposed to reduce the Si-SiC hybrid power switch. Inthe this paper, a hybrid switching method or is proposed to reduce the The SiC MOSFET always keeps off state Figure during the IGBT switching-on asthe shown dynamic switching loss of of IGBT. As shown 2a,the theSiC SiC MOSFET isoff in transiation, series with Si IGBT. dynamic switching loss IGBT. As shown Figure 2a, MOSFET is in series with the Si IGBT. in Figure 2b. As a result, the IGBT can be turned on under ZVHC condition and turned off under The SiC MOSFET always keeps the theIGBT IGBTswitching-on switching-on transiation, as shown The SiCcondition. MOSFET always keeps theoff offstate stateduring during the or or off off transiation, as shown ZCHV in Figure 2b. As a result, the IGBT can be turned on under ZVHC condition and turned off under in Figure 2b. As a result, the IGBT can be turned on under ZVHC condition and turned off under ZCHV condition. ZCHV condition.

(a)

(b)

Figure 2. (a) Proposed Hybrid Switches Configuration; and, (b) Modulation.

(a)

(b)

Figure 2. (a) Proposed Hybrid Switches Configuration; and, (b) Modulation.

Figure 2. (a) Proposed Hybrid Switches Configuration; and, (b) Modulation.

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3. Hybrid Soft Switching Method Based on Device Level 3. Hybrid Soft Switching Method Based on Device Level 3.1. Proposed Hybrid Switches Configuration and Modulation 3.1. Proposed Hybrid Switches Configuration and Modulation Figure 2 shows the series hybrid switches configuration and modulation. A SiC MOSFET is seriesFigure with 2anshows IGBT,the as series displayed inswitches Figure 2a. Providing SiC a proper turn-off signal is hybrid configuration and MOSFET modulation. A SiC MOSFET is series the central concept to helpinIGBT achieve soft switching. In thea turn-on period (t1~t3), first, the with an IGBT, as displayed Figure 2a. Providing SiC MOSFET proper turn-off signal isatthe central voltage the IGBT to switching. zero when In thethe SiC MOSFET is turned t1. the After a while, concept on to help IGBTdecreases achieve soft turn-on period (t1~t3),off atat first, voltage on the IGBT decreases is turned on at t2,when whichthe indicates that there will be current in theory. to zero SiC MOSFET is turned offno at voltage t1. Afterand a while, thecrossing IGBT is turned on After the transient turn-on period is finished, the SiC MOSFET is turned onthe again at t3. at t2, which indicates that there willof beIGBT no voltage and current crossing in theory. After transient Then, the turn-on period of the hybrid switches is completed. the turn-off period first, turn-on period of IGBT is finished, the SiC MOSFET is turned onInagain at t3. Then, the (t4~t6), turn-onat period the current through IGBT decreases to zero the SiC MOSFET turned at t4. through After a while, of the hybrid switches is completed. Inwhen the turn-off period (t4~t6), atisfirst, theoff current IGBT the IGBT is off at which indicates that off there will be no voltage current crossing in decreases to turned when zero thet5, SiC MOSFET is turned at t4. After a while, theand IGBT is turned off at t5, theory. After the transient turn-off period of IGBT is finished, the SiC MOSFET is turned on again at which indicates that there will be no voltage and current crossing in theory. After the transient turn-off t6. Then, turn-off period ofSiC theMOSFET hybrid switches is on completed. TheThen, deadthe time Td1 and delayoftime period of the IGBT is finished, the is turned again at t6. turn-off period the T d2, which have is a significant on the switching carefully designed. To verify hybrid switches completed.effect The dead time Td1 and loss, delayneed time to Td2be , which have a significant effect the proposed hybrid switching method,designed. the series switches arehybrid applied to a common on the switching loss, need to be carefully To hybrid verify the proposed switching method, circuit-double pulse test, which is presented in the circuit-double following sections. the series hybrid switches are applied to a common pulse test, which is presented in the following sections. 3.2. Hybrid Soft Switching Method Analysis in Double Pulse Test 3.2. Hybrid Soft Switching Method Analysis in Double Pulse Test The common double pulse test circuit is given in the dashed box in Figure 3a. When testing the The common double circuitoff is given the dashed in Figure 3a. an When testingThe the performance of switch S2,pulse S1 istest turned all theintime and is box paralleled with inductor. performance switch S2, is S1given is turned offBy allanalyzing the time and paralleled with ancurrent inductor. The double pulse of drive signal to S2. the is voltage Vce and the Ice of S2double in the pulse drive signalperiod, is givenInformation, to S2. By analyzing voltage Vce and the current Ithe S2 in the whole ce of whole switching such asthe collector-emitter overvoltage, reverse recovery switching Information, collector-emitter overvoltage, reversevoltage recovery current of current of period, diode, and switchingsuch lossascan be found. As the overlap ofthe switch’s and current diode, and switching loss, loss can found. As theaoverlap switch’s such voltage current the decide the switching thisbe paper provides way toof minimize lossand in order todecide achieve a switching loss, this paper provides a way to minimize loss in orderdouble-pulse to achieve a better performance better performance of IGBT. Figure 3a shows a new such hybrid switches testing circuit. S3 of aIGBT. Figure 3a shows a new hybrid switches testing circuit.S1S3isisturned a silicon is silicon carbide MOSFET connected in seriesdouble-pulse with the primary circuit. offcarbide all the MOSFET connected in series the on primary turned off off first all the time. S2 is about to time. When S2 is about to bewith turned or off,circuit. S3 willS1beisturned and lastWhen for a specific time. be turned on or off, S3 will be turned off first and last for a specific time. After the switching transition After the switching transition of S2 is finished, S3 will be turned on again, as shown in Figure 2b. of S2 isthe finished, S3 willoff, be the turned on again, shown in Figure Whentothe S3 is turned off,and the When S3 is turned current that isas passed through S2 2b. is forced zero. The voltage is passed through S2 isare forced to zero. Thethe voltage and current states of three switches current that states of three switches different from conventional one. There are six stagesare in different from the conventional one. There are six stages in switching-on or off period. switching-on or off period.

Inductor

Gate driver Si IGBT Gate driver

SiC MOSFET

DC input

(a)

(b)

Figure and, (b) (b) DPT DPT platform. platform. Figure 3. 3. Double Double Pulse Pulse Test Test (DPT) (DPT) for for the the hybrid hybrid switches switches (a) (a) DPT DPT Circuit; Circuit; and,

3.2.1. Turn-On Period According to the proposed gate signals for the hybrid switches, which is shown in Figure 2b, there are six stages for the IGBT turn-on period t1~t3. Stage 1—before t1: S1 and S2 are off-state,

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3.2.1. Turn-On Period According to the proposed Energies 2018, 11, x FOR PEER REVIEW gate signals for the hybrid switches, which is shown in Figure 6 of2b, 16 there are six stages for the IGBT turn-on period t1~t3. Stage 1—before t1: S1 and S2 are off-state, while S3 is on-state. At thisAttime, voltage of S2 V equals to input voltage Vin . Current of S2of Is2S2 and while S3 is on-state. this the time, the voltage ofS2S2 VS2 equals to input voltage Vin. Current Is2 S3 whilewhile the current of S1 of Is1 S1 equals to thetonegative current of inductor IL ; Stage 2—at andIs3S3are Is3zero, are zero, the current Is1 equals the negative current of inductor IL; Stage t1: S3 t1: is turned off at time There is no voltage transfer in the in circuit. The voltage will stay S2. 2—at S3 is turned off att1. time t1. There is no voltage transfer the circuit. The voltage willonstay The current states of all the do not do change too; Stage duringduring this time, states on S2. The current states of switches all the switches not change too;3—t1~t2: Stage 3—t1~t2: thisthe time, the of current and theand voltage on each on switch keepstill unchanged; Stage 4—at t2: Figure 4a illustrates states of current the voltage eachstill switch keep unchanged; Stage 4—at t2: Figure 4a the equivalent of hybrid switches double-pulse test at t2 in thetest switching-on period. As soon illustrates the circuit equivalent circuit of hybrid switches double-pulse at t2 in the switching-on as S2 is As turned S2the transfers ofto S3the VS3voltage , whichof means VS3 equals period. soonon, as the S2 isvoltage turnedofon, voltagetoofthe S2voltage transfers S3 VS3that , which means to Vin now. Redtoarrows show current of each switch. of S3’s capacitor charged by the DC source. that VS3 equals Vin now. Redthe arrows show the current each switch.isS3’s capacitor is charged by The current of inductor IL flows to the parallel diode. Theparallel S2’s capacitor discharged by itself. the DC source. The current of inductor IL flows to the diode. voltage The S2’sis capacitor voltage is S3’s capacitor stop untilwill VS3 stop equals to Vinuntil . Stage this5—t2~t3: time, theduring states discharged by will itself. S3’scharge capacitor charge VS3 5—t2~t3: equals to during Vin. Stage of andstates the voltage on each still keep unchanged; Stage 6—at t3: FigureStage 4b shows thiscurrent time, the of current and switch the voltage on each switch still keep unchanged; 6—atthe t3: equivalent circuitthe of equivalent hybrid switches test at double-pulse t3 in the switching-on period. As soon as Figure 4b shows circuitdouble-pulse of hybrid switches test at t3 in the switching-on S3 is turned on again, S1’son diode reverse recovery current flow recovery to S2. It brings theflow overcurrent period. As soon as S3ILisand turned again, IL and S1’s diode reverse current to S2. It of I as a consequent. The S3’s capacitor voltage is discharged by itself. The voltage on the inductor brings s3 the overcurrent of Is3 as a consequent. The S3’s capacitor voltage is discharged by itself. The equals the whole period is finished. voltagetoonVthe inductor equalsswitching-on to Vin; then, the whole switching-on period is finished. in ; then,

Vs3

Is3 S3

S1

IL

DC

Is1 (Turn on)

S2

VS2

Is2 (a)

(b)

Figure 4. Turn-on period (a) Stage 4-at t2; and, (b) Stage 6-at t3. Figure 4. Turn-on period (a) Stage 4-at t2; and, (b) Stage 6-at t3.

3.2.2. Turn-Off Period 3.2.2. Turn-Off Period According to the proposed gate signals for the hybrid switches, which is shown in Figure 2b, According to the proposed gate signals for the hybrid switches, which is shown in Figure 2b, there are also six stages for the IGBT turn-off period t4~t6. Stage 1—before t4: Before t4, S2 and S3 there are also six stages for the IGBT turn-off period t4~t6. Stage 1—before t4: Before t4, S2 and S3 are on-state, while S1 is off-state. At this time, the voltage of S1 equals to input voltage Vin. Is2 and Is3 are on-state, while S1 is off-state. At this time, the voltage of S1 equals to input voltage Vin . Is2 and equal to IL; Stage 2—at t4: S3 is turned off at time t4. The equivalent circuit of hybrid switches Is3 equal to IL ; Stage 2—at t4: S3 is turned off at time t4. The equivalent circuit of hybrid switches double-pulse test at t4 in switching-off period is shown in Figure 5a. S3’s capacitor is charged by the double-pulse test at t4 in switching-off period is shown in Figure 5a. S3’s capacitor is charged by the DC source until VS3 equals to Vin. IL flows to the parallel diode of S2, while Is2 falls to zero; Stage DC source until VS3 equals to Vin . IL flows to the parallel diode of S2, while Is2 falls to zero; Stage 3—t4~t5, Stage 4—at t5, Stage 5—t5~t6: during this time, the states of current and the voltage on 3—t4~t5, Stage 4—at t5, Stage 5—t5~t6: during this time, the states of current and the voltage on each each switch still keep unchanged until S3 is turned on again. Stage 6—at t6: Figure 5b gives the switch still keep unchanged until S3 is turned on again. Stage 6—at t6: Figure 5b gives the equivalent equivalent circuit of hybrid switches double-pulse test at t6 in the switching-off period. At time t6, circuit of hybrid switches double-pulse test at t6 in the switching-off period. At time t6, S3 is turned on. S3 is turned on. The S3’s capacitor voltage is discharged by itself until S3’s voltage falls to zero. Both The S3’s capacitor voltage is discharged by itself until S3’s voltage falls to zero. Both the inductor the inductor current and the S1’s reverse recovery current flow to S2. S2’s capacitor voltage is current and the S1’s reverse recovery current flow to S2. S2’s capacitor voltage is charged until VS2 charged until VS2 equals to Vin. Then, the whole switching-off period is finished. The current of S2 Is2 equals to Vin . Then, the whole switching-off period is finished. The current of S2 Is2 and S3 Is3 fall to and S3 Is3 fall to zero, while the freewheeling current of inductor flows to anti-parallel diode gain. zero, while the freewheeling current of inductor flows to anti-parallel diode gain.

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(a)

(b)

Figure 5. Turn-off period (a) Stage 2-at t4; and, (b) Stage 6-at t6.

Figure 5. Turn-off period (a) Stage 2-at t4; and, (b) Stage 6-at t6. (a) (b) 3.3. Simulation and Experimental Results

3.3. Simulation and Experimental Figure 5.Results Turn-off period (a) Stage 2-at t4; and, (b) Stage 6-at t6. 3.3.1. Simulation Results

SimulationResults and Experimental Results 3.3.1. 3.3. Simulation

The simulations are carried out by using MATLAB/Simulink software (R2015a) to analyze and

The simulations are theoretical carried outanalysis. by using MATLAB/Simulink (R2015a)are to given analyze to initially verify Results the The parameters are used software in the simulation in and 3.3.1. Simulation Table 1.verify Parasitic areanalysis. also considered for the devices. Vin = 400 V, Tare d1 = 2 us, in to initially theparameters theoretical The parameters are Input used voltage in the simulation given are carried out by MATLAB/Simulink software to analyze and = 1The us.simulations In the switching-on period, theusing voltage and states keepvoltage the(R2015a) same stages 1, 2, TableT1.d2 Parasitic parameters are also considered for thecurrent devices. Input Vinin=the 400 V, Td1 = 2 us, to initially verify the theoretical analysis. The parameters are used in the simulation are given in 3. During this time, V S2 = Vin, IS2 = 0, VS3 = 0, as shown in Figure 6a. S2 is turned on at t2. The Td2 = Table 1 us. 1. InParasitic the switching-on period, the voltage and current states keep the same in the stages 1, 2, 3. parameters are also considered for the voltage Vinthe = 400 V, Td1 =of2 S3 us, switching state becomes to S1S2S3 = 010. The voltage ondevices. S2 dropsInput to zero, while capacitor During this time, V = V , I = 0, V = 0, as shown in Figure 6a. S2 is turned on at t2. The switching S2 in S2 S3 the voltage and current states keep the same in the stages 1, 2, Td2charged = 1 us. In is tothe Vinswitching-on . S3 is turnedperiod, on again at t3. The switching state changes to S1S2S3 = 011. The state becomes to S1S2S3 =S2010. The drops to in zero, while the capacitor of at S3t2. is charged 3. During this time, V = V in, IS2voltage 0, Vcurrent S3 on = 0,S2as shown Figure S2 is turned The voltage on S3 is discharged to zero.=The flows through S3, the6a. inductor, and S2.onThe current to Vinrising . S3 isedge turned on again at t3. The switching state changes to S1S2S3 = 011. The voltage on switching state becomes to S1S2S3 = 010. The voltage on S2 drops to zero, while the capacitor of S3S3 is of S2 can be observed at t3. The voltage and current waveforms of S2 and S3 in the is charged to V in. S3current is turned on again at t3. The switching state changes to S1S2S3 = 011. The discharged to zero. The flows through S3, the inductor, and S2. The current rising edge switching-off period are shown in Figure 6b. S3 is turned off at t4. The switching state becomes toof S2 voltage S3 is current flows through and The current can be observed atThe t3.discharged The voltage and The current waveforms of S2 S3, and in the switching-off period are S1S2S3 =on 010. current of to S2zero. falls to zero, while the capacitor of the S3S3 isinductor, charged to VS2. in. The voltage rising edge of S2 can be observed at t3. The voltage and current waveforms of S2 and S3 shown inthe Figure 6b.states S3 iskeep turned at in t4.the The switching state becomes The current and current the off same stages 3, 4, 5. During this time,to VS3S1S2S3 = Vin, IS2==010. 0, VS2 = 0.in S3the is of switching-off period are shown in Figure 6b. S3 is turned off at t4. The switching state becomes turned on again at t6. The switching state changes to S1S2S3 = 001. The voltage on S3 drops to zero, S2 falls to zero, while the capacitor of S3 is charged to Vin . The voltage and the current statestokeep S1S2S3 = capacitor 010. The current of S2 falls to whileofthe capacitorofof S3 is charged to Vvoltage in. The voltage while is charged Vinzero, .time, Because the same inthe the stages of 3, S2 4, 5. Duringtothis VS3 =the Vinimpact , IS2 = 0,switches’ VS2 = 0. capacitor S3 is turned onchange again at t6. and the current states keep the same in the stages 3, 4, 5. During this time, V S3 = Vin, IS2 = 0, VS2 = 0. S3 is and parasitic inductor, there are current andThe voltage resonance happened in thewhile circuitthe which can be of S2 The switching state changes to S1S2S3 = 001. voltage on S3 drops to zero, capacitor turned onatagain The observed t2, t3,at t4,t6. and t6.switching state changes to S1S2S3 = 001. The voltage on S3 drops to zero, is charged impact switches’ capacitor voltage change and parasitic inductor, in . Because while to theVcapacitor of S2ofisthe charged to Vof in. Because of the impact of switches’ capacitor voltage change there and are parasitic current and voltage resonance happened the circuit which in can observed t2,bet3, t4, inductor, there are current and voltageinresonance happened thebe circuit whichat can Voltage drop Voltage rise and t6. observed at t2, t3, t4, and t6. Voltage drop Current rise

Current rise

(a)

Voltage rise Current drop

Current drop

(b)

Figure 6. Simulation results of double pulse test for the hybrid switches (Td1 = 2 us; Td2 = 1 us) (a) Turn-on; and, (b) Turn-off. (a) (b) Figure 6. Simulation results of double pulse test for the hybrid switches (Td1 = 2 us; Td2 = 1 us) (a)

Figure 6. Simulation results of double pulse test for the hybrid switches (Td1 = 2 us; Td2 = 1 us) Turn-on; and, (b) Turn-off. (a) Turn-on; and, (b) Turn-off.

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Table The double Energies 2018, 11, x FOR PEER1.REVIEW

pulse test for the hybrid switches parameters.

Parameter Table 1. The Value double pulse test for the hybrid switches parameters.

Parameter Input voltage Parameter Td1 Input voltage Si IGBT Gate Resistor Td1 Si IGBT

Si IGBT Gate Resistor Si IGBT

400/580 Value V 2 us 400/580 V R=1Ω 2 us SKM100GB12T4 1.2 KV/100 A R=1Ω SKM100GB12T4 1.2 KV/100 A

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Value

Inductor Parameter T Inductord2 SiC MOSFET Gate Resistor Td2 SiC MOSFET

SiC MOSFET Gate Resistor SiC MOSFET

Value 1 mH 1/0.7 us 1 mH Ron = 5 Ω/Roff = 2.5 Ω 1/0.7 us CAS120M12BM2 1.2 kV/120 A Ron = 5 Ω/Roff = 2.5 Ω CAS120M12BM2 1.2 kV/120 A

3.3.2. Experimental Results 3.3.2. Experimental Results

1.

V-I Switching waveforms

1.

V-I Switching waveforms

For further verification, experimental results are also carried out. The parameters are listed For further verification, experimental results are also carried out. The parameters are listed in in Table 1. Figure 7a,b shows the common double pulse test results for IGBT. Both in the turn-on and Table 1. Figure 7a,b shows the common double pulse test results for IGBT. Both in the turn-on and the the turn-off are overlaps overlapsbetween betweenvoltage voltage and current waveforms, which cause switching turn-offperiod, period, there there are and current waveforms, which cause switching losses-turn-on lossloss EonEand turn-off loss Eoff . It can be seen that IGBT operates under hard switching losses-turn-on on and turn-off loss E off. It can be seen that IGBT operates under hard switching condition in the common double pulse test. IGBT SKM100GB12T4 MOSFET module condition in the common double pulse test. IGBT module module SKM100GB12T4 andand SiCSiC MOSFET module CAS120M12BM2 areare adopted forforthe double-pulse experiment. Figure 3b shows CAS120M12BM2 adopted thehybrid hybridswitches switches double-pulse experiment. Figure 3b shows the the hardware platform. this test,Td2 Td2isis only only 0.7 0.7 us, thatthat the the MOSFET turn-off hardware test test platform. In In this test, us,which whichcan canguarantee guarantee MOSFET turn-off transition is completed. Typical waveformsfor for the the turn-on turn-off (102(102 A) during the test transition is completed. Typical waveforms turn-on(87 (87A)A)and and turn-off A) during the test are shown in Figure 7c,d. are shown in Figure 7c,d.

Eoff

Eon

(a)

(b)

Voltage drop Current rise Eon

(c)

Voltage rise Current drop

Eoff

(d)

Figure 7. Experimental comparison results of IGBT V-I curves in different double pulse test (a) IGBT

Figure 7. Experimental comparison results of IGBT V-I curves in different double pulse test (a) IGBT turn-on transition in the common DPT; (b) IGBT turn-off transition in the common DPT; (c) IGBT turn-on transition in the common DPT; (b) IGBT turn-off transition in the common DPT; (c) IGBT turn-on transition in DPT with hybrid switches; and, (d) IGBT turn-off transition in DPT with hybrid turn-on transition in DPT with hybrid switches; and, (d) IGBT turn-off transition in DPT with switches. hybrid switches.

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In the turn-on period, S3 is turned off at t1. The voltage of S2 is equal to the input voltage. After S3 finished its turn-off period, the S2 will be turned on at t2. As shown in Figure 7c, the voltage of S2 drops to zero. The capacitor of S3 will be charged by the DC source. Due to the impact of switches’ capacitor voltage change and the parasitic inductor, there is resonance that happened in the circuit. It can be observed a resonant current go through S2, which occurred in the dynamic period. S3 is turned on again at t3. The capacitor of S3 will be discharged to zero, while the voltage S1 equals to Vin . Because the freewheeling diode of S1 stops to conduct, the freewheeling current will directly go to S2. In addition, the reverse recovery current of the diode also flows to S2 which leads overshoot of the IGBT current at t3. Meanwhile, a small bump appears in IGBT voltage curve. It is caused by the bipolar IGBT physics since conductivity modulation needs time and current to establish. With the voltage bump that is generated by high dI/dt, there is some additional overlapping; hence, the turn-on loss is not zero. After the current is stable to the set value, the turn-on transition of the hybrid switches is finished. With the help of SiC MOSFET, the turn-on behavior of the IGBT under this condition can be defined as ZVHC turn-on. However, it can be seen that there still have the switching-on loss of IGBT, which consists of the loss occur at t2 and t3. In the turn-off period, S3 is turned off at t4, as shown in Figure 7d. The voltage of S3 rises to Vin . At the same time, the current of S2 drops to zero. As aforementioned, there is also current resonance happened during the dynamic period. After S3 finished its turn-off period, the S2 will be turned off at t5. The current and voltage states on each switch keep unchanged. After 1.3 us, S3 is turned on again. The overshoot of voltage can be observed caused by the stray inductance in the circuit. It is higher than hard-switching’s, because of the high di/dt that is caused by the SiC MOSFET fast switching-on speed. With the high dV/dt happens on S2, a current bump is found because the stored carriers still need more time to recombine. The current bump brings the overlapping of current and voltage, which causes additional switching-off loss. It is the main reason that the switching-off loss is not zero as theoretical analysis. When the voltage S2 is equal to the DC input voltage, the turn-off transition of the hybrid switches is finished. There also have two parts of switching-off loss of IGBT that occur at t4 and t6. With the help of SiC MOSFET, the turn-off behavior of the IGBT can be defined as ZCHV turn-off. 2.

Switching loss comparison

According to the new V-I curves of IGBT in the hybrid switches, the overlap of current and the voltage in turn-on period and turn-off period are much smaller when compared to the hard switching’s. The IGBT’s dynamic switching loss is efficiently reduced since it is the integration of voltage and current of the overlap [25]. As shown in Figure 7c,d, there are two parts of IGBT switching loss happened both during the turn-on and turn-off period. In this section, the common double pulse test experimental results also are carried out. The same type of IGBT is introduced in the test to get the switching loss under hard switching condition. As shown in Figure 8, the comparison results of switching loss under hard switching and soft switching at a different level of current are given in both the turn-on and turn-off period. In the turn-on period, the current is varies in the range of 0~90 A. As shown in Figure 8a, the red line is the switching-on loss under hard switching condition, while the green line is the switching-on loss under ZVHC turn-on condition. It can be seen that there still has a small switching-on loss for IGBT under ZVHC turn-on condition because of the voltage bump. However, at 87 A, more than 90% IGBT turn-on dynamic loss is reduced with the help of SiC MOSFET. During the turn-off period, the current varies in the range of 0~102 A. As shown in Figure 8b, at 102 A, only 57% turn-off loss is reduced in the turn-off period. There still has a considerable switching-off loss for IGBT under the ZCHV turn-off condition because of the current bump. Further study about the current bump is given in the following section.

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(a)

50% Reduction

(b)

Figure8.8. IGBT losses comparison during on/offon/off periodsperiods (a) Turn-on loss; and,loss; (b) Turn-off Figure IGBTswitching switching losses comparison during (a) Turn-on and, loss. (b) Turn-off loss.

3.

3.

Parameters design Parameters design

There are two critical parameters in the design of SiC MOSFET gate signal, which are the dead There are two critical parameters in the design of SiC MOSFET gate signal, which are the dead time time Td1 and the delay time Td2. For the design of the delay time Td2, the primary concern is making Td1 and the delay time Td2 . For the design of the delay time Td2 , the primary concern is making sure sure that the turn-off transition of SiC MOSFET is completed during this time. It can keep the whole that the turn-off transition of SiC MOSFET is completed during this time. It can keep the whole circuit circuit from the overlap of the SiC MOSFET switching transition time and the IGBT switching from the overlap of the SiC MOSFET switching transition time and the IGBT switching transition time. transition time. As mentioned previously, there is voltage bump in the IGBT’s turn-on period since As mentioned previously, there is voltage bump in the IGBT’s turn-on period since the conductivity the conductivity modulation needs more time and current to establish, while there is a current modulation needs more time and current to establish, while there is a current bump in the IGBT’s bump in the IGBT’s turn-off period because stored carriers need more time to recombine. As a turn-off period because stored carriers need more time to recombine. As a result, the states of the result, the states of the voltage bump and the current bump are decided by the times of t2~t3 and voltage bump and the current bump are decided by the times of t2~t3 and t5~t6. When Td2 is fixed, t5~t6. When Td2 is fixed, the dead time Td1 becomes the critical factor that affects the voltage and the the dead time Td1 becomes the critical factor that affects the voltage and the current bumps. Moreover, current bumps. Moreover, the switching losses of IGBT will also change with different Td1. the switching losses of IGBT will also change with different Td1 . As shown in Figure 7d, there is considerable a current bump, which is the main reason for the As shown in Figure 7d, there is considerable a current bump, which is the main reason for the significant switching-off loss under ZCHV turn-off condition. In order to reduce the switching-off significant switching-off loss under ZCHV turn-off condition. In order to reduce the switching-off loss, loss, the relationship between the current bump, and the dead time Td1 is studied in this section. the relationship between the current bump, and the dead time Td1 is studied in this section. When the When the Td2 is fixed to 0.7 us, the turn-off current bumps of IGBT with various Td1 are shown in Td2 is fixed to 0.7 us, the turn-off current bumps of IGBT with various Td1 are shown in Figure 9a. Figure 9a. It can be seen that the current bump is getting smaller with the increase of Td1. As the It can be seen that the current bump is getting smaller with the increase of Td1 . As the charge Q is the charge Q is the time integral of current, the Q is relatively decreased with a smaller current bump. time integral of current, the Q is relatively decreased with a smaller current bump. As a result, the As a result, the switching-off loss is also reduced, which is shown in Figure 9b. When the dead time switching-off loss is also reduced, which is shown in Figure 9b. When the dead time increases to 6 us, increases to 6 us, 80% IGBT dynamic turn-off loss is decreased. Moreover, the voltage overshoot of 80% IGBT dynamic turn-off loss is decreased. Moreover, the voltage overshoot of IGBT can be also IGBT can be also improved. However, the dead time also has an influence on the effective duty improved. However, the dead time also has an influence on the effective duty cycle for the switch. cycle for the switch. With a larger dead time, the distortion of output waveform will be more With a larger dead time, the distortion of output waveform will be more serious when the hybrid serious when the hybrid switches apply to the practical circuit. As a result, there is a trade-off switches apply to the practical circuit. As a result, there is a trade-off between the switching loss and between the switching loss and the duty loss for the design of the dead time. Moreover, with the the duty loss for the design of the dead time. Moreover, with the application of different IGBT, the application of different IGBT, the state of the current bump will be different too. As shown in state of the current bump will be different too. As shown in Figure 10, Another MG300J2YS50 IGBT Figure 10, Another MG300J2YS50 IGBT is also tested. Unlike Figure 9a, the relationship between Td1 is also tested. Unlike Figure 9a, the relationship between Td1 and the current bump is also changed. and the current bump is also changed. The current bump can be cut down significantly by choosing The current bump can be cut down significantly by choosing the value of Td1 as 3 us instead of 2 us. the value of Td1 as 3 us instead of 2 us. However, there is barely reduction of the current bump However, there is barely reduction of the current bump when Td1 is longer than 4 us. In order to when Td1 is longer than 4 us. In order to achieve the best design of Td1 with the consideration of achieve the best design of Td1 with the consideration of distortion and switching loss reduction, the distortion and switching loss reduction, the current bump state of IGBT is also essential to study. current bump state of IGBT is also essential to study.

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40% Reduction 40% Reduction 50% Reduction 50% Reduction 60% Reduction 60% Reduction 80% 80% Reduction Reduction Q (Td1 =6us ) Q (Td1 =6us )

(a) (a)

(b) (b)

Figure 9. IGBT ZCHV turn-off current bumps and the turn-off losses with various Td1 (a) ZCHV Figure 9. 9. IGBT ZCHV turn-off current bumps and thethe turn-off losses with various Td1Td1 (a)(a) ZCHV Figure IGBT ZCHV turn-off current bumps and turn-off losses with various ZCHV turn-off the current bumps in the IGBT with various Td1; and, (b) The IGBT ZCHV turn-off losses turn-off thethe current bumps in the with with various Td1 ; and, The turn-offturn-off losses with and, (b)IGBT The ZCHV IGBT ZCHV losses turn-off current bumps in IGBT the IGBT various Td1; (b) with various Td1. various T . d1 with various Td1.

(a) (a)

(b) (b)

Figure 10. (a) Hybrid switches DPT test platform with a different IGBT; and, (b) A different IGBT Figure 10. (a) Hybrid switches DPT test platform with a different IGBT; and, (b) A different IGBT Figure (a) Hybrid switches platform ZCHV10. turn-off current bumpsDPT with test various Td1. with a different IGBT; and, (b) A different IGBT ZCHV turn-off current bumps with various Td1. ZCHV turn-off current bumps with various Td1 .

4. Optimization and Application 4. Optimization and Application 4. Optimization and Application 4.1. Improved Modulation for the Hybrid Switches 4.1. Improved Modulation Hybrid Switches 4.1. Improved Modulation forfor thethe Hybrid Switches 4.1.1. Improved Modulation 4.1.1. Improved Modulation 4.1.1. Improved Modulation With the help of the hybrid switching method, the IGBT dynamic switching is reduced With help the hybrid switching the method, dynamic the IGBT dynamic switching is reduced With the the help of theofhybrid switching switching is reduced significantly. significantly. However, there’s still has method, considerableIGBT switching loss, especially the switching-off loss. significantly. However, there’s still has considerable switching loss, especially the switching-off loss. However, there’s has considerable switching especially the switching-off loss. To improve To improve thestill performance of the hybrid loss, switches, an improved modulation method is the also To improve the performance of the hybrid switches, an improved modulation method is also performance of shown the hybrid switches, an improved modulation method also proposed. As shown proposed. As in Figure 11, the IGBT is turned on at t1. Then, is the MOSFET is turned on atint2. proposed. As shown in Figure 11, the IGBT isMOSFET turned on at t1. Then, the MOSFET is turned on att1t2. Figure 11, the IGBT is turned on at t1. Then, the is turned on at t2. The delay time between The delay time between t1 and t2 is Td3. At t3, the MOSFET is turned off first. After another delay The delay time between t1 and t2 is T d3 . At t3, the MOSFET is turned off first. After another delay and t2 is . AtIGBT t3, the is turned off first.ofAfter delayhappened time Td4 , on the the IGBT is turned off time Td4T,d3the is MOSFET turned off at t4. Instead highanother dV/dt that IGBT, the IGBT time Td4, the IGBT is turned off at t4. Instead of highthe dV/dt that happened on the by IGBT, the IGBT atwill t4. Instead of high dV/dt that happened on the IGBT, IGBT will have low dV/dt sharing the have low dV/dt by sharing the input voltage with the MOSFET naturally. ZCZV turn-off can be willvoltage have low dV/dt by sharingnaturally. the inputZCZV voltage with the naturally. ZCZV turn-off can be input with the turn-off canMOSFET be realized, as shown in Figure 1 (b4). realized, as shown inMOSFET Figure 1(b4). realized, as shown in Figure 1(b4).

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Figure Improvedmodulation modulation for switches. Figure 11.11.Improved forthe thehybrid hybrid switches.

4.1.2. Simulation Results

4.1.2. Simulation Results

11. Improved modulation for the hybrid switches. for the double test are Simulation results ofFigure the hybrid switches with the improved modulation

Simulation results ofinthe hybrid with the for the double carried out, as shown Figure 12. switches The parameters are improved used in the modulation simulation are given in Tabletest 1. are 4.1.2. Simulation carried out,voltage as shown Figure arethe used in the simulation givenand in Table 1. Input Vin Results =in400 V, Td312. = 1The us, parameters Td4 = 1 us. In turn-on period, both S2are (IGBT) S3 are off-state before t1. The current of S2 I S2 is zero. The input voltage is shared by these Input(MOSFET) voltage V = 400 V, T = 1 us, T = 1 us. In the turn-on period, both S2 (IGBT) and S3 (MOSFET) in d4 switches with the improved modulation for the double test are Simulation resultsd3 of the hybrid two switches. The S2 turned at t1, in are Figure Thesimulation voltage onare thegiven IGBTin drops to1. are off-state before t1. Theisin current of12. S2The IS2as isshown zero. The input voltage is shared by these two switches. carried out, as shown Figureon parameters used12a. in the Table zero, while the voltage on the S3 increases to the input voltage. With the smaller dV/dt, it can be seen voltage in t1, = 400 V, Td3 =in1 Figure us, Td4 12a. = 1 us. Involtage the turn-on period, S2 to (IGBT) S3 the The S2Input is turned onVat as shown The on the IGBTboth drops zero,and while that the resonant happened in the circuit is muchofsmaller when compared tovoltage Figureis6a. After abydelay (MOSFET) are off-state before t1. The current S2 I S2 is zero. The input shared these voltage on the S3 increases to the input voltage. With the smaller dV/dt, it can be seen that the resonant time d3, S3 is turned on. A high di/dt still can be observed. Figure 12b gives the V-I waveforms of two Tswitches. The S2isismuch turned on at t1, as shown in Figure 12a. The6a. voltage the IGBT drops happened in the circuit smaller when compared to Figure Afteron a delay time Td3 ,toS3 is the turn-off transition period. S3 increases is turnedtooff atinput t3. IS2 falls toWith zero,the while thedV/dt, voltage on S3 VS3 zero, while the voltage on the S3 the voltage. smaller it can be seen turned on. A to high di/dt still can behigh observed. Figure 12bagives thethat V-I happened waveforms of the turn-off increases 400 V. Because of the dV/dt, there is still resonant in the circuit. that the resonant happened in the circuit is much smaller when compared to Figure 6a. After a delay transition period. S3 isoff turned off voltage at t3. IS2 falls to zero, while the voltage on S3 VS3input increases to 400 V. When S2d3,isS3 turned aton. t4,A the S2 V S2 starts to increase slowly to share the the input time T is turned high di/dtofstill can be observed. Figure 12b gives the V-I waveforms of Because of the high dV/dt, there is still a resonant that happened in the circuit. When S2 is turned voltage with S3. Since there is low that off is applied the IGBT when compared to Figure the turn-off transition period. S3 dV/dt is turned at t3. IS2tofalls to zero, while the voltage on S36b, VS3 off atFigure t4, the12b voltage of VS2 starts to increase to share the input inputisin voltage with S3. defined as ZCZV (Zero Current Zero is Voltage) turn-off. The the resonant eliminated increases tois400 V. S2 Because of the high dV/dt, slowly there still a resonant that happened the circuit. due to the small onto S2.the thetostored carriers oftoIGBT more time to Sinceeffectively there dV/dt that is dV/dt applied when compared to Figure 6b,have Figure 12b isinput defined WhenisS2low is turned off at t4, the voltage ofMoreover, S2IGBT VS2 starts increase slowly share the input the recombine with small dV/dt, which helps toisreduce the bump. As a result, the dynamic as ZCZV (Zero Current Zero Voltage) turn-off. resonant is eliminated effectively due to the6b, small voltage with S3.the Since there is low dV/dt thatThe applied tocurrent the IGBT when compared to Figure turn-off loss of IGBT can be reduced effectively under the ZCZV turn-off condition. In addition, the Figure 12b is defined as ZCZV (Zero Current Zero Voltage) turn-off. The resonant is eliminated dV/dt on S2. Moreover, the stored carriers of IGBT have more time to recombine with the small dV/dt, switched onsmall or offdV/dt for one in the improved modulation. Itofhelps simplify the design effectively due to the the ontime S2. aMoreover, stored carriers IGBT have time to whichMOSFET helps toisreduce current bump. As result, thethe dynamic turn-off loss of IGBTmore can be reduced and implement of the gate signal of MOSFET. For the design of the delay time, the main consideration recombine with smallturn-off dV/dt, which helps toInreduce the current bump. Asisaswitched result, theon dynamic effectively under thethe ZCZV condition. addition, the MOSFET or off for ofturn-off Td3 is still a of trade-off between voltageeffectively bump and distortion. Unlike Td3, Td4condition. only needIntoaddition, make sure loss IGBT can be reduced under the ZCZV turn-off the one time in the improved modulation. It is helps simplify the design and implement of the gateof signal the switching-off transition finished in this time. In conclusion, better performance MOSFET is switched on orofoffMOSFET for one time in the improved modulation. It helps simplify the design of MOSFET. For the design of the delay time, the main consideration of T is still a trade-off between d3 IGBT can be achieved withsignal the improved modulation in theofhybrid switches. Further application and implement of the gate of MOSFET. For the design the delay time, the main consideration voltage bump and distortion. Unlike T , T only need to make sure the switching-off transition of circuit of the hybrid switches is given in the next section. d3 d4 of Td3 is still a trade-off between voltage bump and distortion. Unlike Td3, Td4 only need to make sure MOSFET is finished intransition this time. conclusion, betterinperformance of IGBT can be achieved with the switching-off of In MOSFET is finished this time. In conclusion, better performance of the improved modulation in the hybrid switches. Further application circuit of the hybrid switches IGBT can be achieved with the improved modulation in the hybrid switches. Further application is given circuit in the of next the section. hybrid switches is given in the next section.

(a)

(b)

Figure 12. Simulation results of double pulse test for the hybrid switches with improved modulation (a) Zero Current Hard Voltage (ZCHC) turn-on; and, (b) Zero Current Zero Voltage (ZCZV) turn-off.

(a)

(b)

Figure 12. Simulation results of double pulse test for the hybrid switches with improved modulation

Figure 12. Simulation results of double pulse test for the hybrid switches with improved modulation (a) Zero Current Hard Voltage (ZCHC) turn-on; and, (b) Zero Current Zero Voltage (ZCZV) turn-off. (a) Zero Current Hard Voltage (ZCHC) turn-on; and, (b) Zero Current Zero Voltage (ZCZV) turn-off.

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4.2. Hybrid Switching Method Apply to HERIC Inverter 4.2. Hybrid Switching Method Apply to HERIC Inverter 4.2.1. Configuration and 4.2.1. Configuration and Modulation Modulation 4.2.1. Configuration and Modulation In with thethe helphelp of SiC the dynamic loss IGBT efficiently reduced. In the theprevious previoussections, sections, with of MOSFET, SiC MOSFET, the dynamic lossis IGBT is efficiently In the previous sections, with the be help of SiCtoMOSFET, thecircuit. dynamic loss IGBT is efficiently This hybrid switching method also can applied a practical As shown in Figure 13, an reduced. This hybrid switching method also can be applied to a practical circuit. As shown in Figure reduced. This hybrid switching method alsothe can be appliedoftothe a practical circuit. As shown in Figure improved HREIC inverter is proposed with application hybrid switches. Two SiC MOSFETs 13, an improved HREIC inverter is proposed with the application of the hybrid switches. Two SiC 13, an improved HREIC inverter is proposed with the application of the hybrid13a. switches. Two SiC and two diodes are added to common circuit, as shown The additional MOSFETs and two diodes arethe added to theHERIC common HERIC circuit,inasFigure shown in Figure 13a. The MOSFETs and two diodes are added to the common HERIC circuit, as shown in Figure 13a. The diodes are introduced prevent the IGBT S1/S2 from freewheeling. The improved modulation additional diodes areto introduced to prevent the current IGBT S1/S2 from current freewheeling. The additional diodes introduced to the IGBT from of current freewheeling. for the newmodulation HERIC are inverter is given in prevent the Figure 13b. The S1/S2 modulation switches keep The the improved for the new HERIC inverter is given in the Figure 13b. TheS1~S5 modulation of improved modulation forone, the while new HERIC inverter is given in the Figure 13b. Theaccording modulation of same as the conventional the gate signals for the MOSFET are designed to the switches S1~S5 keep the same as the conventional one, while the gate signals for the MOSFET are switches S1~S5 keep the same as the conventional one, while the gate signals for the MOSFET are improved hybrid switches The gate signalsmodulation. detail in theThe positive negative is designed according to the modulation. improved hybrid switches gate and signals detailcycle in the designed according to the improved hybrid switches modulation. The gate signals detail in the given in and Figure 14. positive negative cycle is given in Figure 14. positive and negative cycle is given in Figure 14.

(a) (a)

(b) (b)

Figure 13. 13. Improved with hybrid switching switching method Figure Improved HERIC HERIC inverter inverter circuit circuit and and modulation modulation with the the Figure 13. Improved HERIC inverter circuit and modulation with the hybrid hybrid switching method method application (a) Improved HERIC inverter; (b) Improved modulation. application application (a) (a) Improved Improved HERIC HERIC inverter; inverter; (b) (b) Improved Improved modulation. modulation.

(a) (a)

(b) (b)

Figure 14. Gate signals of IGBT and MOSFET (a) The positive cycle; and, (b) The negative cycle. Figure 14. 14. Gate of IGBT IGBT and and MOSFET MOSFET (a) (a) The The positive positive cycle; cycle; and, and, (b) (b) The The negative negative cycle. cycle. Figure Gate signals signals of

In the positive cycle, S2, S3, S6, and S7 are off-state, while S5 is turned on. S1, S4, and S8 In the positive cycle, S2, S3, S6, and S7 are off-state, while S5 is turned on. S1, S4, and S8 operate at high frequency. AsS3, shown in S7 Figure 14a, S14S8 = 000 t1. on. TheS1, freewheeling current In the positive cycle, S2, S6, and are off-state, while S5before is turned S4, and S8 operate operate at high frequency. As shown in Figure 14a, S14S8 = 000 before t1. The freewheeling current goes through the anti-paralleled S6 and S5.=S1000 andbefore S4 aret1. turned on at t1. The voltage S1 at high frequency. As shown in diode Figureof14a, S14S8 The freewheeling currenton goes goes through the anti-paralleled diode of S6 and S5. S1 and S4 are turned on at t1. The voltage on S1 and S4 are to zero by themselves. theturned D9, the current to through thedischarged anti-paralleled diode of S6 and S5.By S1adopting and S4 are onfreewheeling at t1. The voltage on goes S1 and and S4 are discharged to zero by themselves. By adopting the D9, the freewheeling current goes to S1 is blocked. There is no current flow to S4 either because S8 is turned off at this time. In S4 are discharged to zero by themselves. By adopting the D9, the freewheeling current goes to S1 S1 is blocked. There is no current flow to S4 either because S8 is turned off at this time. In conclusion, the freewheeling current keeps the S8 same beforeofft2.at S8 turned on at t2. The is blocked. There is no current flow to S4path either because is turned thisistime. In conclusion, the conclusion, the freewheeling current path keeps the same before t2. S8 is turned on at t2. The currents of S1current and S4 path start keeps to increase. Thebefore inverter in the mode, whichofmeans freewheeling the same t2. operates S8 is turned on active at t2. The currents S1 andthat S4 currents of S1 and S4 start to increase. The inverter operates in the active mode, which means that the current flowsThe through S1,operates ac side, in S4,the S8,active and D10. output voltage VABcurrent is equal to the input start to increase. inverter mode,The which means that the flows through the current flows through S1, ac side, S4, S8, and D10. The output voltage VAB is equal to the input voltage. As S4, theS8, turn-on transition is finished, it V can be achieved that there is a gap between S1, ac side, and D10. The output voltage is equal to the input voltage. As the turn-on AB be achieved that there is a gap between the voltage. As the turn-on transition is finished, it can the voltage falling edge and the current rising edge of IGBT. As a result, the dynamic turn-on losses of voltage falling edge and the current rising edge of IGBT. As a result, the dynamic turn-on losses of S1 and S4 can cut down. At t3, S8 is turned off first. The currents of S1 and S4 fall to zero, while the S1 and S4 can cut down. At t3, S8 is turned off first. The currents of S1 and S4 fall to zero, while the

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transition finished, it can be achieved that there is a gap between the voltage falling edge and the Energies 2018,is11, x FOR PEER REVIEW 14 of 16 current rising edge of IGBT. As a result, the dynamic turn-on losses of S1 and S4 can cut down. At t3, freewheeling flows to theofanti-paralleled diode S6 and again. Thecurrent voltages of S1 S8 is turned offcurrent first. The currents S1 and S4 fall to zero,of while the S5 freewheeling flows toand the S4 start to increase S4 are The turned off atoft4.S1There is start also to a gap between anti-paralleled diodewhen of S6 S1 andand S5 again. voltages and S4 increase whenthe S1 current and S4 falling edge theThere voltage rising edge of IGBT, helpedge to reduce the dynamic turn-off are turned offand at t4. is also a gap between thewhich currentwill falling and the voltage rising edge losses ofwhich S1 andwill S4.help The to gate signals the negative cycle areofshown theThe Figure With the of IGBT, reduce the in dynamic turn-off losses S1 andinS4. gate 14b. signals in the same operation principle, is Figure also able helpthe IGBT S2 operation and S4 cutprinciple, down the switching negative cycle are shown inS7the 14b.toWith same S7dynamic is also able to help loss inS2the negative cycle. the dynamic switching loss in the negative cycle. IGBT and S4 cut down 4.2.2. 4.2.2. Simulation Results With With the the proposed proposed modulation, modulation, the the output output voltage voltage of of the the improved improved HERIC HERIC inverter inverter is is perfect perfect 240 The improved inverter works as a regular of the common HERIC inverter. 240 V/60 V/60 Hz Hzsinusoidal sinusoidalwave. wave. The improved inverter works as a regular of the common HERIC Figure 15Figure shows15the simulated waveforms of the proposed HERICHERIC inverter in theinpositive and inverter. shows the simulated waveforms of the proposed inverter the positive negative cycle. In the positive cycle, the gate signals of S1, S4, and S8 are given in Figure and negative cycle. In the positive cycle, the gate of S1, S4, and S8 are given in Figure 15a. 15a. The The voltages S1 S4 and S4 drop to when zero when are turned onSince at t1.the Since the freewheeling voltages of S1ofand drop to zero S1 andS1S4and areS4 turned on at t1. freewheeling current current is blocked by currents D9, the currents andat S4zero keep at zero S8 on. is turned on.isAt t2, S8on. is is blocked by D9, the of S1 andofS4S1keep until S8 isuntil turned At t2, S8 turned turned There path is a current path that by is composed ac and side,S8. S4,The D10, and S8. current There ison. a current that is composed S1, ac side,by S4,S1, D10, current goesThe through S1 goes through and S4then. start As to increase then. As transition the switching-on transition is turn-on finished,isarealized ZVHC and S4 start toS1 increase the switching-on is finished, a ZVHC turn-on is realized the IGBT. S8 isatturned first at goes t3. The currentS1goes S1to and S4 again, drops for the IGBT. S8 isfor turned off first t3. Theoffcurrent through andthrough S4 drops zero to zerothe again, whileofthe of S1atand keepS1atand zeroS4since S1 and S4 are turned while voltages S1 voltages and S4 keep zeroS4since are still turned on still at this time.on Atatt4,this S1 time. Atare t4, turned S1 and off. S4 are turned off. of The of S1to and S4 startAs to increase. As the switching-off and S4 The voltages S1voltages and S4 start increase. the switching-off transition is transition finished, a ZCZV turn-offfor is the realized IGBT.inAs shown in the Figure 15b,turn-on the ZVHC finished, aisZCZV turn-off is realized IGBT.for Asthe shown Figure 15b, ZVHC and turn-on andturn-off the ZCZV are alsofor achieved IGBT S2 and withofthe S7 in and in the the ZCZV are turn-off also achieved IGBT S2for and S3 with theS3help S7help and of D10 theD10 negative negative As athe result, the dynamic switching the high-frequency switch IGBT S1~S4 cycle. Ascycle. a result, dynamic switching losseslosses of theofhigh-frequency switch IGBT S1~S4 cancan be be efficiently reduced. With smaller thermalstress stresscoming comingfrom fromswitching switchingloss, loss,IGBTs IGBTs in the inverter efficiently reduced. With smaller thermal can can push push to to operate operate at at the the higher higher switching switching frequency. frequency.

(a)

(b)

Figure 15. results of the improved HERIC inverter (a) The cycle; (b) The negative Figure 15. Simulation Simulation results of the improved HERIC inverter (a)positive The positive cycle; (b) The cycle. negative cycle.

5. Conclusions 5. Conclusions This paper presents a novel series hybrid switching method to achieve IGBT’s dynamic This paper presents a novel series hybrid switching method to achieve IGBT’s dynamic switching switching loss reduction by switching under Zero Voltage Hard Current (ZVHC) turn-on and Zero loss reduction by switching under Zero Voltage Hard Current (ZVHC) turn-on and Zero Current Current Hard Voltage (ZCHV) turn-off conditions. A SiC MOSFET is utilized to generate a dead Hard Voltage (ZCHV) turn-off conditions. A SiC MOSFET is utilized to generate a dead time in time in order to help IGBT avoiding voltage and current crossing during the switching transition periods. Theoretically, the IGBT switching loss is zero, but the stored minority charge will have an impact on the actual loss. 90% turn-on loss reduction and 57% turn-off loss reduction still can be achieved in theexperimental results. In addition, the hybrid switching method can be easily applied

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order to help IGBT avoiding voltage and current crossing during the switching transition periods. Theoretically, the IGBT switching loss is zero, but the stored minority charge will have an impact on the actual loss. 90% turn-on loss reduction and 57% turn-off loss reduction still can be achieved in theexperimental results. In addition, the hybrid switching method can be easily applied to the voltage source converters. The modulation for SiC MOSFET is easy to design because it is only decided by the gate signal of the series IGBT. With the improved modulation strategy, only one SiC MOSFET and a diode can help two high-frequency switches to reduce the dynamic switching loss in the improved HERIC inverter. The cost can be cut down significantly when compared with the parallel hybrid switch. However, there still have considerable switching-off loss that is caused by the current bump with the proposed method. It still needs improvement for the hybrid switching method. To reduce the current bump efficiently, the approach by using the lifetime killer or decreasing the voltage rise ratio (dv/dt) can be further studied. Moreover, although the SiC MOSFET can help IGBT to reduce the stress of high switching loss, the conduction loss of the hybrid switches is increased because of the series SiC MOSFET. To improve the efficiency of the hybrid switching method, more research needs to be done for the further application in the future. Author Contributions: Lan Ma and Alex Q. Huang proposed the hybrid soft switching method for IGBT; Hongbing Xu and Jianxiao Zou built the simulation model; Lan Ma and Alex Q. Huang performed the experiments for the hybrid soft switching method; Lan Ma and Hongbing Xu analyzed the simulation and experimental results; Lan Ma and Kai Li wrote the paper. Conflicts of Interest: The authors declare no conflict of interest.

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