Impacts of Static and Dynamic Local Bending of Thinned Si chip on MOSFET Performance in 3-D Stacked LSI H. Kino1, J. -C. Bea2, M. Murugesan2, K. -W. Lee2, T. Fukushima2, M. Koyanagi2, and T. Tanaka1,3 1 Dept. of Bioengineering and Robotics, Graduate School of Engineering, Tohoku University 2 New Industry Creation Hatchery Center (NICHe), Tohoku University 3 Dept. of Biomedical Engineering, Graduate School of Biomedical Engineering, Tohoku University 6-6-01 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan Phone: +81-22-795-6909 E-mail:
[email protected] Abstract A three-dimensional (3-D) LSI has many lots of throughSi vias (TSVs) and metal microbumps to achieve electrical connections between stacked thinned LSI chips, and also has organic adhesives to obtain completely bonded thinned LSI chips. However, these elements, especially microbumps and organic adhesives, induce static and dynamic local bending of the thinned LSI chips. In this study, for the first time, we investigated impacts of the static and dynamic local bending on MOSFET characteristics using a novel test structure. Introduction 3-D LSI consisting of vertically stacked several thin Si chips with many TSVs and metal microbumps have attracted much attention as a promising evolution system that enhances LSI performance [1]. 3D-LSI has great advantages, such as parallel processing, high packaging density, low power consumption, short global wiring length, and high-speed operation [2]-[6]. However, it has some problems to be solved for practical applications. In particular, great interest in electrical is mechanical reliability issues are increasing among 3-D LSI researchers. Conventional 3-D LSIs consist of five key technologies, as shown in Fig. 1 [7]-[11]. TSVs and metal microbumps electrically connect between upper and lower Si chips. The thinning of the Si chips leads to a thinner LSI package and a shorter TSV. A shorter TSV makes it possible to decrease parasitic capacitance, electric resistance, and process cost. Chip alignment technology is required to have alignment accuracy less than 1 μm to realize high-density TSV interconnects. It is also necessary to fill an adhesive material called underfill among layers to increase mechanical strength. The organic adhesive surrounds metal microbumps between upper and lower thinned Si chips.
Figure 1. Cross-sectional schematic structure of 3-D LSI.
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The coefficient of thermal expansion (CTE) of the organic adhesive is larger than that of metal microbumps. This mismatch induced the local bending of the thinned LSI chip, because the organic adhesive shrank rather than metal microbumps after 3-D integration process, as shown in Fig. 2. In addition, flexural rigidity of LSI chips decreased due to chip thinning. Therefore, the 3-D integration process generated larger static stress/strain in the chips and the resultant static local bending of the chips in 3-D LSI.
Figure 2. Cross-sectional image of (a) ideal and (b) actual 3-D LSI after 3-D integration process. On the other hand, high speed circuit operation generated a large amount of heat in the thinned LSI chips. This heat expanded the organic adhesive rather than metal microbumps, causing dynamic stress/strain in the LSI chips, as shown in Fig. 3.
Figure 3. Cross-sectional image of actual 3-D LSI in high speed circuit operation.
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These static and dynamic stress/strains induced larger changes of carrier mobility in the MOSFETs. Therefore, it is strongly required to evaluate the impact of larger stress/strain on MOSFET characteristics accurately. As 3-D LSI has several issues, that affect the MOSFET characteristics, such as metal diffusion from TSVs and metal microbumps, disappearance of intrinsic gettering (IG) layers, and mechanical stress/strain caused by TSVs, it is very difficult to evaluate effects elicited only by local bending of the thinned chip on MOSFET characteristics using actual 3-D LSIs [12][16]. In this study, we have proposed a new test structure to evaluate effects of static and dynamic local bending using actual LSI chips, and discussed those local bending effects on the MOSFET characteristics New method of evaluating local bending stress effect Figure 4 illustrates cross sections of the proposed test structure to evaluate the static and dynamic local bending stress effects. The new test structure is composed of Si (dummy) microbumps, organic adhesive, and a thinned LSI chip stacked on Si substrate. The Si microbumps were used instead of metal microbumps, and larger CTE mismatch between Si and organic adhesive still existed. After curing, the organic adhesive applies down forces to the thinned LSI chip by volume shrinkage of the organic adhesive similarly to actual 3-D LSI. And after heating, organic adhesive applies upper force to the thinned LSI chip by volume expansion of the organic adhesive similarly to actual 3-D LSI in high speed circuit operation.
As another advantage of the Si microbumps, metal diffusion into a Si substrate does not occur using the test structure. If the metal diffuses into the Si substrate, the MOSFET characteristics degrade and fluctuate, and it will not be possible to distinguish the effects of the CTE mismatch from those of the metal diffusion. In this test structure, it is easy to control both the position and strength of the local bending stress and to evaluate effects due only to the local bending stress. It is also easy to fabricate the test structure for a short time at a low cost. This test structure was fabricated using the following processes, as shown in Fig. 5. First, Si microbumps were formed on the Si substrate by conventional ICP-RIE process with SF6 and C4F8 as the source gases. The bump size and height were 20 um by 20 um and 20 um, respectively. There were several bump pitches. Then, the 30-um-thick thinned Si chip was bonded on the Si substrate. Epoxy was used as the organic adhesive in this study. After the epoxy was additionally coated around the bonded chip, the bonded chip and Si substrate was temporarily exposed in vacuum atmosphere and opened to the air to completely fill gaps between the thinned chip and the Si substrates by the epoxy. Finally, the epoxy was cured at 150 degree C for 1 hour.
Figure 5. Fabrication process of the test structure. Figure 6 shows a birds-eye SEM image of Si microbumps with 50-μm pitch. Si microbumps has fabricated as designed. And Fig. 7 shows a cross-sectional SEM image of test structure after curing. It is clearly observed that no voids exist in the organic adhesive.
Figure 4. Test structure using Si microbumps and organic adhesive. Figure 6. Birds-eye SEM image of fabricated Si microbumps.
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Figure 7. Cross-sectional SEM image of the fabricated test structure. Effect of static local bending stress We measured the surface profile of thinned Si chips stacked with Si microbumps using white light interferometer. Here, Si chip thickness is 35 μm and Si bump pitch is 500 μm. We can observe approximately 1 μm deflection in this case. The static local bending is clearly observed using our test structure.
Figure 9. Stress distribution image using μRS with (a) 300 μm and (b) 100 μm pitch Si microbumps.
Figure 8. Surface profile of thinned Si chips stacked with Si microbumps measured by white light interferometer.
Then, we measured the MOSFET characteristics in the 30um-thick actual LSI chip stacked on the Si substrate. Figure 10 shows the layout of the Si microbumps and MOSFETs in the thinned Si chip. An nMOSFETs were placed at points A and B with a gate length, and a gate width 0.5 μm, and 10 μm on at point A, 5 μm, and 10 μm at point B, respectively. The drain current flowed along the Y-axis direction.
Next, we measured the static local bending using the test structure with Micro-Raman spectroscopy (uRS). The test structure has showed a stress distribution as shown in Fig. 9. Specifically, there were tensile stresses of more than 1 GPa directly on Si microbumps and compressive stresses of more than 150 MPa in the middle of four adjacent Si microbumps applied to the thinned bulk Si chip, as shown in Fig. 9 (a). This result shows that large static tensile and compressive stresses existed directly on Si microbumps and in the middle of four adjacent Si microbumps owing to adhesive shrinkage after the 3-D integration process. Thus we need to evaluate the effects of the stress distribution on MOSFET characteristics and we measured the MOSFETs fabricated on the locally bent thinned LSI chips using a semiconductor parameter analyzer. Figure 10. Layout of Si microbumps and MOSFETs in thinned LSI chip.
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Figure 11 shows the Id-Vd characteristics of the nMOSFET at point A in the thinned LSI chip without and with the 50-μm-pitch Si microbumps. With the local bending stress, the drain current increased by 7.2% at the Vd and Vg of 1.2 V a after the static local bending stress impressing, because point A is impressed tensile stress, as shown in Fig. 9.
electron mobility increases with tensile strains and decreases with compressive stresses in the Si (100) plane [17][18]. These results agree well with theoretical predictions.
Figure 13. Electron mobility characteristics of nMOSFET in thinned LSI chip without and with Si microbumps at point A.
Figure 11. Id-Vd characteristics of nMOSFET in thinned LSI chip without and with Si microbumps at point A. Figure 12 shows the Id-Vd characteristics of the nMOSFET at point B in the thinned LSI chip without and with Si microbumps. We observed a decrease in drain current by 3.0% at the Vd and Vg of 1.2 V after the static local bending stress impressing, because point B is impressed compressive stress, as shown in Fig. 9.
Figure 12. Id-Vd characteristics of nMOSFET in thinned LSI chip without and with Si microbumps at point B. Figure 13 shows the result of electron mobility characteristics of nMOSFET at point A without and with static local bending stress. The electron mobility increased by 13 % at an effective electrical field of 0.5 MV/cm in the MOSFET placed on the Si microbump. It is well known that
Effect of dynamic local bending stress We should consider the effect of dynamic local bending stress due to the heat generated by high speed circuit operation. First, we measured the MOSFET characteristics at temperatures of 23 and 50 degrees C. Figure 14 shows Id-Vd characteristics of pMOSFET in thinned LSI chip at temperatures of 23 and 50 degree C without Si microbumps. We observed 10 % decreases of ON currents.
Figure 14. Id-Vd characteristics of pMOSFET in thinned LSI chip at temperatures of 23 and 50 degree C without Si microbumps. Next, we measured the MOSFET characteristics at temperatures of 23 and 50 degrees C with Si microbumps similarly to actual 3-D LSI in high speed circuit operation. Figure 15 shows Id-Vd characteristics of pMOSFET in thinned LSI chip at temperatures of 23 and 50 degree C with Si microbumps. The pMOSFET is placed at the point impressed
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compressive stress. We observed approximately 2% decreases in MOSFET ON current from 23 to 50 degree C with the Si microbumps. This result was different from previous result. The previous result agreed well with a SPICE simulation result. The SPICE simulation was shown in Fig. 16. This difference was induced by expansion of the organic adhesive, indicating that dynamic local bending caused complicated effects to the 3-D stacked LSI.
Conclusions We measured the effect of CTE mismatch between the organic adhesive and Si microbumps on MOSFET characteristics in thinned LSI chip. We demonstrated that the static local bending changed the carrier mobility accordingly with the MOSFET position between the Si microbump and MOSFET. We also demonstrated that the dynamic local bending changed the ON current of MOSFET. These results show that it is necessary to carefully design the layout of microbumps and MOSFETs in order to realize higher performance 3-D LSIs with suppressing both static and dynamic circuit performance degradation and fluctuation. Acknowledgments This work was entrusted by NEDO, “Development of Functionally Innovative 3D-integrated Circuit (Dream Chip) Technology”, and supported by ASET, Association of SuperAdvanced Electronics Technologies. The work is also supported by VLSI Design and Education Center (VDEC), the University of Tokyo, in collaboration with Cadence Design Systems. The test structure in this work was fabricated at the Micro/Nano-Machining Research and Education Center at Tohoku University.
Figure 15. Id-Vd characteristics of pMOSFET in thinned LSI chip at temperatures of 23 and 50 degree C with Si microbumps.
Figure 16. SPICE-simulation results of Id-Vd characteristics of pMOSFET at temperatures of 23 and 50 degree C without Si microbumps. Thus, it is necessary to reduce the static and dynamic local bending stress and suppress these negative effects. Both finepitch microbumps and low-CTE adhesive materials can possibly be used to inhibit these negative effects caused by the local bending stress [19]-[21]. This is because a short bump pitch reduces the bending moment and low-CTE adhesive materials reduce the CTE mismatch between metal microbumps and adhesive materials.
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