Implementation and Evaluation of Error Control ... - IEEE Xplore

2014 IEEE International Conference on Industrial Technology (ICIT), Feb. 26 - Mar. 1, 2014, Busan, Korea

Implementation and Evaluation of Error Control Schemes in Industrial Wireless Sensor Networks † , Mikael Gidlund† and Mats Bj¨ ˚ Yonas Hagos Yitbarek‡ , Kan Yu∗ , Johan Akerberg orkman∗ ∗ M¨alardalen

University, Sweden University of Technology, Sweden † ABB AB, Corporate Research, Sweden

‡ Chalmers

Abstract—Industrial Wireless Sensor Networks (IWSNs) have been increasingly adopted in process automation due to a number of advantages such as cost reduction and enhanced flexibility. Nevertheless, transmission over wireless channels in industrial environments is prone to interference, resulting in frequent erroneous packet deliveries. Existing IWSN standards based on the IEEE 802.15.4 specification only prescribe Automatic Repeat Request (ARQ) for packet retransmission, without providing any means for error recovery, which leads to unexpected transmission delay. Forward Error Correction (FEC) code as an alternative approach is able to effectively improve reliability and reduce the number of retransmissions. However, FEC computation requires extra memory and processing time. In this paper, we discuss the timing constraints of employing FEC codes for IWSNs according to the IWSN standards. Then we benchmark a number of different FEC codes in a typical wireless sensor node in terms of memory consumption and processing time. Our results show that LDPC and Turbo code, as the state of the art FEC codes, fail to fulfill the requirement from the IWSN standards while other FEC candidates, such as RS code, are proven to be suitable for the practical implementation in IWSNs.

I. I NTRODUCTION Cost reduction and increased flexibility are the principal reasons for introducing Wireless Sensor Networks (WSNs) into industrial control applications. Industrial Wireless Sensor Network (IWSN) technologies serve a number of purposes, such as monitoring and actuating. Nevertheless, numerous research challenges in adopting wireless networking for industrial purposes continue to persist, one of which is to satisfy the strict real-time and reliability requirements. Compared with conventional WSNs, a great number of applications of IWSNs strictly require deterministic and real-time performance for both economic and safety reasons, since transmission failures or deadline misses may terminate industrial applications and eventually lead to economic loss and safety problems [1]. This is readily available by using wired solutions, but for wireless solutions, industrial facilities abound with metallic surfaces, non-line-of-sight (NLOS) communication, electromagnetic fields and moving objects. All these factors pose a significant threat to reliability and real-time performance by causing frequent packet losses [2]. Nowadays, there already exist several IWSN standards specifically designed to meet the enforced requirements on reliable and real-time transmission, such as WirelessHart [3], ISA100.11a [4] and WIA-PA [5]. Most of these standards are based on the standard IEEE 802.15.4 [6] to provide low

rate and low cost wireless communication. Nevertheless, all these standards fail to provide any advanced error-control mechanism to improve reliability. Instead, only Automatic Repeat Request (ARQ) mechanism is applied, combining with error detection by Cyclic Redundancy Check (CRC). However, an inherent drawback of ARQ is the increased latency of packet delivery, due to a number of retransmissions. The previous empirical results [7] exhibit the serious consequences, such as network congestions, caused by excessive unexpected retransmissions. An alternative approach to improve reliability is the concept of Forward Error Correction (FEC). By applying channel coding on transmitted data, a certain number of corrupted bits in a packet can be corrected. Consequently, data retransmissions are avoided and the real-time performance can be improved. Unfortunately, the FEC approach is omitted in all IEEE 802.15.4-based WSN standards. The major reason for excluding FEC from these standards is the concern of additional power consumption caused by additional FEC calculation and redundant data. However, previous research works have found that in lossy wireless channels FEC may be more energy efficient than ARQ mechanism by reducing the number of retransmissions [8] [9]. Currently significant research efforts have been undertaken on investigating the performance of FEC coding for WSNs, but most of them mainly focus on investigating the energy consumption by applying FEC, setting relationships between consumption and transmission parameters or decreasing Bit Error Rate (BER) with more advanced FEC algorithms. In order to employ FEC in existing wireless sensor nodes, there are more practical aspects that need to be taken into account. The first issue is that directly applying FEC codes on the physical (PHY) layer is impossible if we have no access to the “silicon”. Therefore, software implementation of FEC codes on the MAC layer or above is a more practicable solution. The second is the resource constraint from wireless sensor nodes. Since IWSN nodes are embedded devices with limited memory resources, the FEC code implemented in these nodes should have a small footprint on system’s memory. The last concern is that there are strict timing requirements of data transmissions according to the IWSN standards. Since FEC computation takes time, if the FEC processing time exceeds the maximum allowed time, the IWSN standards are violated. Therefore, in this paper, we first discuss the

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timing requirements from the existing IWSN standards. In order to determine the appropriate FEC codes for IWSNs, we benchmark a number of different FEC codes in terms of the memory footprint and processing time. The selection of our evaluation covers from the extremely simple FEC code, for instance Repetition code, to the the state of the art FEC code, such as Turbo code. All codes are software implemented in a typical wireless sensor node. Our evaluation exhibits that Turbo code and LDPC code, as the advanced FEC codes, are overwhelming to the wireless sensor nodes, although they have outstanding error correction performance. Some other FEC codes are found to be suitable for implementation in a typical IWSN node, such as RS code. To the best of our knowledge, this paper is the first research work to comprehensively benchmark well-known FEC codes in terms of memory and time consumption to explore the feasibility of applying the FEC method in a practical wireless sensor node, along with the IWSN standard requirements. The remainder of the paper is organized as follows. Section II reviews the previous works on applying FEC in WSNs. In Section III briefly describes the basic concepts of the existing IWSN standards and FEC, as well as the discussion of the timing requirements. Section IV describes the experimental setup, followed by the simulation results. The discussion and analysis of the results is given in Section V. Section VI concludes the article. II. R ELATED W ORKS A great number of researches have been done in the area within the sensor network society. Among them, most of the research efforts focus on exploring the energy efficiency of applying FEC coding schemes or FEC related methods for WSNs. For instance, the authors in [10] identified that the use of Error Control Coding (ECC) is able to decrease the transmission power, although the complex decoder requires processing energy. By exploring this trade off the authors declared that applying ECC is more power efficient and the analog decoder implementation outperforms the digital counterpart. In [11], the authors presented an optimum FEC scheme with the maximal energy efficiency for a target communication distance and packet size. The energy efficiency of FEC and ARQ is also compared in this research work. Their results exhibit that the FEC method is less energy efficient than ARQ for a short communication distance. In [8], the impact of error control mechanisms on packet size optimization and energy efficiency is also examined. The authors hold a different opinion that FEC scheme is more energy efficient than retransmission mechanism, although the FEC scheme requires additional energy for encoding/decoding process. Researches in [9] also evaluated FEC and infinite ARQ mechanism in terms of energy efficiency and the authors also proved that the FEC mechanism performs better than the infinite ARQ scheme. The authors in [12] focus on comparing the energy efficiency between different FEC codes, and they found that LDPC code is more energy efficient compare to BCH codes and convolutional codes.

Except energy consumption, BER is another research topic when applying FEC for WSNs. The research work in [13] compared the performance of three different error control codes, namely BCH, RS and convolutional codes, with implementation on FPGA and ASIC design in terms of BER. They announced that binary-BCH codes with ASIC implementation are best suitable for wireless sensor networks. The authors in [14] analyzed the classical FEC and carried out an experiment. Their results show that FEC codes can effectively decrease BER and empower WSNs by increasing the coverage area of a node maintaining the same SNR. It is notable that most of existing research works are based on the assumption that the PHY layer can be easily accessed to employ FEC codes. However, this assumption is not the truth due to restrictions imposed by hardware limitations. Furthermore, most of previous works evaluate their results by simulations. Therefore, this paper focuses on an alternative aspect. As we emphasized above that both WSNs and IWSNs consists of resource constrained embedded devices with limited computation ability and memory size, complicated FEC codes may result in the failure of fulfilling the standard requirement or incompatibility problems with the existing protocols for IWSNs. Although the comparison of several FEC codes for IWSNs has been done in [11], a more comprehensive evaluation of different types of FEC codes is necessary for the appropriate selection of FEC codes for IWSNs. Different from previous works, our paper is based on the software implementation on the MAC layer. III. P RELIMINARIES In this section, we give basic details of the existing standards for IWSNs and point out the constraints from these standards when applying FEC codes, followed by the introduction of the principle of FEC coding. A. IWSN Standards Nowadays, there are several standards used or going to be used in IWSNs, such as Zigbee [15], WirelessHart [3], ISA100.11a [4] and WIA-PA [5]. All these standards are based on the standard IEEE 802.15.4 [6]. In order to improve reliability, the IEEE 802.15.4 standard provides a stop-andwait ARQ mechanism on the MAC layer. According to IEEE 802.15.4, the sender will retransmit the previous packet if no acknowledgment is received within macAckWaitDuration symbol periods, which is in the order of millisecond. The macAckWaitDuration can be calculated as: macAckWaitDuration

= + +

aUnitBackoffPeriod + aTurnaroundTime phySHRDuration 6 × phySymbolsPerOctet (1)

where aUnitBackoffPeriod is the number of symbols forming the basic time period, aTurnaroundTime is RX-to-TX or TXto-RX maximum turnaround time, phySHRDuration is the duration of the synchronization header for the current PHY

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TABLE I C ODE RATES AND E RROR CORRECTING CAPABILITY OF FEC CODES

Fig. 1.

A timeslot of WirelessHART

and phySymbolsPerOctet is the number of symbols per octet for the current PHY. Therefore, the receiver should reply the corresponding acknowledgment as soon as possible once receiving the packet to meet the ACK timing requirement from the standard. Based on the standard, when the FEC method is utilized in IWSNs, the receiver shall not spend extremely long time on processing the FEC code; otherwise, the transmission attempts always fail and the standard is violated. Besides the acknowledgment time requirement, there is another timing constraint from the standards. WirelessHart, ISA100.11a and WIA-PA, as three major standards for industrial automation, apply TDMA transmission on the MAC layer to avoid unpredictable collision. It means that the whole transmission procedure should be accomplished within one time slot. Taking WirelessHart as an example, Figure 1 shows one timeslot and provides an overview of transaction timing. The duration of one timeslot is defined as 10 ms. Therefore, when applying FEC approach on top of the standard, the total timing of sending, receiving, FEC processing and guard-band times should be less than one timeslot duration. Otherwise, the task for the adjacent time slot might be affected. B. Forward Error Correction Channel coding deals with error control coding techniques employed in transmitter and receiver for reliable communication systems. It is a process of adding redundancy parity bits to information bits for error protection. Different from the ARQ mechanism, FEC corrects the detected error without feedback transmission (only through forward transmission). Generally, FEC is classified in to two basic types, namely, block codes and convolutional codes. A block code denoted by (n, k) code, an information symbols length k are coded to obtain a block of n codeword symbols depending only on the k input symbols by adding n-k redundancy check symbols. While a convolutional code, denoted as (n, k, m), contains m memory registers maps k-bits information symbols in to n-bits code block symbols which depends on m previous symbols. For both block and convolutional codes, the code rate, R = k/n(R < 1), indicates the transmission efficiency of the FEC. Higher code rate means lighter transmission overhead and less extra transmission power. IV. E VALUATION C ANDIDATE S ELECTION In order for a comprehensive evaluation of different types of FEC codes for IWSNs, the candidates are selected from both block and convolutional code categories.

FEC Code Repetition (3, 1) Cyclic (15, 7) Hamming (7, 4) BCH (31, 21) RS (15, 11) LDPC (12, 4) TURBO (24, 8)

Code Rate 0.3333 0.4667 0.5714 0.6774 0.7333 0.3333 0.3333

Error correcting capability 1/3 = 0.3333 2/15 = 0.1333 1/7 = 0.1429 2/31 = 0.0645 2/15 = 0.1333 2/12 = 0.1667 3/24 = 0.1250

Repetition (3, 1) code is the first FEC code to be considered in our evaluation. The reason for choosing repetition code as our candidate is the extremely simple implementation for both encoding and decoding. Although the repetition code is inefficient due to its low code rate, it has still been used in a number of communication systems because of its simplicity . Cyclic (15, 7) code based on shift register like implementation is the second candidate from the block coding scheme we will evaluate, since it is a commonly used FEC code with efficient error detection and correction ability. It is a double error correcting code with powerful decoding algorithm based on look up table for faster processing. The Hamming code is one of the most well known FEC codes which has been already widely used in telecommunication systems. As the earliest codes capable of correcting errors, Hamming codes also can be easily implemented for both encoding and decoding. Thus, we choose Hamming (7, 4) code as another candidate. Binary Bose-Choudhary-Hocquenhem (BCH) is the following selected FEC code type. BCH code is an important subclass of cyclic codes. It possess a rich algebraic structure for efficient encoding/decoding algorithms and reduce computational complexity. BCH (31, 21) code is chosen for our evaluation. Reed-Solomon (RS) (15, 11) code is also chosen as one of our evaluation candidates. The RS code is one type of nonbinary BCH codes, and is remarkable due to its high efficiency. It has burst error correcting capabilities, which is extremely suitable for wireless channels. Low-density parity-check (LDPC) codes and Turbo codes are last two candidates for our evaluation. Both of them are well-known for their remarkable performance extremely close to the Shannon capacity formula. Therefore, LDPC codes are in the focus of many standardization activities, such as IEEE 802.11n and IEEE 802.16e, and Turbo codes have been already applied in 3G mobile communication. Therefore, our final selection of evaluation candidates are Repetition(3, 1), Cyclic(15, 7), Hamming(7,4), BCH(31, 21), RS(15,11), LDPC(12, 4) and Turbo(24, 8). The code rates and error correction capabilities of all candidates are summarized in Table I. Higher code rate indicates less redundant data to be added in encoded messages, which leads to better coding efficiency. According to all IEEE 802.15.4-based IWSN standards, the maximum allowed packet length is quite short, only 128 bytes. Therefore, the parameters of all candidates,

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Fig. 2.

Theoretical BER Performance

namely the length of original data and codeword, are chosen to be relatively small. Otherwise, short packets cannot fit for the FEC code length. The theoretical BER performance of all FEC candidates are shown in Figure 2. It is clear that LDPC and Turbo codes significantly outperform other candidates. An extremely low BER can be achieved even when the signal-to-noise ratio (SNR) is very low. Besides these two advanced FEC codes, the RS code also achieve decent BER performance, the third lowest BER curve of all. Repetition code theoretically performs worst, but the complexity of the repetition code is also the lowest. The bandwidth versus power efficiency of all candidates are shown in Figure 3. Power efficiency represents the quality of the channel, whereas bandwidth efficiency refers to the information rate that can be transmitted over a given bandwidth. The channel capacity bounds the information rate that can be achieved over a communication channel. Therefore, theoretically if a FEC code in the figure is more closed to its channel capacity, it is considered to outperformed others. Although from figures above, LDPC and Turbo codes have the best performance, whether they can fit the wireless sensor node according to the standard requirement is questionable. V. P ERFORMANCE COMPARISON AND EVALUATION The purpose of our evaluation is to measure the processing time and memory consumption of FEC codes in a practical IWSN node in order to identify an appropriate algorithm for IWSNs. In this section, we firstly introduce the experimental setup, followed by the evaluation results. A. Experimental Setup In our evaluation, we use a STM32W development kit, shown in Figure 4 from STMicroelectronics as the evaluation node. The microcontroller is a complete System-on-Chip that integrates 2.4GHz, IEEE 802.15.4-compliant transceiver, 32bit ARM Cortex-M3 microprocessor operating at 24MHz with 128-Kbytes flash memory, 8-Kbytes RAM memory, and

Fig. 3.

Bandwidth Vs. Power Efficiency of All Candidates

Fig. 4.

STM32W Development Board

peripheral of use to designers of 802.15.4 based systems. It is a typical wireless sensor node which can be often found as an IWSN device within the automation domain. The IAR Embedded Workbench 6.4 is used as the development environment. The compiler from the IAR Embedded Workbench 6.4 is able to support four optimization levels in terms of size or speed. In order to investigate both the fastest processing time and the least memory footprint, we show the results using both the highest speed and size optimization. All the implementations of FEC codes are based on software implementation using C language. The time complexity of each FEC implementation is summarized in Table II, where M is the block number in one packet, n is the codeword length, k is the original data length, dmin is the minimum Hamming distance of the FEC code, Nldpc is the iteration number of LDPC, wc is the number of 1’s in each row of the parity-check matrix and wr is the columns, Nturbe is the iteration number of Turbe code and Ntrellis is the number of trellis states. All implementations of FEC codes are not optimal with respect to performance. Although further optimization may reduce the footprint and the execution time, tremendous improvement of performance cannot be expected. In IWSNs the maximum payload of IEEE 802.15.4 standard on the MAC layer is defined as 128 bytes. Therefore, the maximum data length is considered in our evaluation in order to assess at the worst case scenario: maximum processing time and memory consumption. Since all packets are FEC encoded,

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TABLE II T HE T IME C OMPLEXITY OF A LL C ANDIDATE I MPLEMENTATIONS

TABLE III E XECUTION TIME OF FEC CODES USING S PEED O PTIMIZATION

FEC Code Cyclic Hamming Repetition BCH RS LDPC TURBO

FEC Code

Encoding time (ms)

Decoding time with no error (ms)

Cyclic (15, 7) Hamming (7, 4) Repetition (3, 1) BCH (31, 21) RS (15, 11) LDPC (12, 4) TURBO (24, 8)

1.6333 2.4500 0.5133 2.4424 0.5953 2.3858 1.9308

3.0067 2.4908 1.5167 1.7044 0.9582 25.4625 703.2

Fig. 5.

Encoding Complexity O(M k) O(M nk) O(M n) O(M k(n − k)) O(M k(n − k)) O(M nk) O(M n)

Decoding Complexity O(M n2 ) O(M nk) O(M n) O(M ndmin ) O(M n(n − k)) O(M Nldpc nwc wr ) O(M Nturbo kNtrellis )

Memory Footprint of FEC codes using Speed Optimization

the maximum packet size of the original message depends on the code rate of the specific FEC code which is calculated as L = 128 · R. B. Evaluation Results The memory usage of each FEC code is shown in Figure 5 and presented into three memory regions: Read-Only (RO) code memory, Read-Only (RO) data memory and Read-Write (RW) data memory. The RO code memory represents the size of executable program, RO data memory represents the size of initialized constant values and RW data memory represents the size of RAM the algorithm uses. The measurement of execution time is based on CPU cycles, shown in Table III. The results of FEC processing time are presented in three different sections: encoding time, decoding time without error and decoding time with maximum correctable error. The maximum correctable error means that a packet encounters the maximum number of errors that the corresponding FEC algorithm can correct them. Since the execution time for decoding messages with and without errors are significantly different, we present the results separately. VI. A NALYSIS AND D ISCUSSION In terms of the memory footprint, among all evaluated FEC codes, Turbo code obviously consumes the most read-only code memory, more than 7K bytes, due to the complicated algorithm. Another advanced FEC code, LDPC, performs better in the read-only code memory, but it requires the most

Decoding time with max errors (ms) 35.6833 3.1383 1.5167 4.4854 2.3454 37.1817 702.1

read-write data memory, nearly 7K bytes. These two FEC codes use 60% and 90% of the total RAM size, which is huge memory consumption for a resource constrained device. When referring to the execution timing, these two sophisticated FEC codes perform even worse. Previous Table II has already shown that both of them have much high complexity than other candidates, and our evaluation results further confirm this fact. The decoding time of Turbo (24, 8) algorithm in the worse case is about 0.7 seconds which is totally unacceptable for IWSNs that incorporates the standard timing requirement. The execution time of LDPC (12, 4) code is faster than Turbo code, but it is still far beyond the standard timing boundary from the standards. Although according to Figure 2 and 3 Turbo and LDPC codes theoretically have extremely outstanding ability to correct errors even in very low SNR and can achieve excellent bandwidth efficiency, from the practical point of view, these two codes can be hardly employed in IWSNs due to the massive resouce consumption and high comlexity. Moreover, in order to approach Shannon limit, both Turbo and LDPC codes should use considerably much longer block length for encoding, but the maximum allowed packet length from the standards makes it even impossible. Except Turbo and LDPC codes, the classic cyclic (15, 7) code also fails to satisfy the requirements from the IWSN standards. Its decoding time in the worst case still severely exceeds the both timing requirements of the standards, namely acknowledgment and TDMA. The cyclic code requires more than 70% of the total RAM memory size, so it is also impractical to be applied in the memory constrained embedded devices. Compared with the cyclic code, the BCH code performs much better in both memory footprint and execution time. However, the decoding time of BCH code in the worse case is about 4.5 ms. Since the duration of one timeslot from the standard WirelessHART is 10ms, BCH decoding almost uses the half of one timeslot. Thus in order to use BCH code for IWSNs, a further speed optimization is definitely required. Otherwise accomplishing transmission procedure within one timeslot is quite risky. The repetition (3, 1) and hamming (7, 4) codes have the advantage of simple implementation, so they consume the least read-only code memory of all other FEC codes. However, the memory footprint of read-write data memory from these two FEC codes still exceed 50% of the overall RAM memory. Especially for the repetition code,

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the processing time is extremely small due to the low time complexity as shown before. However, due to the different error correction behavior, the repitition code always has the same decoding time, even if there is no error in the packet. Furthermore, the code rate of the repetition code is rather low, which leads to very inefficiency data transmissions. Among all FEC candidates, RS (15, 11) code performs best in terms of memory consumption and processing time, which can be chosen as the most appropriate FEC code to be applied in IWSNs. It barely requires 1.2K bytes out of 8K bytes of RAM size, and consumes the least total memory, compared with all other candidates. Both encoding and decoding time of the RS code outperforms all other candidates. The decoding time in the worst case is absolutely acceptable for the TDMA timing requirement, and it may be a little beyond the acknowledgment timing boundary. However, this worst case only happens when 13.3% of a message with the maximum allowed length is corrupted, which rarely occurs in practical applications. RS (15, 11) has also the highest code rate and multi-burst error correcting capability. Eight consecutive bit errors can be corrected by the RS (15, 11) code. The transmission of data over a noisy industrial wireless channel suffers from different types of interferences, so burst errors often occur. Therefore, the RS (15, 11) has a remarkable performance for IWSNs, compared with other candidates. Hamming and Repetition code can be considered as the second and third best candidates, since they are extremely simple to be implemented and still fast enough to finish both encoding and decoding within one timeslot. Perhaps further optimized implementation of these two codes make them also feasible for the timing requirement of acknowledgment, but it is not what the present paper is intended to cover. VII. C ONCLUSIONS AND F UTURE W ORK In this work, we point out that no error correction mechanism is adopted in any IEEE 02.15.4-based standard to provide reliable and low latency transmissions. As FEC coding is an alternative solution, we discuss the constraints of applying FEC codes in IWSNs based the lack of access to the PHY layer, the limited memory resource and the timing requirements from the existing IWSN standards. In order to explore the feasibility of employing FEC codes in existing wireless sensor nodes along with the IWSN standard requirement, we benchmark different types of FEC codes with the software implementation in terms of memory consumption and processing time. Our evaluation results exhibit that LDPC and Turbo codes, as the state of the art FEC codes, are overwhelming to the wireless sensor nodes and fail to fulfill both memory and timing requirements. Repetition and Hamming codes can be considered due to the simplicity, but still not able to give the most satisfying performance. RS (15, 11) code is the most suitable FEC code among all candidates with decent memory footprint and fast processing time. Future research in this area is to scrutinize more FEC codes and optimize the IWSN FEC code implementations for higher efficiency.

R EFERENCES [1]

[2]

[3] [4] [5] [6]

[7]

[8]

[9] [10]

[11]

[12]

[13]

[14]

[15]

˚ J. Akerberg, M. Gidlund, and M. Bj¨orkman, “Future research challenges in wireless sensor and actuator networks targeting industrial automation,” in IEEE 9th International Conference on Industrial Informatics (INDIN’11), July 2011. ˚ J. Akerberg, M. Gidlund, F. Reichenbach, and M. Bj¨orkman, “Measurements on an industrialwireless hart network supporting profisafe: A case study,” in IEEE Conference on Emerging Technologies and Factory Automation (ETFA’11), Sept. 2011. (2010) Hart 7 specification, http://www.hartcomm.org/. [Online]. Available: http://www.hartcomm.org/ Industrial society of automation, http://www.isa.org/. Shenyang institute of automation, http://www.industrialwireless.cn/. “Ieee standard for information technology- telecommunications and information exchange between systems- local and metropolitan area networks- specific requirements part 15.4: Wireless medium access control (mac) and physical layer (phy) specifications for low-rate wireless personal area networks (wpans),” IEEE Std 802.15.4-2006 (Revision of IEEE Std 802.15.4-2003), pp. 1 –305, 2006. ˚ J. Akerberg, M. Gidlund, J. Neander, T. Lennvall, and M. Bj¨orkman, “Deterministic downlink transmission in wirelesshart networks enabling wireless control applications,” in 36th Annual Conference on IEEE Industrial Electronics Society (IECON’10), Nov. 2010, pp. 2120 –2125. Y. Sankarasubramaniam, I. Akyildiz, and S. McLaughlin, “Energy efficiency based packet size optimization in wireless sensor networks,” in Sensor Network Protocols and Applications, 2003. Proceedings of the First IEEE. 2003 IEEE International Workshop on, 2003, pp. 1 – 8. A. Nandi and S. Kundu, “Energy level performance of error control schemes in wireless sensor networks,” in Devices and Communications (ICDeCom), 2011 International Conference on, Feb. 2011, pp. 1 –5. N. Sadeghi, S. Howard, S. Kasnavi, K. Iniewski, V. Gaudet, and C. Schlegel, “Analysis of error control code use in ultra-low-power wireless sensor networks,” in Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, 2006, pp. 4 pp.– 3561. Z. Tian, D. Yuan, and Q. Liang, “Energy efficiency analysis of error control schemes in wireless sensor networks,” in Wireless Communications and Mobile Computing Conference, 2008. IWCMC ’08. International, 2008, pp. 401–405. M. Sartipi and F. Fekri, “Source and channel coding in wireless sensor networks using ldpc codes,” in Sensor and Ad Hoc Communications and Networks, 2004. IEEE SECON 2004. 2004 First Annual IEEE Communications Society Conference on, Oct. 2004, pp. 309 – 316. G. Balakrishnan, M. Yang, Y. Jiang, and Y. Kim, “Performance analysis of error control codes for wireless sensor networks,” in Information Technology, 2007. ITNG ’07. Fourth International Conference on, April 2007, pp. 876 –879. E. Sanchez, F. Gandino, B. Montrucchio, and M. Rebaudengo, “Increasing effective radiated power in wireless sensor networks with channel coding techniques,” in Electromagnetics in Advanced Applications, 2007. ICEAA 2007. International Conference on, 2007, pp. 403–406. “Ieee standard for a smart transducer interface for sensors and actuators wireless communication protocols and transducer electronic data sheet (teds) formats,” IEEE Std 1451.5-2007, pp. C1 –236, 5 2007.

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