WAVE DIGITAL FILTERS FOR SAMPLE RATE CONVERSION. Compared to FIR filters, an IIR filter meeting the same specification generally yields a lower.
Implementation of a Combined Interpolator and Decimator for an OFDM System Demonstrator Henrik Ohlsson, Håkan Johansson, and Lars Wanhammar Department of Electrical Engineering, Linköping University, SE-581 83 Linköping, Sweden email: {henriko, hakanj, larsw}@isy.liu.se ABSTRACT: This paper presents an implementation of a combined interpolator and decimator used in an OFDM system. The implemented component is used both for the forming of the channel and for reducing the requirements on the A/D and D/A converters. The interpolator and decimator have been implemented using lattice wave digital filters and some novel filter structures for decimation and interpolation by a factor of two have been used to increase the performance and reduce the power consumption.
1. INTRODUCTION This paper presents the design and implementation of high-speed multirate digital filters for use in an experimental OFDM based communication system with a data rate of 20 Mbit/s. OFDM is a modulation method for wide-band communications and it is used in several systems, such as xDSL, DAB and HDTV. The filters are used both in the transceiver and in the receiver for channel forming and for reducing the requirements on the A/D and D/A converters. To reduce the requirements on the A/D- and the D/A-converters in the system the converters operate with a small oversampling factor, in this case a factor of two. This means that there is a need for decimation in the receiver and for interpolation in the transceiver. Such sample rate changes can be implemented efficiently using half-band filters. However, the channel forming requirement is not satisfied by using half-band filters alone. Thus, another filter section is required. The overall specification for the filters are given below. A max < 1 dB ω c T = 0.41π rad ω s T = 0.48π rad
A min > 65 dB
(1)
f s, higher = 51.2 MHz f s, lower = 25.6 MHz The filters are implemented using bit-parallel redundant, carry-save arithmetic. For the interpolation and decimation filters some novel structures have been used to increase the performance and reduce the power consumption [1].
2. WAVE DIGITAL FILTERS FOR SAMPLE RATE CONVERSION Compared to FIR filters, an IIR filter meeting the same specification generally yields a lower arithmetic complexity and fewer delay elements which gives a lower power consumption. However, the recursive structure of IIR filters in combination with the need for quantizations may give problems with stability. One class of robust IIR filters is wave digital filters (WDFs). In this class of filters, the bireciprocal lattice wave digital filters (BLWDFs), also called halfband filters, are suitable structures for the implementation of interpolators and decimators for sample rate changes by a factor of two. The magnitude response for a BLWDFs is always 1/ 2 for ωT = 0.5π . Hence, such filters can only be used when we have ω s T > 0.5π . For the specifications used in this application, where ω s T < 0.5π , the sample rate change can be efficiently implemented with a half-
band filter and the required passband may be formed by a correcting filter cascaded with the half-band filter. The transfer function of a BLWDF is shown in eq. 2. 2
2
(2) H ( z ) = H 1 ( z ) + z –1 H 2 ( z ) A filter with such a transfer function may be implemented using a polyphase structure, as shown in fig. 1. For a polyphase structure the actual filtering can take place at the lower of the sample rates which reduces the power consumption.
x(n)
2
y(m)
H(z)
H0(z)
y(2n)
H1(z)
y(2n+1)
x(n)
Figure 1: Interpolator implementation using a polyphase structure. 2.1. Sample Rate Bound for Wave Digital Filters Since WDFs are recursive filter structures there is a limit on the maximum sample rate possible to obtain since the recursive parts of the filter structure can not be pipelined in order to increase the throughput [6]. The longest computational path in any loop limits the sample rate. T
T
a0 a0
x(n) y(n)
x(n)
y(n)
Figure 2: A first order filter section and the corresponding loop that limits the sample rate. For the filter section shown in fig. 2, implemented with bit-parallel arithmetic, the sample rate bound is given as 1 f s, max = ---------------------------------(3) T mult + 2T add where f s, max is the maximal sample frequency, T mult is the latency for the multiplication and T add is the latency for one addition. The loop that yields the lowest sample rate bound is called the critical loop and the corresponding sample interval is called T min . This bound can in this case be improved by rearrangement of the additions in the loop, reducing T min with one T add , as proposed in [7]. This, however, has not been used here. 2.2. Cascaded Bireciprocal Lattice Wave Digital Filters for Sample Rate Change Bireciprocal LWDFs have a high coefficient sensitivity in the stopband and long coefficient wordlengths are therefore required. This will increase T mult since the logical depth in the multiplications are increased. Thus T min increases as well. The required coefficient word length can be reduced by cascading several filter stages. A drawback with this approach is that when performing decimation and interpolation with a factor of two, only one of the cascaded filter stages may operate at the lower sample rate. An approach to reduce power consumption and arithmetic complexity has been proposed in [1] where the overall transfer function of several cascaded half-band filters are restated in polyphase form. This is shown in eq. 4 where A 1 ( z ) and A 2 ( z ) are the allpass filters used in each of the cascaded polyphase filter stages.
H casc ( z ) = [ A 0 ( z 2 ) + z –1 A 1 ( z 2 ) ] M = H 0 ( z 2 ) + z –1 H 1 ( z 2 ) From eq. 4 the new polyphase allpass filters, H 0 ( z ) and H 1 ( z ) , are derived as
(4)
K0
∑ c2i z –i [ A1 ( z ) ] 2i [ A0 ( z ) ] M – 2i
H 0(z) =
(5)
i=0 K1
H 1(z) =
∑ c2i + 1 z –i [ A1 ( z ) ] 2i + 1 [ A0 ( z ) ] M – 1–2i
(6)
i=0
where M ci = , 0 ≤ i ≤ M i
(7)
(M – 1) M and K 0 = K 1 = ------------------- when M is odd and K 0 = ----- , K 1 = K 0 – 1 when M is even. 2 2 For M = 2 , i.e., when we use two cascaded filter stages for the initial solution, the transfer function is obtained as (8) H 0 ( z ) = A 02 ( z ) + z –1 A 12 ( z ) (9) H 1 ( z ) = 2 A0 ( z ) A1 ( z ) The resulting interpolator structure, which is shown in fig. 3, does not only yield a reduced T min due to the shorter coefficient wordlength required for the allpass filters, the arithmetic complexity for the filter is reduced as well. This is because there are several common subfilters in the new polyphase components that may be shared at the expense of some extra adders and multipliers. Thus, the total arithmetic complexity is reduced compared to a straightforward cascaded solution. x(n)
A0(z)
A0(z)
A1(z)
A1(z)
A1(z)
y(m) T
2
Figure 3: Interpolator structure for M = 2 .
3. IMPLEMENTATION OF WAVE DIGITAL FILTERS USING BIT-PARALLEL CARRY-SAVE ARITHMETIC Carry-save arithmetic, which is a redundant arithmetic, is efficient for the implementation of many DSP applications since time consuming carry propagations may be avoided [4]. One such application is the implementation of WDFs, using bit-parallel arithmetic. Since it is not possible to pipeline recursive loops the latency through each loop needs to be reduced to obtain a high maximal sample rate. This is possible by using carry-save adders instead of carry propagation adders. However, there are some properties for WDFs implemented with carrysave arithmetic that need to be considered. A carry-save adder adds three operands and produces as result a sum-vector and a carryvector. This is done with a combinatorial delay of only one full adder and this delay is independent of the data wordlength of the adder operands. To finalize the addition a vector merging adder is needed at the output of the carry-save adder tree. For the adaptor function this addition is placed outside the recursive loops and may therefore be pipelined in order not to
limit the sample rate. Thus, the recursive parts are represented by two data vectors which makes it difficult to properly identify if an overflow occurs in a loop. Such correction is necessary to perform in order to guarantee overflow stability for wave digital filters. However, in [2] a scheme for detection and corrections of overflow that guarantee the stability in carry-save implementation of WDFs was introduced. The scheme for suppression of oscillations is y = x, 0 ≤ x ≤ 2 (10) y = 1, x > 2 y = – 1, x
