Improve the Dynamic Matching of the Source-Switching Charge Pump for High-Performance Phase-Locked Loops 1
Jinbao Lan*1, Zhiqiang Gao2, Yuxin Wang1, Lintao Liu1, Ruzhang Li1 Sichuan Institute of Solid State Circuits, CETC, Chongqing 400000, China 2 Harbin Institute of Technology, Harbin, 150001, China * Email:
[email protected]
Abstract Conventional source-switching charge pump suffers from slow turning-off speed and intrinsic speed mismatch between its NMOS discharging path and PMOS charging path, which incur obvious dynamic mismatch. To alleviate the above problems, this paper proposes an improved source-switching charge pump, which achieves much better dynamic matching while maintains the same static matching. The proposed charge pump outputs less current noise and lowers the reference spur obviously, which makes it quite preferable for high-performance phase-locked loops.
By now, there are many different circuit realizations of the charge pump, among which, the conventional source-switching charge pump recommended by [1], as shown in Fig.2, is widely adopted because of its simple architecture, low power consumption. The use of wide-swing cascode current mirrors increase its output resistance, resulting in relatively good static matching, without large sacrifice of the usable voltage range of Vctrl. In addition, by placing its switches at the source pins of MN2 and MP2 and by adding the capacitors of CN and CP, it achieves moderate turning-on speed without causing large current glitches. UPin
1. Introduction Nowadays, phase-locked loops (PLL) are widely used for clock & data recovery, modulation & demodulation, clock generation, frequency synthesis and etc. The block diagram of a typical charge-pump PLL for Integer-N frequency multiplication is shown in Fig.1, from which it’s easy to see that the charge pump is one of its key building blocks. For high-performance PLL applications, the matching characteristics of the charge pump are quite important, which affect the skew, the determined jitter and the reference spur of the PLL. The charge pump suffers from static and dynamic mismatches. The static mismatch exists because the voltage (Vctrl) at the output port of the charge pump usually changes in a relatively wide range, whereas the output resistance of the charge pump is usually relatively small. The dynamic mismatch occurs when the turning-on or turning-off speed of the charging and discharging currents are different. On the other hand, the turning-on and turning-off speeds of the charge pump determines the maximum applicable reference frequency of a PLL, so the speed of a charge pump is also an important design consideration. K VCO I CP
Figure 1. A Typical Charge-Pump Phase-Locked Loop
978-1-4244-5798-4/10/$26.00 ©2010 IEEE
UP
DNin
MP1
CP
DN
UP MP2
Iup
NodeP MP3 10μA
10μA
SigN
10μA 10μA
110μA
MNxp
Iout
SigP MN3 MN2
CN
DN
NodeN
MPxn
Idn Added by [2,3]
MN1
Figure 2. The conventional source-switching charge pump and the two MOSFETs (in the dashed box) added by [2, 3] to speed up its turning-off speed However, as pointed out by [2, 3], the turning-off speed of the conventional source-switching charge pump is very slow, because when MN1 and MP1 shut off, there exists no charging or discharging path for the intermediate nodes of the Idn or Iup path. To alleviate this problem, [2, 3] adds two extra MOSFETs, which are surrounded by the dashed box in Fig.2. For the Idn path, at the moment that MN1 shuts off, a short low voltage pulse of SigP is generated to turn on MPxn for a short while, which injects some positive charge to NodeN, resulting in a fast shutting-off of MN3. As a result, the turning-off speed of Idn path is increased. When and after MN1 turns on, SigP keeps high, so the added MPxn has no influence on Idn during this period. Similarly, the added MNxp speeds up the turning-off of the Iup path in the same way. The experiment results of [2, 3] reveal
that by raising the turning-off speed of the conventional source-switching charge pump, its dynamic matching is improved and its output current noise is lowered. Unfortunately, neither [2] nor [3] give any detail on how the pulse signals of SigP and SigN are properly generated. Besides, they both neglect the fact that the NMOS Idn path is intrinsically faster than the PMOS Iup path, which is another important cause for dynamic mismatch. In this paper, based on the ideas of [2, 3] and our observation, we present a detailed circuit design to improve the dynamic matching of the conventional source-switching charge pump. The proposed charge pump is demonstrated in Section 2, and its benefits are described in Section 3. 2. The Proposed Charge Pump The proposed source-switching charge pump of this work is shown in Fig.3. To improve the dynamic matching of the conventional source-switching charge pump of [1], we added all the extra components surrounded by the dashed box. Specifically, the small capacitor CslowN added to NodeN_new is used to slow down the NMOS Idn path. Its effect can be seen from the transient simulation waveforms in Fig.4. When the Idn paths of both the conventional and the proposed charge pumps are turned on at the same time, because of CslowN, the voltage of NodeN_new decreases slower than that of NodeN_old, and resultantly the turning-on speed of Idn_new is slowed down. In this work, CslowN is realized with a small NMOS capacitor and its value should be chosen properly to get the turning-on speeds of the Iup and Idn paths matched. We obtain that value through trial and error. UPin
UP
UP
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td
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NodeP_new UP
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MNx2
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Iout Ixn
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MPx2 DN
CslowN
Figure 4. The transient waveforms of the conventional and proposed charge pumps In the proposed charge pump, except the small capacitor CslowN, all the other added components are used to speed up the turning-off speed of the charge pump. As illustrated by Fig.4, for the Idn path, at the moment that MN1 shuts off, because of the delay element td inserted in the the DNx path, DN changes to 0 before DNx goes up to 1 for a short time of about td, during which MPx1 and MPx2 are simultaneously on. Obviously, a positive current pulse Ixn is now injected to NodeN_new, which speeds up its voltage rise and resultantly speeds up the turning-off of Idn_new. Except for the aforementioned special case occurring at the moment that MN1 is shut off, MPx1 and MPx2 are never simultaneously turned on again, which means the added components do not affect the other normal functions of the source-switching charge pump. Similarly, the turning-off speed of the Iup path of the proposed charge pump is speeded up in the same way by MNx1 and MNx2.
MN2
CN DN
MN1
td
DNx
Figure 3. The charge pump proposed by this work By the way, in all the figures of this paper, the suffix “_old” indicates signals taken from the conventional source-switching charge pump of [1], and the suffix “_new” indicates signals taken from the proposed charge pump of this paper.
3. Performance Comparison Through circuit simulations, the benefits of the proposed charge pump are demonstrated in the aspects of dynamic matching, static matching, output noise current and incurred reference spur. Fig.5 shows the proposed charge pump achieves much better dynamic matching than the conventional source-switching charge pump. On the other hand, Fig.6 shows that the proposed charge pump has the same static matching as the conventional
one because our improvements do not affect the static performance. Additionally, because of speeding up, the total on-time of the proposed charge pump is shorter, which makes it output less noise current, as proven by the simulation results in Fig.7.
the proposed charge pump reduces the reference spurs of the test bench PLL greatly, due to the improvement it achieves in the aspect of dynamic matching.
Figure 7. The noise currents outputted by the conventional and proposed charge pumps 0
Figure 5. The dynamic matching characteristics of the conventional and proposed charge pumps
Power (dBm)
-20
X: 1.01e+009 Y: -50.31
-40
-60
-80 0.98
0.99
1 Frequency (Hz)
1.01
1.02 9
x 10
Figure 8. Reference spurs of the test bench PLL using the conventional charge pump 0 -10
Figure 6. The static matching characteristics of the conventional and proposed charge pumps To investigate how the proposed charge pump affects the reference spur, we set up a test bench Integer-N PLL as Fig.1 shows. Its parameters are: Kvco=250MHz/V, Icp=110A, R1=13.4k, C1=88.8pF, C2=6.87pF, Ndiv=100, Fref=10MHz. The loop bandwidth of the PLL is about 0.5MHz and its open loop phase margin is about 60°. To minimize the influence of charge pump static mismatch, the VCO is specially designed to oscillate at 1GHz when its control voltage is 0.6V. As a result, when the test bench Integer-N PLL locks, its Vctrl=0.6V and Fvco=1GHz, which means under this condition the dynamic mismatch is the main cause for reference spurs. Compare Fig.8 with Fig.9, we can see
Power (dBm)
-20 -30 -40 -50 X: 1.01e+009 Y: -68.01
-60 -70 -80 0.98
0.985
0.99
0.995
1
1.005
Frequency (Hz)
1.01
1.015
1.02 9
x 10
Figure 9. Reference spurs of the test bench PLL using the proposed charge pump References [1] Wooguen Ree, ISCAS 1999, p.545 (1999). [2] Kun-Seok Lee and Hwayeal Yu, 2008 IEEE Radio Frequency Integrated Circuits Symposium, p.299 (2008). [3] Kun-Seok Lee, US patent, Application Number: US20070272923.
