Improved Procedure to Extract the Limiting Carrier

1

Improved Procedure to Extract the Limiting Carrier Velocity in Ultra Scaled CMOS devices P. Toniutti1,2 , R. Clerc2 , P. Palestri1 , C. Diouf3 , A. Cros3 , D. Esseni1 , F. Boeuf3 , G. Ghibaudo2 and L. Selmi1 1 DIEGM, Via delle Scienze 208, 33100 Udine, Italy, 2 IMEP-LAHC, MINATEC, Grenoble, France, 3 ST-Microelectronics, Crolles, France. email: [email protected]

Abstract— The validity of a previously published extraction technique for the limiting carrier velocity responsible for current saturation in nano-MOSFETs is carefully re-examined by means of accurate Multi Subband Monte Carlo transport simulations. By comparing the extracted limiting velocity to the calculated injection velocity, we identify the main sources of error of the extraction method. Then, we propose a new extraction procedure and extensively validate it. Our simulations and experimental results reconcile the values and trends of the extracted limiting velocity with the expectations stemming from quasi ballistic transport theory.

I. I NTRODUCTION

VG

MSMC S

G

where ID−lim is the upper bound of the ID obtained when the channel length LG tends to zero. The gate overdrive VGT is defined as VGS −VT H and CG is an effective gate capacitance per unit area. Both the QB and the drift diffusion (DD) models lead to Eq. 1 for LG →0, but with vlim being vinj in the QB and vsat in the DD case. The vlim extracted in [10] has been found higher than vsat , but with almost the same temperature dependence. An unexplained LG dependence [10] has also

VD

vlim

?

VS v inj =

Extraction Procedure

ID

vinj

Σ f(k)v (k) x

vinj

Σ v >0 f(k)

vsat

vx >0 x

Recent studies [1], [2], [3], [4], [5], [6] pointed out the importance of the injection velocity vinj on the performance of nano-MOSFETs. The injection velocity, defined in Fig. 1, is the average velocity of the carriers with positive group velocity vx at the virtual source (V S), that is the maximum of the potential energy barrier at the source side of the channel. Under purely ballistic transport at high VDS all carriers at the V S move with positive vx and vinj , multiplied by the charge density at the V S, gives the maximum attainable current. In real cases (quasi-ballistic transport QB) the velocity at the V S is lower than vinj , but gets closer to it as we approach purely ballistic transport. Since vinj is significantly enhanced by strain [4], [5] many studies have considered this effect to explain the effectiveness of strain technologies in improving the MOSFET on-current [2], [3]. Many techniques have been proposed to extract vinj from experiments in order to compare different technologies [7], [8], [9], [10]. In this context, Ref. [10] presented a promising technique to extract the vlim which is here defined as the velocity that yields the current per unit device width ID−lim , according to: ID−lim = CG VGT vlim (1)

D

or

VS

Fig. 1. Approach followed in this paper: the extraction procedure of [10] is applied to the ID −VG obtained from MSMC simulations; the extracted vlim is compared with the vinj calculated from the carrier velocity distributions and with the vsat used in TCAD simulations. V S denotes the Virtual Source.

been observed, thus raising doubts about the actual transport regime in nano-MOSFETs. In this work, we use an accurate and calibrated transport model for ultra scaled MOSFETs, based on the Multi-subband Monte Carlo (MSMC) approach [11], to extract the vlim by applying to the simulated ID −VG curves the technique of [10]: we compare vlim extracted from the ID −VG characteristics to vinj extracted at the V S in the device simulation (see Fig.1). We critically discuss the validity of the experimental technique and identify the most important sources of error. Then, we propose and validate an improved vlim extraction method whose results are in agreement with the values and trends predicted by QB transport theory. II. R EVIEW OF THE vlim EXTRACTION PROCEDURE OF [10] The method starts by determining the series resistances [12], the gate capacitance CG , and the linear and saturation threshold voltages (VT H,lin and VT H,sat ) as in [13]. Then, normalized “apparent” mobilities are extracted using: µapp ID−lin (2) = LG CG VGT,lin VDS lin

in linear regime, and:

µapp 2ID−sat = 2 LG sat CG VGT,sat

(3)

2

EOT [nm] 0.85

VDD [V] 1.0

Type

10

Lines: Experiments Symbols: Simulations

HP

TABLE I M AIN

PARAMETERS OF THE SIMULATED DEVICES .

LG

3

IS THE NOMINAL

GATE LENGTH .

2

DG-SOI

tSi [nm] 7

µeff [cm /Vs]

LG [nm] 15

Structure

16

-2

17

-2

NA=2x10 cm NA=3x10 cm 18

-2

NA=2.4x10 cm

where λ is the mean free path and LKT is the KT -layer, and assuming that the vlim is the same in both the saturation and linear regimes, i.e. vlim =vinj,lin =vinj,sat , the expression for the limiting velocity can be finally deduced from the apparent mobilities according to: vlim =

e(VGS − VT H,sat ) − 4kB T i h G G 2e µLapp − µLapp sat

(5)

where e is the electron charge, kB is the Boltzmann constant and T is the temperature. Eq. 5 can be derived casting the expression for ID as: (6)

that is as a combination of the long channel drift-diffusion current ID−DD , namely:  VGT,lin VDS,lin lin  = µ0 CG  ID−DD LG 2 VGT,sat   I sat D−DD = µ0 CG 2LG

(7)

and the ID−lim of Eq. 1. Eq. 6 can be derived from the QB ballistic theory in the linear regime [1] and also in saturation provided the KT -layer length takes its long channel expression, which is [14]: LKT =

2LG kB T e(VGS − VT H,sat )

(8)

Eq. 6 can also be derived from the DD model with velocity saturation, provided the Caughey-Thomas model with β=1 [15] is used for the velocity-field relation and the electric field at the source end of the channel takes the form: FS =

VGS − VT H,sat 2LG

2

0.1

(9)

1.0 Eeff [MV/cm]

Fig. 2. Comparison between the universal mobility curves of [16] and the simulated ones using the MSMC model [11] for different values of the channel doping, as a function of the effective field Eef f . Temperature is 300K.

1000 Universal 2

Universal bulk mobility MSMC T-CAD T-CAD (Recalibrated µ)

100

10

lin

−1 −1 −1 ID = ID−lim + ID−DD

10

µeff [cm /Vs]

in the saturation one. That essentially means taking the mobility as a fitting parameter to reproduce the ID −VG curves with the well known MOSFET model for long channel devices without velocity saturation. Equating the expressions for the currents in Eqs. 2 and 3 with the general quasi-ballistic currents, that can be expressed as [1]:  eVDS,lin λ lin   ID−QB = L+λ CG VGT,lin vinj,lin 2kB T (4) λ  sat  ID−QB = CG VGT,sat vinj,sat 2LKT + λ

12 -2

10

13

Ninv/2 [cm ] Fig. 3. Comparison between the long channel mobility obtained with the MSMC and T-CAD simulators in the DG devices of Tab. I. The T-CAD mobility models have been recalibrated on the MSMC results. The universal bulk mobility curve [16] is also shown.

III. A NALYSIS AND RESULTS The extraction procedure of [10] has been applied to the ID −VG calculated with accurate MSMC simulations [11] of scaled Double Gate (DG) transistors (parameters in Tab. I). The MSMC model can account for several technology boosters (high-κ dielectrics, strain) as extensively described in [14]. Fig. 2 demonstrates that the quantization and scattering models of the MSMC simulator nicely reproduce the universal bulk mobility curves of [16]. Fig. 3 shows that in the DG structure of Tab. I, the long channel mobility calculated with the MSMC simulator is still close to the universal one for undoped bulk transistors. The same figure also shows the mobility calibration that has been needed for the T-CAD simulator. Extracted vlim values are directly compared with simulated vinj in Fig. 4, showing a significant discrepancy. Note that for Lg >300 nm the extraction procedure is not reliable since Fig. 5 shows that the two terms in Eqs. 2 and 3 tend to the same value and the inverse of their difference in Eq. 5 thus tend to diverge. For shorter devices the inaccuracy of the vinj extraction is instead due to the failure of Eq. 6. In fact, as shown in Figs. 6, 7 and 8, the current deduced from Eq. 6 is in respectable

3

Isat [µA/µm]

7

velocity [10 cm/s]

1.0

0.0 10

VGS=1.0V VDS=1.0V 100 LG [nm]

10

1000

Fig. 7.

-5

100 LG [nm]

1000

60 Saturation Linear Error [%]

L/µeff [Vs/m]

Linear Saturation

Ballistic D-D(T-CAD) MSMC Eq.(6)

Same as in Fig. 6, but in saturation regime.

Fig. 4. Comparison between vinj calculated with the MSMC transport model and vlim extracted as in [10] (Eq. 5) from the ID −VG curves calculated with the MSMC model. The inaccuracy of the extraction technique is evident.

40

20

0 10

100 LG [nm]

1000

Fig. 8. Percentage error of Eq. 6 with respect to the ID of the MSMC model for the linear and saturation regimes, as extracted from Figs. 6 and 7. The calibration of the mobility models employed in the T-CAD (shown in Fig. 3) yield almost zero error in long channel devices.

-6

10 10

100 LG [nm]

1000

Fig. 5. Comparison between the linear and saturation LG /µapp obtained from the MSMC simulations of the devices in Tab. I.

1000

Ilin [µA/µm]

1000

100

vinj vlim

10

VGS=VDS=1.0V

10000

2.0

VGS=1.0V VDS=10mV

100 Ballistic DD (T-CAD) MSMC Eq.(6) 10 10

100 LG [nm]

1000

Fig. 6. Comparison between Eq. 6 (open triangles) and the results of the MSMC simulations in linear region (closed triangles). ID−lim (filled circles) is taken from ballistic MSMC simulations (no scatterings); ID−DD is taken from TCAD simulations without velocity saturation (filled squares).

agreement with MSMC simulations in the linear region, but not in the saturation region. Interestingly, the vlim we have extracted by applying the method of [10] with the MSMC curves shows the same unexplained gate length (Fig. 4) and temperature (Fig. 9) dependencies as the one extracted from the experiments in [10]. Fig. 10 shows that the velocity profile in MSMC simulations. Since velocity saturation is a well defined concept only in uniform transport conditions [17], [18] and the electric field is instead very rapidly changing along the channel in short devices, as expected, no velocity saturation is observed in the MSMC simulations unless it is artificially and erroneously imposed by the model, as it happens when the saturation velocity vsat is accounted for in the T-CAD simulations. We thus conclude that: 1) the vlim extracted according to [10] is an inaccurate estimate of vinj because Eq. 6 is inaccurate in the saturation region; 2) the results in [10] do not prove that nano-MOSFET transport is limited by vsat , since the same temperature and LG dependence is found when applying the method to the MSMC simulations where there is no velocity saturation.

4

10000

ID [µA/µm]

VGS=VDS=1.0V

7

velocity [10 cm/s]

2.0

1.0 LG=15nm LG=30nm LG=100nm 0.0

200

1000

Open: vlim Closed: vinj 300 T [K]

100 10

400

Fig. 9. Comparison between the calculated vinj (MSMC) and the vlim extracted by the method of [10] applied to ID −VG from the MSMC simulator as a function of temperature, for different gate lenght in the DG device of Tab.I. The decrement of vlim with T is an artifact of the extraction procedure.

MSMC Eq.(6) Eq.(10) (α=0.7) 100 LG [nm]

Fig. 11. Comparison between MSMC simulations of the drain current in saturation and Eq. 10, allowing to calibrate α at a value α'0.7.

60 Eq.(6) Eq.(10) (α=0.7) Error [%]

Circles:LG=15nm Triangles:LG=100nm

7

velocity [10 cm/s]

4.0 3.0 2.0

40

20

DD+vsat

1.0 0.0 0

1000

0 10

0.2

0.4

0.6

0.8

1

Fig. 10. Drift velocity versus channel position normalized to LG according to MSMC and T-CAD simulations. x=0 is the source end of the channel. The V S is not at x=0 due to the presence of the gate overlap. Note the absence of any velocity saturated region in the MSMC results.

IV. T HE NEW EXTRACTION PROCEDURE Fig. 7 shows that Eq. 6 is in good agreement with MSMC simulations in saturation only when ID is close to either ID−lim (LG ≤15 nm) or ID−DD (LG ≥300 nm). To better represent the intermediate QB regime we replace Eq. 6 with an empirical generalization, that is: =

−α ID−BAL

+

−α ID−DD

(10)

where α is an adjustable parameter, as described below. A new expression for the vlim can be worked out as:  α  α L/µapp |sat e(VGS − VT H,sat ) α = (1−ξ) + ξ (11) L/µapp |lin 4kB T where: ξ=

2kB T µapp evlim L lin

1000

Fig. 12. Percentage error of Eq. 6 (i.e. Eq. 10 with α=1 as in [10]) and Eq. 10 with α=0.7. Eq. 10 reduces the errors to values comparable to those of the linear case in Fig. 7.

x/LG

−α ID

100 LG [nm]

(12)

Figs. 11 and 12 show that α'0.7 allows us to nicely reproduce the whole ID vs. LG curve. Moreover, Fig. 13 shows that the same α value yields good agreement between the extracted vlim and the expected vinj calculated from simulations as in Fig. 1. Fig. 14 shows that the vlim extracted by our new method has the expected dependence upon LG and

T and it is in good quantitative agreement with the calculated vinj also for intermediate LG values. These results demonstrate that the new extraction procedure based on Eqs. 10, 11 and 12 yields results because, if applied to simulated data, provides vlim values in agreement with the limiting velocity extracted from internal microscopic analysis of the carrier motion in the device. V. E XPERIMENTS We have applied the new technique to bulk MOSFETs fabricated with a 28 nm strained Silicon technology (parameters in Tab. II) [19]. Fig. 15 shows that the new procedure yields significantly higher velocity with respect to the results 28-LSTP Structure Bulk Stress [GPa] 1.5GPa (Uni) Oxide SiON + HfSiON EOT [nm] 1.11 Vdd [v] 1.0 NA [cm−2 ] 4×1017 Type LSTP TABLE II M AIN PARAMETERS OF THE MEASURED DEVICES .

5

α=0.7 1.0

0.4 0.2

vinj vlim (Eq.(5)) vlim (Eq.(11))

VTH,lin

VTH,sat Open symbols: Exp. Closed symbols: MSMC

0

0.0 10

100

2.0 LG=100nm

Fig. 16. Comparison between experimental VT H for the device described in Tab. II and MSMC simulations.

1000 ID-sat Open symbols: Exp. Closed symbols: MSMC 100

ID-lin

7

ID [µA/µm]

Fig. 13. Comparison between the vinj (extracted at the VS in theMSMC simulations), the vlim obtained applying the method of [10] (Eq. 5) and the new procedure (Eq. 11). α'0.7 yields good agreement between the extracted vlim and vinj .

LG=15nm

100 LG [nm]

LG [nm]

velocity [10 cm/s]

VTH [V]

0.6

7

velocity [10 cm/s]

2.0

10

1.0 vinj vlim (Eq.(5)) vlim (Eq.(11)) 0.0

200

300 400 T [K]

Fig. 17. Comparison between experimental ID for the device described in Tab. II and MSMC simulations. Uniaxial strain (1.5 GPa) has been included in the MSMC as expected from experimental analysis [19]. The strain enhancement model has been described in [2].

200

300 400 T [K]

Fig. 14. Comparison between the vinj (MSMC) and the vlim by the new method (with α=0.7) as a function of the temperature and for different gate length. The negligible temperature variation of vinj of the MSMC results is better reproduced using the new method.

7

velocity [10 cm/s]

2.0

1.5

1.0

vinj (MSMC) Eq.(5) Eq.(11)

100 LG [nm]

VGT=VDS=VDD

0.5

100

obtained using the method in [10], free of anomalies in the LG dependence. The extracted velocity is also higher than vsat , as expected in such short transistors where the strain booster is very effective. To confirm the quantitative validity of the extracted values, we performed MSMC simulations of these devices. The default model parameters that reproduce the universal mobility curves of long devices [16] (as shown in Fig. 2) have been maintained [11]. Figs. 16 and 17 compare the experimental VT H and ID with the MSMC simulations while and demonstrate good mutual agreement over a wide range of channel length and bias conditions. Filled circles in Fig. 15 report vinj at the V S of the MSMC simulations calculated according to the definition in Fig. 1. As can be seen, the simulated vinj is in very good agreement with the vlim extracted from the experiments and the discrepancy is not larger than that between measured and simulated ID in Fig. 17 providing reassuring indications on the validity of the new extraction procedure.

LG [nm] VI. C ONCLUSIONS Fig. 15. vlim extracted using the method based on the old Eq. 5 and the new Eq 11 from the experimental data on the devices of Tab. II. The vinj calculated with MSMC simulations is in good agreement with the vlim extracted by the new method.

A detailed analysis of the results in [10] based on an accurate transport model for nanoscale transistors led us to propose an improved extraction technique for the limiting velocity for carrier transport in nano-MOSFETs. The new

6

method has been extensively validated by simulations and, when applied to 28 nm technology devices, provides realistic estimates of the injection velocity. ACKNOWLEDGMENTS The work was partly supported by ?? R EFERENCES [1] M. Lundstrom and Z. Ren, “Essential physics of carrier transport in nanoscale MOSFETs,” IEEE Transactions on Electron Devices, vol. 49, no. 1, pp. 133–141, 2002. [2] N. Serra, F. Conzatti, D. Esseni, M. De Michielis, P. Palestri, L. Selmi, S. Thomas, T. Whall, E. Parker, D. Leadley, L. Witters, A. Hikavyy, M. Hytch, F. Houdellier, E. Snoeck, T. Wang, W. Lee, G. Vellianitis, M. van Dal, B. Duriez, G. Doornbos, and R. Lander, “Experimental and physics-based modeling assessment of strain induced mobility enhancement in FinFETs,” in IEEE International Electron Devices Meeting, 2009, pp. 1–4. [3] F. Conzatti, N. Serra, D. Esseni, M. De Michielis, A. Paussa, P. Palestri, L. Selmi, S. Thomas, T. Whall, D. Leadley, E. Parker, L. Witters, M. Hytch, E. Snoeck, T. Wang, W. Lee, G. Doornbos, G. Vellianitis, M. van Dal, and R. Lander, “Investigation of Strain Engineering in FinFETs Comprising Experimental Analysis and Numerical Simulations,” IEEE Transactions on Electron Devices, vol. 58, no. 6, pp. 1583–1593, 2011. [4] S. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, S. Nakaharai, T. Numata, J. Koga, and K. Uchida, “Sub-band structure engineering for advanced CMOS channels,” Solid-State Electronics, vol. 49, no. 5, pp. 684–694, 2005. [5] M. Ferrier, R. Clerc, L. Lucci, Q. Rafhay, G. Pananakakis, G. Ghibaudo, F. Boeuf, and T. Skotnicki, “Conventional Technological Boosters for Injection Velocity in Ultrathin-Body MOSFETs,” IEEE Transactions on Nanotechnology, vol. 6, no. 6, pp. 613–621, 2007. [6] C. Jeong, D. Antoniadis, and M. Lundstrom, “On Backscattering and Mobility in Nanoscale Silicon MOSFETs,” IEEE Transactions on Electron Devices, vol. 56, no. 11, pp. 2762–2769, 2009. [7] M.-J. Chen, H.-T. Huang, K.-C. Huang, P.-N. Chen, C.-S. Chang, and C. Diaz, “Temperature dependent channel backscattering coefficients in nanoscale MOSFETs,” in IEEE International Electron Devices Meeting., 2002, pp. 39–42. [8] V. Barral, T. Poiroux, J. Saint-Martin, D. Munteanu, J.-L. Autran, and S. Deleonibus, “Experimental Investigation on the Quasi-Ballistic Transport: Part I - Determination of a New Backscattering Coefficient Extraction Methodology,” IEEE Transactions on Electron Devices, vol. 56, no. 3, pp. 408–419, 2009. [9] G. Giusi, G. Iannaccone, D. Maji, and F. Crupi, “Barrier Lowering and Backscattering Extraction in Short-Channel MOSFETs,” IEEE Transactions on Electron Devices, vol. 57, no. 9, pp. 2132–2137, 2010. [10] D. Fleury, G. Bidal, A. Cros, F. Boeuf, T. Skotnicki, and G. Ghibaudo, “New experimental insight into ballisticity of transport in strained bulk MOSFETs,” in Symposium on VLSI Technology, 2009, pp. 16–17. [11] L. Lucci, P. Palestri, D. Esseni, L. Bergagnini, and L. Selmi, “Multisubband Monte Carlo Study of Transport, Quantization, and ElectronGas Degeneration in Ultrathin SOI n-MOSFETs,” IEEE Transactions on Electron Devices, vol. 54, no. 5, pp. 1156–1164, 2007. [12] D. Fleury, A. Cros, G. Bidal, J. Rosa, and G. Ghibaudo, “A New Technique to Extract the Source/Drain Series Resistance of MOSFETs,” IEEE Electron Device Letters, vol. 30, no. 9, pp. 975–977, 2009. [13] D. Fleury, A. Cros, H. Brut, and G. Ghibaudo, “New Y-function-based methodology for accurate extraction of electrical parameters on nanoscaled MOSFETs,” in IEEE International Conference on Microelectronic Test Structures, 2008, pp. 160–165. [14] D. Esseni, P. Palestri, and L. Selmi, Nanoscale MOS transistors. Cambridge University Press, 2011. [15] D. Caughey and R. Thomas, “Carrier mobilities in silicon empirically related to doping and field,” Proceedings of the IEEE, vol. 55, no. 12, pp. 2192–2193, 1967. [16] S. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the universality of inversion layer mobility in Si MOSFET’s: Part I-effects of substrate impurity concentration,” IEEE Transactions on Electron Devices, vol. 41, no. 12, pp. 2357–2362, 1994. [17] J. A. Cooper and D. F. Nelson, “High-field drift velocity of electrons at the Si-SiO2 interface as determined by a time-of-flight technique,” Journal of Applied Physics, vol. 54, no. 3, pp. 1445–1456, 1983.

[18] C. Jacoboni and L. Reggiani, “The Monte Carlo method for the solution of charge transport in semiconductors with applications to covalent materials,” Reviews of Modern Physics, vol. 55, pp. 645–705, 1983. [19] F. Arnaud, A. Thean, M. Eller, M. Lipinski, Y. Teh, M. Ostermayr, K. Kang, N. Kim, K. Ohuchi, J.-P. Han, D. Nair, J. Lian, S. Uchimura, S. Kohler, S. Miyaki, P. Ferreira, J.-H. Park, M. Hamaguchi, K. Miyashita, R. Augur, Q. Zhang, K. Strahrenberg, S. ElGhouli, J. Bonnouvrier, F. Matsuoka, R. Lindsay, J. Sudijono, F. Johnson, J. Ku, M. Sekine, A. Steegen, and R. Sampson, “Competitive and cost effective high-k based 28nm CMOS technology for low power applications,” in IEEE International Electron Devices Meeting, 2009, pp. 1–4.