Feb 1, 2002 - ABSTRACT. Data processing apparatus comprising: a processor core hav ing means for executing successive pr
USO0RE43248E
(19) United States (12) Reissued Patent
(10) Patent Number: US RE43,248 E (45) Date of Reissued Patent: Mar. 13, 2012
Nevill (54)
INTEROPERABILITY WITH MULTIPLE
4,398,243 A
8/1983 Holberger et al.
INSTRUCTION SETS
4,434,459 A 4,434,461 A 4,459,657 A
2/1984 Holland et a1. 2/1984 Puhl 7/1984 Murao
(75) Inventor:
Edward Colles Nevill, Huntingdon (GB)
(73) Assignee: ARM Limited, Cambridge (GB)
4,511,966 A
4/1985
Hamada ...................... .. 364/200
4,514,803 A
4/1985
Agnew et a1. ............... .. 364/200
4,554,627 A
11/1985 Holland et a1.
(Continued)
(21) Appl. No.: 10/066,475
FOREIGN PATENT DOCUMENTS
(22)
Filed:
Feb. 1, 2002
109567
EP
Reissue of:
(64)
10/1983
(Continued)
Related US. Patent Documents
OTHER PUBLICATIONS
Patent No.:
6,021,265
Issued:
Feb. 1, 2000
Order Construing Disputed Claims and Terms, ARM Limited v.
Appl. No.:
08/840,557 Apr. 14, 1997
picoTurbo, Inc, Case No. C-00-00957 (N.D. Calif, Jun. 15,
U.S. Applications: (62) Division ofapplicationNo. 08/477,781, ?led on Jun. 7,
(Continued)
Filed:
2001)(Wilken, 1.).
1995, noW Pat. No. 5,758,115.
(30)
Primary Examiner * Kenneth R Coulter
(74) Attorney, Agent, or Firm * White & Case LLP
Foreign Application Priority Data
(57) Jun. 10, 1994
(GB) .................................... .. 9411670
(51)
Int. Cl. G06F 9/30
(52)
US. Cl. ...................................... .. 712/209; 712/210
(58)
Field of Classi?cation Search ................ .. 712/209,
(2006.01)
executed; a program counter register for indicating the address of a next program instruction Word in the data memory; means for modifying the contents of the program counter register in response to a current program instruction Word; and control means, responsive to one or more prede
712/210
See application ?le for complete search history. (56)
References Cited
termined indicator bits of the program counter register, for controlling the processor core to execute program instruction Words of a current instruction set selected from the predeter
U.S. PATENT DOCUMENTS 4,217,638 A 4,236,204 A 4,274,138 A
8/1980 Namimoto et al. 11/1980 Groves 6/1981 Shimokawa
4,338,663 A
7/1982
4,346,437 A
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mined plurality of instruction sets and speci?ed by the state of the one or more indicator bits of the program counter register.
Strecker et a1. ............. .. 712/228
10
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ABSTRACT
Data processing apparatus comprising: a processor core hav ing means for executing successive program instruction Words of a predetermined plurality of instruction sets; a data memory for storing program instruction Words to be
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US RE43,248 E Page 2 US. PATENT DOCUMENTS
8887 888,888,888.
5;
533333;;
3433;
9/1987 Keeley et a1. ............... .. 364/200 .
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.
.
.
Inc, Case N0. C-00-00957 (N.D. Calif, Dec. 22, 2000). Initial Disclosure by Defendant picoTurbo, Inc. of Prior Art Under
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’
’
"m
’
’
’
ay
1
'
_
_
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5,542,059 A
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5 606 714 A
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Gilson
...... ..
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.
5,630,083 A
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536303153 A
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5,664,147 A 5,666,355 A
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5,689,672 A
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Jaggar
ARM’s Opposition and Cross Motion for Summary Judgment that the Patents-in-Suit are not Invalid, Nov. 2, 2001. . . , . . . . . Plaintiff ARM s Reply in Support of its Opposition and Cross Motion for Summary Judgment that the Patents-in-Suit are not Invalid.
5,740,461
A
5 758 l 15 A 5,781,750 A 88
537843585 A
7/1998 Denman
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5,784,636 A
7/199g Rupp ,,,,,,,,,,,,,,,,,,,,, ,, 395/g0037
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5,796,973 A
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5,968,161 A
10/1999 Southgate ..................... .. 712/37
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5,970,254 A
10/1999 C001_