IEEE TRANSACTIONS ON COMPUTERS,
VOL. 50, NO. 11,
NOVEMBER 2001
1103
Introduction to the Special Section on High Performance Memory Systems Haldun Hadimioglu, Member, IEEE, David Kaeli, Member, IEEE, and Fabrizio Lombardi, Member, IEEE
æ 1
INTRODUCTION
W
HILE microprocessor designs have continued to increase in speed and complexity, dynamic random access memories (DRAMs) have failed to keep pace. This trend has created a widening gap in performance between microprocessors and their supporting memory systems. While hierarchical memories (i.e., caches) have been used to bridge this gap in the past, the distance (in terms of cycles) between caches and DRAMs continues to grow. Our inability to design memory systems that can keep pace has warranted looking for new approaches bridging the memory wall. In June 2000, a new workshop was held with the 27th International Symposium on Computer Architecture (ISCA27), titled: ªSolving the Memory Wall Problem.º Dr. Maurice V. Wilkes provided the keynote talk on ªThe Memory Gapº and has also provided us with his perspective on ªHigh Performance Memory Systemsº in this section. Many of the papers submitted to this section were more mature versions of the work presented at this new workshop. A second workshop was held with ISCA28 in Goteborg, Sweden. This special section of the IEEE Transactions on Computers is devoted to papers focused on the issue of ªAdvances in High Performance Memory Systems.º Forty-two papers were submitted to this section, with each paper receiving a minimum of three reviews. More than 160 reviews were completed by the referees. We would like to acknowledge the work of these referees in producing an outstanding set of 10 papers for this section. These papers provide a good cross-section of the research underway both in industry and academia on addressing the memory wall problem. We have organized this issue around three broad approaches:
1. 2. 3.
hardware approaches, architectural approaches, and compiler/operating system approaches.
. H. Hadimioglu is with the Department of Electrical Engineering and Computer Science, Polytechnic University, 333 Jay St., Brooklyn, NY 11201. E-mail:
[email protected]. . D. Kaeli and F. Lombardi are with the Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115. E-mail: {kaeli, lombardi}@ece.neu.edu. For information on obtaining reprints of this article, please send e-mail to:
[email protected], and reference IEEECS Log Number 114462.
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HARDWARE APPROACHES
The first paper, ªCache-Memory Interfaces in Compressed Memory Systemsº by Caroline D. Benveniste, Peter A. Franaszek, and John T. Robinson, describes a compressed random access memory system that is being used in IBM's Memory Expansion Technology. In the second paper, Lixin Zhang, Zhen Fang, Mike Parker, Binu K. Mathew, Lamber Schaelicke, John B. Carter, Wilson C. Hsieh, and Sally A. McKee describe the Impulse Memory Controller. Impulse provides us with the ability to perform dynamic optimization at the memory controller interface. The third paper, ªHigh-Performance DRAMs in Workstation Environmentsº by Vinodh Cuppa, Bruce Jacob, Brian Davis, and Trevor Mudge, presents a performance study of some of the more recent advances in DRAM design. This study evaluates eight different design features in terms of latency and bandwidth. The fourth paper in this issue, titled ªHardware and Software Techniques for Controlling DRAM Power Modesº and written by Victor Delaluz, Mahmut Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, and Mary Jane Irwin, presents a different aspect of the memory wall problem: power management. The memory system can consume as much as 90 percent of the overall system energy dissipation. This paper presents a number of hardware and compile-time techniques to manage power more effectively.
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ARCHITECTURAL APPROACHES
Next, we look at three papers that address the memory wall problem utilizing advanced architectural techniques. The next paper in this issue, ªSilent Stores and Store Value Localityº by Kevin M. Lepak, Gordon B. Bell, and Mikko H. Lipasti, provides an in-depth analysis of the causes of stores which overwrite a value in memory with the same value (i.e., a silent store). By eliminating these stores, we can reduce the demands on the memory system. The sixth paper, ªImproving Performance of Large Physically Indexed Caches by Decoupling Memory Addresses from Cache Addressesº by Rui Min and Yiming Hu, proposes using color-indexed physically addressed caches that can reduce conflict misses. The last paper in this group on architectural techniques is titled ªDesigning a Modern Memory Hierarchy with Hardware Prefetching.º In this paper, Wei-Fen Lin, Steven K. Reinhardt, and Doug Burger investigate tuning accesses to the second-level cache with the goal of providing sustained bandwidth.
0018-9340/01/$10.00 ß 2001 IEEE
1104
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IEEE TRANSACTIONS ON COMPUTERS,
COMPILER/OPERATING SYSTEM APPROACHES
In this section, we have included three papers that address memory performance employing the operating system or advanced compilation techniques. The eighth paper, titled ªHardware Compressed Main Memory: Operating System Support and Performance Evaluationº by Bulent Abali, Mohammad Banikazemi, Xiaowei Shen, Hubertus Franke, Dan E. Poff, and T. Basil Smith, describes operating system enhancements used to manage the MXT compressed memory system (see the first paper in this section). In the ninth paper, by Rajeev Barua, Walter Lee, Saman Amarasinghe, and Anant Agarwal, titled ªCompiler Support for Scalable and Efficient Memory Systems,º the authors describe the Maps technology used to perform bank disambiguation at compile time. The final paper in this section, titled ªAutomatic Code Mappng on an Intelligent Memory Architectureº by Yan Solihin, Jaejin Lee, and Josep Torrellas, presents compile-time algorithms for exploiting processor-in-memory architectures.
5
SUMMARY
The architecture, design, and implementation of high performance memory systems continues to be an area ripe for new advances in technology and algorithms. Researchers will need to aggressively pursue new ideas in this area if we ever intend to close the memory gap.
ACKNOWLEDGMENTS We would like to thank all of the authors who submitted papers to this section. We hope that the readers find this section valuable and enjoyable. We would like to thank the students of the Northeastern University Computer Architecture Research Laboratory (NUCAR) for their assistance during the review process and acknowledge the following individuals who served as referees for this special issue: D. Albonesi, M. Annavaram, H. Aydin, J. Baer, R. Balasubramonian, I. Bahar, S. Bartolini R. Barua, C. Benveniste, L. Bhuyan, D. Burger, M. Burtscher, A. Buyuktosunoglu, B. Calder, J. Carter, J. Chang, M. Charney, F. Chong, B. Cockburn, J. Corbal, V. De La Luz, A. Delis, A. Dominguez, S. Dwarkadas, S. Eggers, D. Elliott, J. Emer, B. Falsafi, M. Farrens, R. Figueiredo, R. Flynn, M. Forsell, H. Franke, E. Gehringer, R. Giorgi, B. Goeman, P. Gonzalez, S. Haga, U. Holze, W. Hong, Y. Hu, R. Ito, B. Jacob, S. Jones, N. Jouppi, J. Kalamatianos, G. Kandiraju, B. Kazar, G. Kedem, D. Keen, K. Keeton, A. Khalafi, P. Kogge, C. Kulkarni, J. Lee, W. Lee, Z. Li, D. Lilja, W. Lin, M. Lipasti, C. Luk, M. Martonosi, S. McFarling, F. Meyer, D. Morano, A. Moshovos, T. Mudge, S. Mukherjee, W. Najjar, S. Onder, D. Ortega, N. Park, M. Pearson, V. Piuri, D. Poff, A. Prete, V. Raman, S. Reinhardt, S. Rixner, L. Sadwick, N. Sam, X. Shen, T. Sherwood, A. Sivasubramaniam, Y. Solihin, Y. Song, V. Srinivasan, P. Stenstrom, S. Swarkadas, J. Torrellas, D. Tullsen, G. Tyson, M. Valero, S. Weiss, S. Yang, Q. Yang, E. Yardimci, J. Yi, X. Zhang, Z. Zhang, and B. Zorn.
VOL. 50,
NO. 11,
NOVEMBER 2001
Haldun Hadimioglu received the BS and MS degrees in electrical engineering from the Middle East Technical University, Ankara, Turkey. He received the PhD degree in computer science from the Polytechnic University in New York. His PhD research was in parallel processing, parallel disk systems and file servers. He worked as a research engineer at PETAS in Ankara, Turkey, and later as an instructor during his PhD studies. He is involved in the development of high-speed optical packet switching systems, such as building the photonic frontend processor of a WDM multicast switch. His other research interests are ASIC design of ATM switch circuits, network processors, and memory performance improvement techniques which include compression-based and block-based execution models. He coorganized the Solving the Memory Wall Workshop at ISCA 2000 and the Memory Performance Issues Workshop at ISCA 2001. In addition, he has taken part in computer architecture education workshops. He is currently an Industry Associate Professor in Computer and Information Science and Computer Engineering at Polytechnic University. He is also a member of the Distributed Information Systems Group of the Center for Advanced Technology in Telecommunications at Polytechnic University. He is a member of the IEEE, ACM, and Sigma Xi. David Kaeli received the BS and PhD degrees in electrical engineering from Rutgers University and the MS degree in computer engineering from Syracuse University. He is presently an associate professor on the Electrical and Computer Engineering Faculty at Northeastern University, Boston, where he directs the Northeastern University Computer Architecture Research Laboratory (NUCAR). Prior to joining Northeastern in 1993, he spent 12 years at IBM, the last at the T.J. Watson Research Center, Yorktown Heights, New York. Dr. Kaeli is an associate editor of the IEEE Transactions on Computers, a member of the Executive Committee of the IEEE TCCA, and is a US National Science Foundation (NSF) CAREER receipient. He is also a Research Thrust leader in the NSF CenSSIS Engineering Research Center at Northeastern. He is a member of the IEEE. Fabrizio Lombardi graduated in 1977 from the University of Essex (UK) with the BSc (Hons.) degree in electronic engineering. In 1977, he joined the Microwave Research Unit at University College London, where he received the Master in Microwaves and Modern Optics (1978), the Diploma in Microwave Engineering (1978), and the PhD degree from the University of London (1982). He is currently the chairperson of the Department of Electrical and Computer Engineering and holder of the International Test Conference (ITC) Endowed Professorship at Northeastern University, Boston. Prior to joining Northeastern, he was a faculty member at Texas Tech University, the University of Colorado-Boulder, and Texas A&M University. He has received many professional awards: the Visiting Fellowship at the British Columbia Advanced System Institute, University of Victoria, Canada (1988), twice the TEES Research Fellowship (1991-1992, 1997-1998), the Halliburton Professorship (1995), and an International Research Award from the Ministry of Science and Education of Japan (1993-1999). Dr. Lombardi was the recipient of the 1985/86 Research Initiation Award from the IEEE/ Engineering Foundation, a Silver Quill Award from Motorola-Austin (1996), and a Distinguished Visitor of the IEEE Computer Society for the period 1990-1993. He was an associate editor of the IEEE Transactions on Computers (1996-2000). Currently, he is the associate editor-in-chief of the IEEE Transactions on Computers. He has been involved in organizing many international symposia, conferences, and workshops sponsored by organizations such as NATO and IEEE, as well as guest editor for archival journals and magazines such as the IEEE Transactions on Computers, IEEE Micro, and IEEE Design and Test. His research interests are fault-tolerant computing, testing and design of digital systems, configurable computing, defect tolerance, and CAD VLSI. He has published extensively in these areas and has edited six books. He is a member of the IEEE.
