Investigation of Polysilazane-Based SiO2 Gate Insulator ... - IEEE Xplore

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 3, MARCH 2013

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Investigation of Polysilazane-Based SiO2 Gate Insulator for Oxide Semiconductor Thin-Film Transistors Huynh Thi Cam Tu, Satoshi Inoue, Phan Trong Tue, Takaaki Miyasako, and Tatsuya Shimoda

Abstract—To realize all-solution-processed oxide semiconductor thin-film transistors (TFTs), for use in display applications in particular, a polysilazane-based SiO2 gate insulator is investigated. The gate leakage current was reduced to 1 × 10−8 A/cm2 at 1 MV/cm. TFTs were successfully fabricated using a ZrInZnO precursor solution for the active layer and a polysilazane-based solution for the gate insulator. A smooth interface without defects was confirmed in the ZrInZnO/SiO2 system. The resulting TFTs exhibited a field-effect mobility of 19–29 cm2 · V−1 · s−1 with a low leakage current of less than 9 × 10−11 A. These results are very promising for the development of all-solution-processed oxide semiconductor TFTs, which have the potential to replace TFTs fabricated by vacuum deposition methods.

In this paper, therefore, we applied the solution-processed SiO2 gate insulators in oxide semiconductor TFTs. Polysilazane was used as a precursor because of its potential to form a dense film and to reduce the leakage current at a lower annealing temperature [9] compared with other precursors such as tetraethyl orthosilicate and tetramethyl orthosilicate [11], [12]. This paper reports the properties and evaluates the conduction mechanism of the SiO2 films formed using a polysilazane-based solution. Furthermore, the performance of the solutionprocessed ZrInZnO TFTs fabricated using the polysilazanebased SiO2 gate insulator is described for the first time.

Index Terms—Gate insulator, leakage current, oxide semiconductor, polysilazane, SiO2 , solution process, thin-film transistor (TFT).

II. E XPERIMENTAL D ETAILS

I. I NTRODUCTION

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XIDE semiconductor thin-film transistors (TFTs) have attracted considerable interest for use in next-generation flat-panel displays because of their high electron mobility and high optical transparency [1]–[5]. Many researchers have fabricated oxide semiconductor TFTs by using vacuum deposition methods such as RF magnetron sputtering and plasmaenhanced chemical vapor deposition (PECVD); however, these methods use energy and materials inefficiently. In contrast, solution processing can reduce the energy requirements as well as material wastage. SiO2 has been used as a gate insulator in most oxide semiconductor TFTs because of its low leakage current and high breakdown voltage[6]–[8]. These SiO2 films are fabricated by vacuum deposition methods, i.e., PECVD and sputtering. Although the solution-processed SiO2 films have been used as gate insulator in amorphous silicon TFTs and polycrystalline silicon TFTs [9], [10], these films have not been applied to the oxide semiconductor TFTs.

Manuscript received November 12, 2012; revised December 17, 2012, and January 7, 2013; accepted January 14, 2013. Date of publication February 4, 2013; date of current version February 20, 2013. This work was supported by the ERATO program, Japan. The review of this paper was arranged by Editor J. Huang. H. T. C. Tu and T. Shimoda are with the School of Materials Science, Japan Advanced Institute of Science and Technology, Nomi 923-1292, Japan (e-mail: [email protected]; [email protected]). S. Inoue and P. T. Tue are with the Green Devices Research Center, Japan Advanced Institute of Science and Technology, Nomi 923-1211, Japan (e-mail: [email protected]; [email protected]). T. Miyasako is with Yokkaichi Research Center, JSR Corporation, Yokkaichi 5108552, Japan (e-mail: [email protected]). Digital Object Identifier 10.1109/TED.2013.2241440

To form the SiO2 films, we used a polysilazane-based solution (NP110-20, AZ Electronic Materials) consisting of a basic unit (H2 Si−NH)n that undergoes the following reaction: −(H2 Si−NH) − +2H2 O → SiO2 + NH3 + 2H2 . To evaluate the films’ properties, 5% polysilazane diluted with xylene was spin coated on p+ -silicon substrates at 2500 r/min for 30 s and dried at 250 ◦ C for 5 min. Next, these films were annealed for 2 h under air atmosphere. The annealing temperatures of 250 ◦ C, 350 ◦ C, and 450 ◦ C were used. The thicknesses of the SiO2 films were 121, 118, and 114 nm after annealing at 250 ◦ C, 350 ◦ C, and 450 ◦ C, respectively. The thickness was measured by ellipsometry using a spectroscopic ellipsometer (SEMILAB Sopra GES5E). The Cauchy model was chosen to fit the ellipsometry data [13]. The molecular composition of the films was characterized by a Fourier transform infrared (FT-IR) spectrophotometer (Shimadzu FT-IR8200PC). Thermal desorption spectroscopy (TDS) was used to investigate the structural modification of the films by annealing. To investigate the electronic properties of these SiO2 films, capacitors were fabricated. A 200-nm layer of platinum was sputtered on the films to form the top electrodes. The leakage current was measured using a semiconductor parameter analyzer (Agilent 4155C). Positive voltages were applied to the top electrode of the capacitor, while the bottom electrode was grounded. High-frequency capacitance-voltage (C–V ) measurements were used to determine the dielectric constant of the SiO2 films. The C–V characteristics were measured at a frequency of 100 kHz by using an Agilent 4284A LCR meter.

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 3, MARCH 2013

Fig. 1. Schematic cross-sectional view of TFT with SiO2 gate insulator using polysilazane-based solution.

Fig. 1 shows the structure of the oxide semiconductor TFT. Reverse-staggered TFTs were fabricated, and the p+ silicon substrate was used as their gate electrodes. First, the polysilazane-based solution was spin coated on the substrate and annealed at 450 ◦ C for 2 h, forming a SiO2 gate insulator with a thickness of 115 nm. Second, the ZrInZnO precursor solution was spin coated on the SiO2 film at 3000 r/min for 30 s and annealed by rapid thermal annealing (RTA) at 500 ◦ C for 10 min in oxygen ambient to form a 20-nm ZrInZnO active layer. A ZrInZnO solution with a concentration of 0.2 mol/kg was synthesized by blending 0.2 mol/kg of zinc chloride (ZnCl2 , Kanto Chemical) in 2-methoxyethanol (Kanto Chemical) and 0.2 mol/kg of indium (III) acetylacetonate [In(OCCH3 CHOCCH3 )3 , Sigma-Aldrich] and zirconium (IV) butoxide [Zr(OC4 H9 )4 , Sigma-Aldrich] dissolved in propionic acid (Kanto Chemical) [14]. The atomic ratio of Zr : In : Zn was 0.05 : 2 : 1. Third, the ITO film was deposited by RF sputtering in Ar gas at 8 × 10−4 Pa and was patterned by a lift-off technique to form source and drain electrodes. Fourth, the ZrInZnO film was patterned by using inductively coupled plasma reactive-ion etching at 80-W ICP power, 16-W RF power, and 50-sccm Ar for 7 min to form the channel patterns. Finally, the TFTs were postannealed with RTA at 400 ◦ C for 10 min in ambient air. The interface of the ZrInZnO/SiO2 system was characterized by energy-dispersive X-ray spectroscopy (EDX), transmission electron microscopy (TEM), and secondary ion mass spectroscopy (SIMS). The transfer (ID –VG ) and output (ID –VD ) characteristics of the TFTs were measured using a semiconductor parameter analyzer (Agilent 4155C). III. R ESULTS AND D ISCUSSION Fig. 2 shows the FT-IR spectra at 1200–700 cm−1 . The 795and 1080-cm−1 peaks are attributed to the Si–O vibration mode [15]. The absorption peaks corresponding to the Si-N vibration mode (around 875 cm−1 [16]) and the Si-H vibration mode (around 950 cm−1 [11]) are observed. These Si-N and Si-H peaks became less intense with increasing annealing temperature and almost disappeared at 450 ◦ C. It is considered that polysilazane was effectively converted to SiO2 at 450 ◦ C [12]. Fig. 3 shows the data from the TDS analysis of the SiO2 films after being dried at 250 ◦ C for 5 min and after annealing at 450 ◦ C for 2 h under air atmosphere. The NH3 intensity was dramatically reduced by annealing, which is consistent with the results of the FT-IR analysis. However, a small amount of NH3 was desorbed even after annealing. These data suggest that nitrogen remains in the SiO2 films. Therefore, an enhancement

Fig. 2. FT-IR normalized spectra of SiO2 films using a polysilazane-based solution with annealing temperatures of 250 ◦ C, 350 ◦ C, and 450 ◦ C, respectively.

Fig. 3. Intensities of NH3 (molecular weight = 17) from TDS analysis of SiO2 films using polysilazane-based solution before and after annealing at 450 ◦ C.

of the conversion from polysilazane to SiO2 is necessary for obtaining higher quality films. Fig. 4 shows the leakage current densities of the SiO2 films formed from the polysilazane-based solution. The leakage current density decreases significantly with increasing annealing temperature, and it is reduced to 1 × 10−8 A/cm2 at 1 MV/cm at 450 ◦ C. This is the same level as those of CVD-SiO2 films [17]. At a low electric field, the leakage currents are reportedly due to space-charge-limited conduction [18]. In this conduction mechanism, the current is produced by the injection of carriers from the electrode to oxide. The injected carriers are trapped in trap states present in the forbidden gap of the oxide, which influences the current flow. These traps play an important role in current conduction in SiO2 films. The trap states are understood to be generated by Si–N and Si-H bonds in the SiO2 films that were reduced by annealing. Consequently, the leakage current decreased, which is supported by the FT-IR data. In addition, the kink phenomenon was observed at around 1.2 MV/cm in the sample annealed at 450 ◦ C, which suggests that another mechanism became dominant at this point.

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Fig. 6. Dielectric constant kr extracted from the slope of Poole–Frenkel linear fitting and dielectric constant εr obtained from the high-frequency C–V measurements.

Fig. 4. Leakage current density of thermal SiO2 film (with a thickness of 100 nm) and of SiO2 films using polysilazane-based solution annealed at 250 ◦ C, 350 ◦ C, and 450 ◦ C.

Fig. 7. EDX line analysis across the ZrInZnO/SiO2 system.

Fig. 5. Poole–Frenkel [ln(J/E)−E 1/2 ] plot. The filled circles indicate the data used for linear fitting.

Because the kink phenomenon occurred at a moderate electric field, we believe that the Poole–Frenkel conduction mechanism could govern the leakage current in the SiO2 film. This mechanism is also influenced by the trap states in the oxide. When an electric field is applied to the oxide, the barrier height of the trap is lowered, which makes it easier for the trapped carriers to move to another trap state. Therefore, the current increases with the applied electric field. The Poole–Frenkel current can be mathematically described by [19] ⎛ ⎞⎤ ⎡  3 q E ⎠⎦ 1 ⎝ qφt − (1) JPF = qNt μE exp ⎣− kT πε0 kr where Nt , μ, qφt , and kr are the trap density, carrier mobility, barrier height potential of the traps, and dielectric constant of the oxide, respectively. The expression q 3 E/πε0 kr indicates the magnitude of the reduction in the trap barrier height by the electric field.

Fig. 8. SIMS depth profile of 131 OIn− and 28 Si+ in ZrInZnO/SiO2 system.

Fig. 9. Cross-sectional TEM images of the amorphous ZrInZnO/SiO2 system: (a) Low magnification and (b) high magnification.

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 3, MARCH 2013

Fig. 10. (a) ID –VG transfer characteristics and (b) ID –VD characteristics of the ZrInZnO TFTs with SiO2 gate insulator using polysilazane-based solution.

To conclude that Poole–Frenkel conduction dominates the leakage current, the following requirements should be satisfied. √ 1) The Poole–Frenkel plot [ln(J/E), E] is linear. 2) The dielectric constant kr induced from the Poole– Frenkel plot is close to dielectric constant εr which is obtained by other measurements. From the data of leakage √ current of the SiO2 films, the Poole– Frenkel plot [ln(J/E), E] was examined, as shown in Fig. 5. As can be seen, the obtained curves were linear. The dielectric constants kr were extracted from the slope of the Poole–Frenkel plots. The equation for the slope (S) deduced from (1) is as follows:  q3 1 S= . (2) kT πε0 kr The extracted dielectric constants kr were compared with the dielectric constants εr obtained by C–V measurements, which are shown in Fig. 6. Note that kr is close to εr for the sample annealed at 450 ◦ C; therefore, we concluded that the leakage current at an electric field of > 1.2 MV/cm was due to Poole–Frenkel conduction. Fig. 7 shows the EDX line profile, which indicates the interdiffusion of components between the ZrInZnO and SiO2 films. The spatial resolution of this system is about 4 nm. There is a rather small diffusion of zinc in the ZrInZnO/SiO2 system. To evaluate the interdiffusion of silicon from SiO2 to ZrInZnO and indium from ZrInZnO to SiO2 precisely, SIMS analysis was performed, as shown in Fig. 8. The 131 OIn− ion was selected to eliminate the effect of sputtering and knocking during the SIMS measurement of In+ ions. These data indicate that a rather small diffusion of indium occurred at the interface of the ZrInZnO/SiO2 system. The intensity of the 28 Si+ ion decreased significantly across the ZrInZnO film; however, the influence of knocking and sputtering of Si+ ions could not be eliminated in this measurement. Therefore, further studies will be necessary to clarify this observation. Fig. 9(a) and (b) shows the cross-sectional TEM images of the solution-derived ZrInZnO/SiO2 system. Despite high annealing temperature (500 ◦ C), it was confirmed that the ZrInZnO film remained amorphous [14]. The interface was

smooth, without any voids or defects, which suggests that a good MOS interface could be realized. Fig. 10(a) shows the ID –VG characteristics of five TFTs fabricated using a ZrInZnO precursor solution for the active layer and a polysilazane-based SiO2 solution for the gate insulator. The channel width and length were 60 and 20 μm, respectively. The fabricated TFTs exhibited a low gate leakage current of less than 9 × 10−11 A/cm2 because of the high-quality gate insulator. The saturation mobility (μsat ) was estimated from the slope of (IDS )0.5 versus the gate voltage (VGS ). The threshold voltage was obtained from the intersection of the linear portion of this curve at the x-axis (y = 0). The μsat values of these devices ranged between 19 and 29 cm2 · V−1 · s−1 , and the subthreshold slope ranged between 340 and 660 mV/decade. The threshold voltage ranged from 2.7 to 3 V, and the ION /IOFF ratio was about 1.5 × 107 at a drain voltage of 1.5 V. A discontinuity observed in the range −2 V < VG < 0 V in these transfer characteristics is due to the limitation of our measurement system; definition is 0.1 pA. The ID –VD characteristics of the TFTs measured at various gate voltages (VG ) are shown in Fig. 10(b). Typical n-channel transistor characteristics were obtained. The performance of the TFTs is almost equivalent to that of oxide semiconductor TFTs fabricated by a vacuum process such as the sputtering method [1], [20], [21]. These results indicate that the SiO2 films formed using a polysilazanebased solution are superior in terms of not only the leakage current but also the quality of the MOS interface. IV. C ONCLUSION We have investigated a SiO2 gate insulator fabricated using a polysilazane-based solution for use in all-solution-processed TFTs. The leakage current density of the SiO2 film was 1 × 10−8 A/cm2 at 1 MV/cm, which is sufficient for the gate insulator in TFTs. The leakage current mechanism was discussed, and the Poole–Frenkel current was observed at electric fields greater than 1.2 MV/cm for the SiO2 film annealed at 450 ◦ C. The TFTs using a ZrInZnO solution precursor for the active layer and a polysilazane-based solution for the SiO2 gate insulator were fabricated for the first time and exhibited excellent performance. These are promising results for the realization of all-solution-processed oxide semiconductor TFTs.

TU et al.: INVESTIGATION OF SiO2 GATE INSULATOR FOR OXIDE SEMICONDUCTOR TFTs

ACKNOWLEDGMENT The authors would like to thank Mr. D. Hirose at Japan Advanced Institute of Science and Technology and the researchers of the ERATO Shimoda Nano-Liquid Process Project for their kind support and discussions. R EFERENCES [1] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-temperature fabrication of transparent flexible thin-film transistor using amorphous oxide semiconductor,” Nature, vol. 432, no. 7016, pp. 488–492, Nov. 2004. [2] C. G. Lee and A. Dodabalapur, “Solution-processed zinc–tin oxide thinfilm transistors with low interfacial trap density and improved performance,” Appl. Phys. Lett., vol. 96, no. 24, pp. 243 501-1–243 501-1, Jun. 2010. [3] K.-B. Park, J.-B. Seon, G. H. Kim, M. Yang, B. Koo, H. J. Kim, M.-K. Ryu, and S.-Y. Lee, “High electrical performance of wet-processed indium zinc oxide thin film transistors,” IEEE Electron Device Lett., vol. 31, no. 4, pp. 311–313, Apr. 2010. [4] M.-G. Kim, H. S. Kim, Y.-G. Ha, J. He, M. G. Kanatzidis, A. Facchetti, and T. J. Marks, “High-performance solution-processed amorphous zinc– indium–tin oxide thin-film transistors,” J. Amer. Chem. Soc., vol. 132, no. 30, pp. 10 352–10 364, Aug. 2010. [5] J. S. Park, W.-J. Maeng, H.-S. Kim, and J.-S. Park, “Review of recent developments in amorphous oxide semiconductor thin-film transistor devices,” Thin Solid Films, vol. 520, no. 6, pp. 1679–1693, Jan. 2012. [6] M. Mativenga, M. H. Choi, J. W. Choi, and J. Jang, “Transparent flexible circuits based on amorphous-indium–gallium–zinc–oxide thin-film transistors,” IEEE Electron Device Lett., vol. 32, no. 2, pp. 170–172, Feb. 2011. [7] M. Mativenga, J. K. Um, D. H. Kang, R. Mruthyunjaya, J. H. Chang, G. N. Heiler, T. J. Tredwell, and J. Jang, “Edge effects in bottom-gate inverted staggered thin-film transistors,” IEEE Trans. Electron Devices, vol. 59, no. 2, pp. 2501–2506, Sep. 2012. [8] E. Fortunato, P. Barquinha, and R. Martins, “Oxide semiconductor thinfilm transistors: A review of recent advances,” Adv. Mater., vol. 24, no. 22, pp. 2945–2986, Jun. 2012. [9] I. Yudasaka, H. Tanaka, M. Miyasaka, S. Inoue, and T. Shimoda, “Poly-Si thin-film transistors using polysilazane-based spin-on glass for all dielectric layers,” SID Int. Symp. Dig. Tech. Papers, vol. 35, no. 1, pp. 964–967, May 2004. [10] J. L. Yeh and S. C. Lee, “Amorphous-silicon thin-film transistor with liquid phase deposition of silicon dioxide gate insulator,” IEEE Electron Device Lett., vol. 20, no. 3, pp. 138–139, Mar. 1999. [11] H. Kozuka, M. Fujita, and S. Tamoto, “Polysilazane as the source of silica: The formation of dense silica coatings at room temperature and the new route to organic–inorganic hybrids,” J. Sol-Gel Sci. Technol., vol. 48, no. 1/2, pp. 148–155, Nov. 2008. [12] K. Kamiya, T. Tange, T. Hashimoto, H. Nasu, and Y. Shimuzu, “Formation process of silica glass thin films from perhydropolysilanze,” Res. Rep. Faculty Eng. Mie Univ., vol. 26, no. 12, pp. 23–31, Dec. 2001. [13] H. Xie, J. Wei, and X. Zhang, “Characterisation of sol-gel thin films by spectroscopic ellipsometry,” J. Phys., Conf. Ser., vol. 28, no. 1, pp. 95–99, 2006. [14] P. T. Tue, T. Miyasako, J. Li, H. T. C. Tu, S. Inoue, E. Tokumitsu, and T. Shimoda, “High-performance solution-processed ZrInZnO thin-film transistors,” IEEE Trans. Electron Devices, vol. 60, no. 1, pp. 320–326, Jan. 2013.

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Huynh Thi Cam Tu received the M.S. degree in materials science and technology from Japan Advanced Institute of Science and Technology, Nomi, Japan, in 2012, where she is currently working toward the Ph.D. degree in the School of Materials Science.

Satoshi Inoue received the Ph.D. degree from Tokyo University of Agriculture and Technology, Fuchu, Japan. He is currently a Research Professor with the Green Devices Research Center, Japan Advanced Institute of Science and Technology, Nomi, Japan.

Phan Trong Tue received the Ph.D. degree in materials science and technology from Japan Advanced Institute of Science and Technology (JAIST), Nomi, Japan, in 2011. Since April 2012, he has been with the Green Devices Research Center, JAIST.

Takaaki Miyasako received the Ph.D. degree from the Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Meguro, Japan, in 2012. Since April 2012, he has been with Yokkaichi Research Center, JSR Corporation, Yokkaichi, Japan.

Tatsuya Shimoda received the B.S. and Ph.D. degrees from The University of Tokyo, Bunkyo, Japan, in 1977 and 1985, respectively. He is currently a Director and a Professor with the Japan Advanced Institute of Science and Technology, Nomi, Japan.