LC oscillator design at 10-GHz using substrate capacitance with scalable varactor parameters extraction technique T.Hui Teo1,2 , Yong-Zhong Xiong1 , Jeffrey Shiang Fu2 , Eng Leong Tan2 1
Institute of Microelectronics, 11 Science Park Road, Singapore Science Park-II, Singapore 117685. Telephone:(65)6770-5323, Fax:(65)6774-5754, Email:
[email protected] 2 School of Electrical and Electronics Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798.
Abstract— Design of quadrature oscillator at 10-GHz is demonstrated, which involved development of direct parameter extraction technique of scalable varactor. The varactor is used in the tank circuit. The effects of the substrate parasitic of SiGe in quadrature LC oscillator design was also investigated. Exploiting the substrate effect and accurate device characterization, a quadrature oscillator with -106-dB phase noise at 1-MHz offset using 2.50-V single supply was measured. The core oscillator consumes only 1.6-mA each at 10-GHz.
I. I NTRODUCTION Quadrature oscillator is found to be one of the important components in clock recovery circuit in optical devices [1], [2], [3], [4], [5], [6]. In this application, the oscillator does not require wide tuning range as voltage-control-oscillator (VCO) in frequency synthesizer. However, due to the process variation and parasitic effects, designing an oscillator to oscillate at desired frequency become a challenge in both process control and device modeling. To minimize the design error, devices contribute to the oscillation should be carefully characterized and included in the design phase. At 10-GHz, device with less parasitics effect is preferred. Hence, SiGe is widely adopted in these frequency range due to its high frequency capability. The substrate parasitic at collector, which is the output port becomes important in these frequencies. Accurate extraction of the substrate network has been reported in [7], and the result was adopted here in the design of 10-GHz LC oscillator. In the design of the oscillator, varactor value of less than 0.50-pF is required. However, characterization of varactor with such low value is problematic and easily affected by the measurement setup. The model is not always available. In this work, we have to estimate the varactor value from the measured data. A direct extraction technique for scalable varactor was developed and demonstrated here. This paper is organized as follow. Section II gives basic analysis of the design of quadrature oscillator. Section III deals with the direct parameter extraction of the varactor. This is followed by measurement results in Section IV. Finally, the conclusion is given in Section V. II. A NALYSIS Fig. 1(a) shows the block diagram of the quadrature oscillator, [8]. VoI and VoQ are quadrature oscillation signals. The corresponding schematic of the VCO is depicted in Fig. 1(b). Two VCOs are required to generate π2 phase difference. Similarly, n VCO is used to generate nπ phase difference. Hence, the circuitries of the quadrature VCO is at least doubled compare to single VCO. In this case, power consumption should be optimized.
Based on the LC oscillator design considerations proposed in [9], [10], larger inductance is required to minimize the power consumption. This however reduces the tuning range. Symmetrical spiral inductor was adopted for its higher quality factor and area efficiency [10]. Its center is connected to Vs , which is the supply voltage, Fig. 1(b). Vs dc couples to the collector of the n-p-n devices and the cathode of the pnjunction varactors. In this case, the substrate parasitics at the collector should be carefully considered. This is because the parasitic capacitances are part of the tank circuit, as follow, fvco (V )
=
2·π
1 . L · (Cpn (V ) + Cp )
(1)
where L, and Cpn (V ) are the inductance of spiral inductor and the pn-junction capacitance respectively. Cp simply represents the parasitic capacitances. Bias currents for VCO core and input device, I1 and I2 were optimized for phase noise, [6]. Although, the bias currents can also be used to tune the oscillation frequency, it was fixed in this work to validate the substrate effect. III. C APACITANCE S CALING There are three types of RF (radio frequency) capacitor available in this process; MIM (metal-insulator-metal), pnjunction, and accumulation-MOS. A generic equivalent circuit for the RF capacitor consists of series of capacitor, resistor and inductor, as well as the substrate network, Fig. 3, [11]. The capacitances of these capacitors are different functions of the applied voltage. Port-1 and port-2 represents the top plate and bottom plate of the capacitor respectively. The design of the capacitor should minimize the substrate effect at the bottom plate. Thus a simple substrate network is adequate. The MIM capacitor is independent of the voltage variation, and thus is not tunable. The pn-junction capacitor in its reverse biased condition is described by the depletion capacitance as, Cpn
=
1−
Cjpn0 mjpn Vjpn φjpn
(2)
where Cjpn0 , is the junction capacitance at zero bias, Vjpn , is the applied reverse voltage, φjpn is the junction built-in voltage, and mjpn is the exponent. The accumulation-MOS capacitor has two modes of operation, accumulation and depletion modes. Its capacitance can be described empirically as, [12], Vjm − Vm0 (3) Cm = Cm0 + Cm1 · tanh Vm1
Ca
La
Ra
1 Vq+
Vd+ VCO 1
Vd−
Vd+
Vq+
VCO 2
Vq−
Vd−
Vo− Vo+
Cc
Vq−
Vo− Vo+
Rc
VoQ
VoI
Fig. 3.
(a)
General equivalent circuit for RF capacitor.
A. Extraction of Equivalent Circuit
Vs
Vt Vb Vq+
Vq−
Vo−
Vo+
Vd−
Vd+
I1
I2
(b) Fig. 1. Quadrature oscillator, (a) Block diagram, (b) Oscillator core schematic
Fig. 2.
2
Microphotograph of the quadrature oscillator
where Cm0 , Cm1 , are the capacitance at applied voltages, Vm0 , Vm1 respectively, and Vjm , is the applied voltage. These parameters are directly extracted from the measured data. It is scalable and related to its physical characteristics. The expression can be implemented with Verilog-A for circuit simulation, since it is widely supported by the simulator such as, SPECTRE by Cadence, Advanced Design System by Agilent. Verilog-A has the advantage of fast and easy implementation compared with other models, [13], [14], [15], [16].
The circuit elements values are extracted directly from the measured S-parameters. At different bias voltages, the voltage dependent circuit elements values are different also. Direct extraction technique should be employed to accurately estimate the voltage dependent values. Higher accuracy of the extracted values will ease the fitting process to get the transfer functions in (2), and (3). The extraction technique is described here. The impedance of the series components in Fig. 3 can be described by, 1 ), (4) Za = Ra + j(ωLa − ωCa 1 ). (5) Zc = Rc − j( ωCc The imaginary part of (4) is rearranged as, 1 imag(Za )ω = ω 2 La − , (6) Ca 1 1 1 = − + La . (7) imag(Za ) ω Ca ω 2 By plotting imag(Za )ω versus ω, La can be estimated from its gradient. The same approach applies to obtain Ca from plot imag(Za ) ω1 versus ω12 . Ra is simply estimated from the real part of (4). This technique is more accurate and widerband than the extraction method described in [16], where La is calculated at only a single frequency point. Rc and Cc can also be extracted from the real and imaginary parts of (5). Fig. 4 illustrates the extraction techniques described here. The gradients in Fig. 4(b) indicates the capacitance variations. These gradients were extracted and plotted versus their applied voltages. The results were shown in Fig. 5(a) and Fig. 5(b) for pn-junction and accumulation-MOS varactor. Fig. 5 shows the measured capacitances as a function of the applied voltages. Note that the measured data fits nicely with the simulated transfer functions. These transfer functions can be described in term of the number of fingers, n, and are thus scalable. The transfer functions were obtained empirically by substituting (8),(9) into (2),(3) respectively. Cjpn0 = (5.642n − 2.705) × 10−14 mjpn = 0.242 φjpn = 0.663 Cm0 = (2.924n + 6.413) × 10−14 Cm1 = (1.759n + 3.340) × 10−14 Vm0 = −0.110 Vm1 = 0.350
(8)
(9)
2
Nf104 Nf78 Nf51 Nf26 Transfer Function
6.00
0
5.00 Capacitance [pF]
imag(Za)ω [1011 Ω rad]
5.50
-2 -4 -6
1
2
3.50 3.00 2.50 2.00 1.00
-10 0
4.00
1.50
Vjm increases (-1.60V to 1.00V)
-8
4.50
3
0.50 -3.50
4
-3.00
ω2 [1021 rad2]
-2.50 -2.00 -1.50 -1.00 Applied Voltage, Vjpn [V]
(a)
0.00
(a)
5
5.50 5.00
0
4.50 -5
Capacitance [pF]
imag(Za)ω-1 [10-8 Ω rad-1]
-0.50
-10 -15 -20 -25
Vjm increases (-1.60V to 1.00V)
-30 1
2
3
3.50 3.00 2.50 2.00 1.50 1.00 0.50
-35 0
4.00
Nf104 Nf78 Nf51 Nf26 Transfer Function
4
ω-2 [10-19 rad-2]
0.00 -2.00
-1.50
-1.00 -0.50 0.00 Applied Voltage, Vjm [V]
0.50
1.00
(b)
(b)
Fig. 4. Illustration of capacitor network extraction, (a) La , (b) Ca , using a-MOS capacitor with number of fingers, Nf=104
Fig. 5. Capacitor transfer function, (a) Cpn , (b) Cm , for different number of fingers
IV. E XPERIMENTAL R ESULTS
the pulling effect. In this work, 2.50-V supply voltage has been found suitable for the 10-GHz application. The oscillation frequency of the oscillator as a function of the supply voltage was measured, Fig. 7(b). In this measurement, the voltage across the pn-junction varactor was fixed. Thus, the variation is merely due to the substrate capacitance at the collector.
The oscillator was designed and fabricated using SiGe with 0.18-µm CMOS baseline. The schematic is depicted in Fig. 1. Fig. 2 shows the microphotograph of the quadrature oscillator including on-chip buffer. For the core circuit, each n-p-n device has an emitter area of 0.30×20.00-µm2 . Pn-junction varactor with 8 fingers was used. For each finger the area of the anode is 2×15-µm2 . The characteristics of the pnjunction varactor were estimated from the extraction results in Section III. The performance of the oscillator was measured with Rohde & Schwarz signal analyzer, FSQ26 equipped with phase noise measurement capability. The output spectrum of the oscillator at 2.50-V and 3.00-V supply voltages are shown in Fig. 6(a) and Fig. 6(b) respectively. As expected, the oscillator with higher supply voltage has better phase noise performance. It is about 6-dB improvement with 3.00-V compare to 2.50-V supply voltage at 1-MHz offset frequency. The tuning profile of the oscillator at different supply voltages was also measured, Fig. 7(a). The supply voltage can be incorporated in the oscillator design for tuning purpose. In this case, local regulated supply voltage to the oscillator should be employed, which is a common practice to suppress
V. C ONCLUSION The substrate effect of the n-p-n SiGe device was investigated and incorporated into the 10-GHz LC oscillator design. In the design of the oscillator, a direct extraction technique was also developed to help the design engineer to build a scalable varactor library. This technique is practically useful when the given data does not include the desired values. Using these design techniques, a low phase noise and low power oscillator at 10-GHz was implemented. ACKNOWLEDGEMENT The authors would like to thank engineers from Integrated Circuit and System Laboratory, Institute of Microelectronic, for various technical discussion.
−10.0
10.60
Center at 10.3269GHz
−20.0
10.50
−40.0 −50.0 −105.85dBc/Hz @1.0MHz
−60.0 −70.0 2
−80.0 −90.0
Frequency, (GHz)
Amplitude, (dBm)
−30.0
10.40 10.30 10.20 10.10 10.00
−90
9.90
Vs=2.50V Vs=3.00V Vs=3.30V
−100.0 9.80
−110.0 −4.0 −3.0 −2.0 −1.0 0.0 1.0 2.0 3.0 4.0
0.00
0.50
Offset Frequency, (MHz)
−10.0
Center at 10.4929GHz
10.45
−40.0 −50.0
−111.11dBc/Hz @1.0MHz
−60.0 −70.0 −80.0
Frequency, (GHz)
Amplitude, (dBm)
3.50
10.50
−30.0
−90.0
3.00
(a)
(a)
−20.0
1.00 1.50 2.00 2.50 Control Voltage, (V)
10.40 10.35 10.30 10.25 10.20
−90
10.15
−100.0 −110.0 −4.0 −3.0 −2.0 −1.0 0.0 1.0 2.0 3.0 4.0 Offset Frequency, (MHz)
10.10 2.20
2.40
2.60 2.80 3.00 3.20 Supply Voltage, (V)
3.40
3.60
(b)
(b)
Fig. 6. Buffered output spectrum at different supply voltages, (a) Vs =2.50-V, (b) Vs =3.00-V
Fig. 7. Measured VCO tuning profile, (a) function of control voltage, Vt at different supply voltages, Vs , (b) function of supply voltages, Vs , by fixing Vd =2.00-V (Vd =Vs − Vt )
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