A Design Guide for Reducing Substrate Noise Coupling ... - IEEE Xplore

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CHIP A Design Guide for Reducing Substrate Noise Coupling in RF Applications Ahmed Helmy and Mohammed Ismail his article discusses a set of design guidelines to reduce the on-chip substrate noise coupling in RF and mixed signal applications. Measurement data is presented to compare the various signal isolation techniques. A design flow is calibrated to the measured data and is used to expand the design guide to include the effects of the geometrical and electrical parameters of the isolation structures as well as the frequency of operation on the isolation level. A set of guidelines is presented to the reader as a summary of the studied experiments.

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BACKGROUND Signal isolation, especially between the digital and analog regions of the chip, is an increasing challenge for deep submicron technologies due to the increased integration complexity. Noise coupling may occur through the power supply lines, ground rails, and common silicon substrate. The difficulty of integrating analog and highspeed digital functions on a single chip increases with scaling in both device geometry and supply voltage. Signal isolation is critical for the success of cointegrating high-performance analog circuits and highly complex digital signal processing functions on the same die or substrate. Such cointegration is driven by the growth in many modern communication systems and personal mobile computers to reduce size, power, and cost and present to the end user a single chip solution. In such an environment, noise disturbances generated by high switching IEEE CIRCUITS & DEVICES MAGAZINE

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SEPTEMBER/OCTOBER 2006

rates of digital circuits and the presence of strong interference signals between tightly coupled channels can propagate through the common silicon substrate due to the finite conductivity and permitivity of the substrate material and couple to circuits located in different parts of the substrate. Figure 1 shows the substrate noise coupling phenomena at a glance. Coupling occurs between a noise transmitter, which in most cases, is a fast switching digital block, and a noise receiver, which in most cases, is a sensitive analog or RF block. Coupling takes place due to the capacitive and resistive nature of the substrate-device interface. The disturbances may, in many cases, be significant enough to degrade the performance of the sensitive analog and RF circuits sharing the same substrate with the digital blocks. Certain types of circuits have traditionally been built on separate substrates in order to minimize noise coupling between them. For example, low-noise amplifiers and switching circuits such as dividers and high-power circuits are traditionally built on separate substrates. Then a system in package (SIP) is designed to build a single chip module to be presented to the end user as a single package solution for integration on the system board. Such a process, although beneficial in many cases, adds a huge overhead to the design, validation, and testing resources. Higher levels of integration have several associated advantages and disadvantages. Obvious advantages are the reduced package count and die area. 8755-3996/06/$20.00 ©2006 IEEE

This leads to lowered costs and reduced sizes. The power dissipation can also be reduced as fewer pads and interconnect lines need to be driven, thereby avoiding the associated capacitance and parasitic self and mutual inductances. It may be possible to improve the highfrequency response of the circuits or even extend the frequency range of the circuits’ performance, as the package parasitics often degrade the frequency response at the high-frequency end of the application [1]. A major disadvantage of integration is the increased interaction between circuits. This interaction can appear in two major ways. It can occur due to the significant mutual inductance and capacitance, which exist between any two bond wires and pins in a package. The second method for interaction is through the common substrate shared by the circuits. Integrating high-power switching noise generating circuits and sensitive low-noise circuits on the same substrate while avoiding performance degradation due to substrate coupling is currently being viewed as a major challenge by circuit and system designers.

TRANSMISSION MEDIUM Substrates act as the transmission media for coupling the noise from one device to another placed on the shared substrate. The nature of the substrate as a transmission medium and the process technology parameters that affect its behavior is given as a function of the frequency of operation by referring to Maxwell’s equations and its derivates 7■

Noise Transmitter

[2], [3]. The current in the substrate can be given by Maxwell’s equation as

Noise Receiver

J = (σ + jωεSi )E, P-well

N+

N+

N+

N+

I_noise I_noise

P-sub

Backplane

Lbp

1. Substrate noise coupling at a glance.

Cutoff Freq Versus Substrate Resistivity 80 Cutoff Freq Versus Substrate Resistivity

Cutoff Freq fc (GHz)

70 60

where J is the current density in the substrate (A/cm2 ); E is the electric field (V/cm), which drives this current density; σ is the conductivity (S/cm); εsi is the dielectric permittivity of silicon (εo 8.854e-14 * εr 11.7 F/cm); and ω is the frequency in rad/s. The substrate impedance and the behavior of the substrate as a noise transmission medium are frequency dependent. As long as σ ωεSi , the current in the substrate will be dominated by its resistive nature. At low frequencies, dielectric capacitive behavior of the substrate is insignificant, and hence, it can be considered merely as a resistive medium. This assumption is valid below a certain cutoff frequency fc [4].

50

fc = 1/(2πρsub εsi ),

40 30 20 10 0 0

10

20 30 Substrate Resistivity (Ω-cm)

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2. Frequency (fc) below which substrate is purely resistive.

Study Model File to Accurately Define SubstrateDevice Interface Runset Integration for LVS and PEX

Layout Data GDS Layout Parasitics

Process Information Substrate Stack Info Doping Profile Junction Cap Values

Package Model Schematic Data

Substrate Model Extraction Kemel (Finite Difference Method)

Substrate RC Model

h

enc

tB Tes

Circuit Simulator

3. The design flow used to characterize substrate noise coupling. ■8

(1)

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(2)

where ρsub is the substrate resistivity (1/σ ). Figure 2 shows a plot of the substrate resistivity as a function of the frequency at which σ = ωεSi called the cutoff frequency fc . For ρsub = 10 -cm, the substrate can be considered as a resistive medium below 15 GHz. Thus, for most of the RF and mixed signal applications, the substrate medium can be treated as a resistive medium—the higher the conductivity the higher the frequency up to which the substrate can be treated as purely resistive. Above this frequency, the capacitive term starts to kick in and the model of the substrate becomes a mesh of Rs and Cs [5]. The current density J = σ E considers only the current due to the drift of the majority carriers by the electric field below the cutoff frequency. Minority carriers current are not considered, since they are diffusion driven and can complicate the model. Minority carriers, once injected into the substrate, can exist for long periods of time (carrier lifetime) and cause significant local variations in conductivity. However, a large injection of minority carriers into the substrate usually indicates a fault bias condition as what will occur when a device to substrate IEEE CIRCUITS & DEVICES MAGAZINE

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junction is turned on. Thus, under proper operating and bias conditions, the above model is considered to be valid.

THE DESIGN FLOW The design flow adopted for simulating the substrate noise coupling is summarized in Figure 3. It starts by defining the device-substrate interface and integrating this in the rule files used for layout versus schematic check and layout parasitic extraction. The rule files decide based on the substrate-device interface what to include in the substrate model and what to leave behind as part of device models. The layout data is used to identify the geometries, interconnectivity, and location of the devices and the substrate isolation structures that are designed. The process stack information and doping profile are other inputs to the solver. The above-mentioned inputs are fed to the substrate model extraction kernel [6]–[8]. A commercially available tool that represents the industry standard is used as the extraction kernel [9]. To calibrate this design environment, a test chip is designed and measured to compare silicon measurements to the simulation results and ensure that the design environment used is accurately predicting silicon behavior. Once this calibration is done, the use of the design environment, substrate model extraction, and simulations will be extended to other isolation structures to come up with a design guide for substrate noise isolation using substrate isolation structures, floor planning, and circuit design techniques.

the process technology features used for isolation, while different sizes and geometries are deferred to be simulated using the calibrated design flow. A gold ohmic contact was made to the back surface of the die and was connected to the measurement system ground during the testing. The different isolation techniques are discussed in the next sections.

BASELINE ISOLATION The layout used for the baseline isolation is shown in Figure 4. The ground G pads are tapped to the substrate and connected to the measurement system ground. The G pads are connected together in both X and Y directions to 70 µm

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100 µm Rec

S Rec

G

G

P+

P-well

25 µm

P-sub

G G

120 µm

Trans

G

P+

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25 µm

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G

G 100 µm

4. Structure used to measure and simulate baseline isolation.

Baseline Isolation −20 −21

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THE TEST CHIP

Basline_simulation

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A test chip is designed and measured to assess the impact of the different substrate isolation techniques on the substrate noise coupling. The substrate isolation characterization is performed on a high-resistive substrate of 10 -cm. The test chip used for this characterization contained various substrate crosstalk reduction structures. The purpose of this test chip is to calibrate the design flow used to model the substrate to silicon data. A limited set of structures are designed and measured that scans

form an equipotential surface that ensures accurate measurements. Without such connection, the measurements will be too noisy. The feed lines connect the receiver and the transmitter to the signal S pads. The resistance of the feed lines and their vias together with the parasitic pad capacitance are deembedded to get the isolation information of the receiver and transmitter only. Two port single-ended S-parameter measurements are done, and the isolation S12 in dB versus frequency after deembedding is shown in Figure 5. The simulation result is overlaid on the measurement in Figure 5. The S12 values are based on a setup where port 1 is the receiver while

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Freq (GHz) 5. Measurement versus simulation for baseline isolation. 9■

port 2 is the transmitter. Both the receiver and the transmitter are p+ diffusion regions in a p-well substrate, thus they both have ohmic contacts to the substrate. Since the substrate has a resistivity of 10 -cm it will behave as a resistive network up to the cutoff frequency. Thus, the equivalent model between the receiver and the transmitter is all resistive, and the S12 data looks pretty much constant up to ∼15 GHz, as expected from an all-resistive mesh. Beyond this frequency, the isolation behavior starts to depart from a resistive behavior, and it starts to decrease with increasing the frequency due to the contribution of the distributed RC network that represents the substrate beyond the cutoff frequency.

70 µm 10 µm

3 µm Rec

S Rec

G

G

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P+ 25 µm

G

120 µm

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P-sub

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S Trans

G

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25 µm

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G 100 µm 6. p+ guard ring structure.

Case B

S Rec

G

P+ GUARD RING ISOLATION

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120 µm

S Rec

G

G

zsh

G

120 µm

zgnd

zgnd zsh S Trans

G

S Trans

G

G

G

(b)

(a)

7. Guard ring different grounding schemes.

p Guard Ring Isolation

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S12_meas_ring at receiver S12_sim_ring at receiver S21_meas_ring at transmitter S21_sim_ring at transmitter

S12 (dB)

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Freq (GHz) 8. Measurement versus simulation for p+ guard ring isolation. ■ 10

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A p+ guard ring surrounding the noise receiver is shown in Figure 6. The guard ring is connected to the ground pads using a low-ohmic contact connection. This ground connection is needed for the ring to act as a sink to the substrate noise currents. The layout is also used to serve the purpose of measuring the substrate isolation if the guard ring surrounds the transmitter. This is achieved by also monitoring S21 in addition to S12, i.e., flipping the roles of the noise transmitter and noise receiver. Adding a second guard ring to simultaneously surround both the transmitter and the receiver can be dangerous. The reason is that both guard rings have to be grounded to sink the substrate noise currents and if they are both tied to the same ground node, this can create a short circuit path to the substrate noise current as shown in Figure 7(a). If ZshZgnd, adding a guard ring around the transmitter will increase noise coupling to the receiver. If, on the other hand, the two guard rings are tied to two separate ground nodes, isolation is enhanced. Figure 8 shows the measurement and simulation results of the above-mentioned scenarios. Figure 9 shows the simulation results comparing the different ground connections with guard ring inductance set to 1 nH. The isolation provided by the p+ guard ring is IEEE CIRCUITS & DEVICES MAGAZINE

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p Guard Ring Isolation


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S12_P_guard_at_rec_only S21_P_guard_at_trans_only S12_CaseB S12_CaseA

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Freq (GHz) 9. Simulation results for the different grounding schemes of the p+ guard ring.

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N+ GUARD RING ISOLATION The layout of the structure is shown in Figure 10. Two n+ guard rings are placed around the receiver and the transmitter. Two dc pads are needed to bias the n+ guard rings to dc supplies to create reverse bias p-n junctions between the n rings and the p substrate. The structure can be used to measure the impact of a single n ring around the receiver by keeping the n ring around the transmitter floating and connecting that around the receiver to vdd1, which will act as an ac

error between measurement and simulation. Figure 13 compares the p+ ring and the n+ ring isolation values in all of their configurations. The p-n junction between the n guard ring and the p substrate introduces high-capacitive impedance at low frequency. This high impedance prevents substrate noise currents from reaching the receiver. This is shown in Figure 11 by the dip in the isolation at frequencies below 1 GHz. Beyond this frequency, this impedance becomes smaller in comparison to the substrate resistive network, thus the isolation remains almost constant up to the cutoff frequency. Beyond this frequency the isolation is degraded as frequency increases due to the capacitive nature of

ground to sink the substrate noise current. It is also used to measure the impact of a single n ring around the transmitter by keeping the n ring around the receiver floating and connecting that around the transmitter to vdd2. If both n rings are simultaneously connected to vdd1 and vdd2 respectively, the impact of two rings, one surrounding the receiver and one surrounding the transmitter, is measured and compared to the above-mentioned two cases. Figure 11 shows the measurement data for the three cases. Figure 12 shows the simulation results overlaid on the measured data. A good fit is obtained between measurement and simulation up to the cutoff frequency, then a deviation occurs within 2 dB

S12 (dB)

superior to the baseline isolation by approximately 30 dB. The p+ guard ring can effectively eliminate the surface noise current flow (which is the dominant noise current component in high-resistive substrates if compared to the bulk component that is dominant in low-resistive substrates [10]) by sinking this noise current to the lowohmic ground connection. Since p+ guard ring acts as a resistive network due to its ohmic contact to the substrate and the substrate behavior is resistive up to the cutoff frequency, the isolation is constant within 2 dB up to 15 GHz, then it starts to degrade with frequency due to the capacitive behavior of the substrate beyond the cutoff frequency. Comparing the scattering parameters shown in Figure 8, we notice that adding p+ guard ring to surround the noisy circuit block transmitter is a more efficient technique to reduce substrate crosstalk. The isolation in this case is larger than the case of the p+ guard ring surrounding the receiver by ∼2.5 dB. Putting the p+ guard ring around the noisy circuit is more capable of sinking the substrate current before it propagates to other locations in the substrate. Also, the impedance of the guard ring connection to ground can pick up noise, and putting the guard ring around the receiver may degrade the isolation, while putting it around the transmitter leaves room for the residual noise that is not sunk to ground due to the presence of this impedance to be attenuated by the distance isolation in the highresistive substrate.

Vdd1

G 100 µm

S Rec

10 µm 3 µm

G

N+

vdd1 Rec

P+ 25 µm

N+

P-well

P-sub

N-well

N+

P+ 25 µm

Vdd2

G

S Trans

vdd2

Trans

120 µm

N+

P-well

P-sub

G

10. n+ guard ring isolation structure. 11 ■

n Guard Ring Isolation

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One n Guard Ring at Rec Meas Two n Guard Rings Meas One n Guard Ring at Trans Meas

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Freq (GHz) 11. Measurement data for n+ guard ring isolation.

n Guard Ring Isolation −60 −65

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One n Guard Ring at Rec Meas One n Guard Ring at Rec Sim Two n Guard Rings Meas Two n Guard Rings Sim One n Guard Ring at Trans Meas One n Guard Ring at Trans Sim

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Freq (GHz) 12. Measurement versus simulation for n+ guard rings.

Comparing Isolation Techniques

p Guard Ring at Rec One n Guard Ring at Rec p Guard Ring at Trans One n Guard Ring at Trans

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DEEP N-WELL ISOLATION

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Freq (GHz) 13. Comparison between the isolation of p and n rings. ■ 12

the substrate behavior that kicks in beyond the cutoff frequency. The cutoff frequency in this case is larger than the case of the p guard ring due to the fact that the conductivity of the n guard ring is larger than that of the p guard ring. As shown in Figure 11, putting the n guard ring around the transmitter is a more efficient isolation technique. Isolation is increased by approximately 2.5 dB if compared to the isolation of the n guard ring placed around the receiver. This conclusion is similar to what was concluded for placing the p+ guard rings around the receiver and transmitter in the previous section. Adding two n guard rings around both the transmitter and the receiver provides 5 dB more isolation if compared to the isolation of a single guard ring placed around the transmitter only and 7.5 dB if compared to the isolation of a single guard ring placed around the receiver only, provided that the ac ground of the n guard rings are separate. The simulation results shown in Figure 12 track the above-mentioned behavior accurately. In Figure 13, the p guard ring is compared to the n guard ring. The nwell guard ring contact provides higher isolation than p+ guard ring contact especially at low frequency due to the impedance of the junction capacitance at low frequency. At higher frequencies, it still provides better isolation due to its lower sheet resistivity. For the same doping concentration, the n guard ring is ∼2X less resistive due to the fact that the electron mobility in the n guard ring is larger than the hole mobility in the p guard ring.

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The effect of a deep n-well guard ring is compared to the n+ guard ring. Figure 14 shows the layout of the structure. A p+ diffusion representing the receiver is placed in a p-well that is isolated from the common p-substrate by a deep n-well implant. An n-well guard ring surrounds the receiver and is put on top of the deep n-well tub. An n+ diffusion is implanted and contacted in the n-well guard ring and connected via low-resistive metal routing to the dc pad to bias the n-well. The IEEE CIRCUITS & DEVICES MAGAZINE

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vdd1

70 µm

Vdd1

100 µm

10 µm 3 µm

S Rec

G

G

Rec

P+

N+

N+

25 µm

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N-well 120 µm

vdd2 10 µm

N+

Vdd2

S Trans

G

G

Trans

P+

N+

25 µm

P-well Deep N-well P-sub

N-well 14. Deep n-well guard ring isolation structure.


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Deep n-well Isolation −60

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Deep n-Well Isolation Meas Deep n-Well Isolation Sim

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Freq (GHz) 15. Measurement versus simulation for deep n-well guard rings.

Comparing Isolation Techniques −60 −65 −70

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transmitter layout is identical to the receiver, except for the dc pad that is connected to a separate supply. Figure 15 shows the measurement results of the isolation versus frequency. The simulation result of the isolation is overlaid on the measurement data. Figure 16 shows the measurement results comparing the isolation of the n guard ring to the isolation of the deep n-well guard ring, the comparison is performed for the case of two guard rings simultaneously surrounding the receiver and the transmitter with the rings tied to separate supplies. The deep n-well acts as a low-resistive current sink that is buried in the substrate. This will provide a sink to deep substrate noise currents and will extend the effect of the current sink from the surface to a deeper distance in the substrate. Such design will enhance the isolation if compared to the regular n-well ring that only provides current sink to surface currents. The substrate noise current is now forced to dive deeper in the substrate to reach the receiver, such deep path has more impedance due to the high-resistive nature of the substrate Figure 16 shows at least 5 dB of isolation enhancement of the deep n-well guard ring over the n guard ring. Since the resistivity of the deep n-well is less than the p substrate, its cutoff frequency is pushed beyond the 15 GHz and the isolation remains more constant than the case of p guard

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Two Deep n Well Guard Rings Two n Guard Rings

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Freq (GHz) 16. Comparing deep n-well and n-well isolation. 13 ■

rings. Figure 16 shows that the low-frequency behavior of the deep n-well is different than that of the n-well. The deep n-well isolation is better at low frequency and it degrades with increasing the frequency slower than the n-well. The reason is due to the fact that the deep n-well is more lightly doped than the regular n+ well and hence the capacitance of its p-n junction with the p substrate is smaller than that of the n+ well. Being less capacitive increases the capacitive impedance of the p-n junction and hence it takes a higher frequency for this impedance to vanish relative to the substrate resistive network. Beyond this frequency the dip in the isolation vanishes and the isolation reaches its plateau value. The previous design guidelines can be summarized as follows: Design Guide 1: Baseline isolation (isolation between ohmic contacts to the substrate in the absence of any isolation structure) is constant with frequency up to the cutoff frequency. Beyond the cutoff frequency, the isolation degrades with frequency. Selection of the resistivity of the process technology low enough to ensure a high-cutoff frequency and high enough to ensure low-substrate eddy current loss is recommended. Design Guide 2: A p+ guard ring with low impedance to ground surrounding the noise receiver provides better isola-

tion if compared to the baseline isolation at all frequencies. The guard ring acts as a current sink to the surface noise current which are the dominant noise currents in high-resistive substrates. The bulk impedance is high, thus forcing noise currents to the surface. Design Guide 3: Isolation due to p+ guard rings is constant with frequency for noise receivers and transmitters that are contacting the substrate via ohmic contact, up to the cutoff frequency. The frequency dependency is not as constant if compared to the baseline isolation due to the fact that the impedance of the guard ring connection to ground increases with frequency hence it weakens the current sinking capability of the guard ring as frequency increases. Design Guide 4: Placing the guard ring around the noise transmitter is a more effective isolation technique than placing it around the noise receiver. Design Guide 5: n+ guard rings provide better isolation than p+ guard rings specially at low frequency due to the capacitive nature of the p-n junction that provides high impedance to noise currents at low frequency. As frequency increases the isolation of the n+ ring approaches that of the p+ ring, but still remains better due to the lower resistivity of the n+ ring which acts as a better sink if compared to the p+ ring of the same geometry at the same frequency of operation.

Basline Isolation Versus Distance for Resistive Coupling

f=1 GHz, Lbp=0.1nH f=1 GHz, Lbp=2nH f=10 GHz, Lbp=0.1nH f=10 GHz, Lbp=2nH f=1 GHz, no bp f=10 GHz, no bp

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Distance (µm) 17. Effect of backplane impedance on isolation. ■ 14

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Design Guide 6: Placing two n+ rings to surround the noise receiver and transmitter provides better isolation than a single ring, as long as the two rings are connected to separate supply lines. Tying both rings to the same ground degrades isolation. Design Guide 7: As the frequency increases and the guard ring impedance to ground increases, the current sinking capability of the ring vanishes and the isolation approaches the baseline isolation. Thus, it is crucial to ground the substrate isolation structure using very low impedance connections to keep their effect up to the frequency of interest. Design Guide 8: A deep n-well n+ guard ring provides more isolation if compared to the n+ guard ring and has a better isolation versus frequency. Deep n-well forces the noise current to penetrate deeper in the substrate where it faces high impedance. Also, the low-frequency isolation is superior to the n+ guard ring because the deep n-well is lightly doped than the n-well and hence its capacitance to substrate is lower, thus its impedance is higher and the isolation degrades slower with frequency.

BACKPLANE CONNECTION The isolation between two surface contacts in a high-resistive substrate is simulated with and without BP contact to study the impact of grounding the BP on the noise isolation. Figure 1 shows the simulated structure, except that the contact to substrate is ohmic p+ implants. The parameters varied in the simulation are: The frequency is set to 1 GHz and 10 GHz. The BP inductance is set to 0.1 nH and 2 nH. The distance between the contacts is varied from 10 µm to 400 µm. Figure 17 shows the simulation results for the case with no BP, i.e., floating the BP of the wafer, and it shows four plots with different frequencies and BP inductances. Examining the simulation results in Figure 17, the following design guides can be extracted. Design Guide 9: grounding the BP of the high-resistive substrate provides ∼5 dB more isolation at small distances (low bulk current) and ∼10 dB more isolation at large distances (higher bulk current) if compared to the floating BP IEEE CIRCUITS & DEVICES MAGAZINE

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tions to see the impact of D, d, w, LGR , freq, and ρ on the isolation and to compile the design guidelines for designing the guard ring. Unless otherwise stated the following are assumed as defaults: D = 120 µm, d = 10 µm, w = 3 µm, LGR = 0.01 nH, freq = 1, GHz, ρ = 10 -cm. Figure 19 shows the simulation results of isolation versus D for different frequencies and guard ring inductances. Design Guide 14: for all cases, isolation improves with distance D. Design Guide 15: At low f*L as the case of L = 0.01 nH and f = 1, 10 GHz, the isolation is enhanced by ∼10 dB as D is changed from 20 µm to 400 µm. While at high f*L as the case of L = 2, 4 nH, the

Since it provides better isolation, for all of the following simulations, the BP will be grounded with L = 0.01 nH.

GEOMETRY OF GUARD RINGS Because of the uncertainty about the amount of additional isolation provided by guard rings, designers may use guard rings that provide little isolation or may even increase noise coupling. This fact necessitates the quantitative understanding of the isolation provided by the guard rings. It is also beneficial in avoiding unnecessary engineering time and area overhead. Figure 18 shows the structure that is simulated. The guard rings geometrical and the electrical parameters are varied in the next sec-

D

Rec

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d W P+

LGR

P+

25 µm

P+

P+

P-well

P-sub

25 µm

Lbp

18. Geometry of a guard ring.

Gaurd Ring Isolation Versus Distance

f=1 GHz, LGR=0.01nH f=1 GHz, LGR=2nH f=1 GHz, LGR=4nH f=10 GHz, LGR=0.01nH f=10 GHz, LGR=2nH f=10 GHz, LGR=4nH

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S12 (dB)

substrate. Grounding the BP provides a path to ground for the bulk noise current and hence improves the isolation. The improvement is not significant (few dBs) since it is hard for the noise current to get to the wafer BP due to the high resistivity of the substrate. The percentage of the noise current that can make it to the BP increases with frequency as the frequency approaches the cutoff frequency and the substrate capacitive impedance starts to lower the overall substrate impedance, but the impedance of the BP inductance increases with frequency, and its sinking ability decreases. Design Guide 10: Minimizing the inductance of the BP slightly enhances the isolation. Small inductance provides a better ground current sink, while the improvement is only mild due to the fact that the bulk current in high-resistive substrates is not the main noise current contributor. Design Guide 11: The isolation gets better as the distance between the noise transmitter and noise receiver increases. The distance based isolation saturates as the distance gets large if compared to the receiver and transmitter areas. Design Guide 12: For baseline isolation the isolation is relatively frequency independent at frequencies below the cutoff frequency and for ohmic coupling to the substrate. For noise sources that are capacitively coupled to the substrate as in the case of a MOS capacitor that is capacitively coupled to the substrate via the gate capacitance, the isolation becomes a function of frequency, with a large enhancement at low frequency. Design Guide 13: The isolation at low frequency ∼1 GHz for capacitive coupling is enhanced by ∼20 dB relative to the resistive coupling case. At high frequency ∼10 GHz, the improvement in isolation due to the capacitive coupling nearly vanishes. The capacitance of the MOS cap introduces high impedance at low frequency that diminishes the amount of noise that is coupled to the substrate relative to the ohmic case. As frequency increases, the capacitive impedance decreases and the isolation approaches the ohmic case.

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19. Guard ring isolation versus D. 15 ■

isolation improves by ∼20 dB. Thus, the dependence of the isolation on the distance D is not effective at low guard ring inductance, as compared to the cases of high guard ring inductance. This is because the isolation is mainly provided by the guard ring sinking the noise current at low inductance, and increasing the distance adds only slight improvement. While at high inductance the sinking capability is weakened and the distance can contribute more to the isolation. Design Guide 16: In all cases, the ∂I/∂D is max at low D, thus increasing the distance leads to diminishing return especially at low inductance.

Design Guide 19: At high f*L the guard ring approaches being floating and the isolation approaches that of the baseline. In other situations, LGR can inject noise due to its mutual inductance with the neighbor bond wires; in such case the guard ring becomes worse than the baseline. The distance d shown in Figure 18 is varied in a series of simulations. Examining Figures 20 and 21 yields several design guides. Design Guide 20: A guard ring that is tightly enclosing the noise receiver provides up to ∼7 dB of extra isolation if compared to a guard ring that is away from the noise receiver, as long as the inductance of the guard rings to ground is kept very small. The degradation in isolation saturates as the enclosure distance d increases. Design Guide 21: As the guard ring inductance and frequency increase the guard ring loses its current sinking capability and its contribution to the noise isolation. In this case, the enclosure distance plays fewer roles in improving the isolation. This is shown in Figure 20, where the isolation improvement due to a smaller distance d gets less as f*L increases. We also notice that the isolation value approaches its baseline value as f*L increases. Design Guide 22: The increase in isolation due to increasing the distance D is more for a higher resistive substrate. In other words, the rate of change of isolation versus distance D (∂ I/∂ D) is

Design Guide 17: Isolation at both high and low frequencies are very close in value as long as the inductance is very low. This is because the high frequency is still below cutoff frequency and the guard ring is still a good sink even at high frequency due to the low inductance. This will change in the case of capacitive coupling, where low frequency isolation is improved significantly. Design Guide 18: As f and L both go up, D becomes effective in providing isolation. This indicates that more current flows in the substrate and not sunk by the guard ring.

Isolation Versus Ring Enclosure Distance d Substrate Resistivity = 10 Ω−cm

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D=120 µm, f=10 GHz, L=4 nh D=400 µm, f=10 GHz, L=4 nH D=120 µm, f=1 GHz, L=2 nH

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d (µm) 20. Guard ring isolation versus d.

Isolation Versus Ring Enclosure Distance d Substrate Resistivity = 10 Ω-cm

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S12 (dB)

−60

D=120 µm, f=1 GHz, L=0.01 nH

−80

Isolation Versus Ring Enclosure Distance d Substrate Resistivity = 50 Ω-cm

D=120 µm, f=1 GHz, L=0.01 nH D=400 µm, f=1 GHz, L=0.01 nH

−75 −80

D=400 µm, f=1 GHz, L=0.01 nH

−85

−85 0

10

20

30

40

50

0

d (µm)

10

20

30

40

50

d (µm)

(a)

(b) 21. Guard ring isolation versus d.

■ 16


■



■


DUAL GUARD RINGS

Design Guide 27: As f*L increases, the guard ring loses its sinking capability and the isolation is degraded. In such case, the width of the guard ring becomes an ineffective way of providing isolation. In the presence of coupled noise and high f*L, a wider guard ring will pick more noise than a narrow ring, and isolation degrades beyond baseline (with no ring altogether). Design Guide 28: Since wider guard rings provide only slight isolation improvement and they may inject more noise if coupled to a noisy bond wire, narrower guard rings with very low inductance to ground are recommended. Design Guide 29: During chip floor planning, it is highly recommended to spatially separate the noisy signals from sensitive circuits, both on die as far as metal routing and on the package by separating the bond wires of these pins to different sides of the package.

K

An n-well guard ring provides extra isolation if compared to the p guard ring. In the following section, both rings are used simultaneously to study the impact of a dual guard ring on isolation. Figure 24 shows the structure used in the simulation. The inductances of both guard rings are set to be very low. The enclosure distance between the receiver and the ring is kept equal to the distance between both rings. The frequency used in the simulation is high enough to remove the low-frequency isolation enhancement introduced by the capacitive impedance of the p-n junction of the well. This will rule out the parameters that are not present in the case of a p ring alone. Figure 25 shows the simulation results that compare the isolation of a p guard ring alone to the case of dual p and n guard rings.

D

Rec

Trans

d W LGR

Vnoise

P+

P+ 25 µm

P+

P+

P-well

P-well

25 µm

Lbp

22. Guard ring noise coupling.

Isolation Versus Ring Width

−10 −20 −30

S12 (dB)

directly proportional to ρ. As seen in Figure 21(a), the delta in isolation between D = 120 µm and D = 400 µm when ρ = 10 -cm is less than that in Figure 21(b) when ρ = 50 -cm. As ρ gets higher, increasing the distance D causes the impedance between the noise source and noise receiver to increase rapidly if compared to a lower ρ. Design Guide 23: The rate of change of isolation versus substrate resistivity ∂ I/∂ρ is directly proportional to D. As shown in Figure 21, the delta in the isolation between the top curve of Figure 21(a) and the top curve of Figure 21(b) is smaller than that between the bottom curve of Figure 21(a) and the bottom curve of Figure 21(b). At small distance D, changing the substrate resistivity won’t change the substrate resistance and isolation much if compared to the case of larger D. Design Guide 24: For all cases, isolation improves with substrate resistivity. Figure 22 shows the structure used to simulate the relation between guard ring width w and isolation. In this study, the impact of noise coupled to the guard ring through a neighbor bond wire inductance is also highlighted. Bond wires of signals or ground and supply lines that are close to the sensitive circuitry may be switching at high rates and introduces noise to the guard ring under consideration through the mutual coupling between the bond wire inductors. Figure 23 shows four plots of isolation versus ring width for different parameters with and without Vnoise (noise from a neighbor bond wire). Design Guide 25: For low guard ring inductance to ground, increasing the ring width provides more current sinking capability and hence better isolation (∼5 dB). The isolation improvement vanishes at higher w’. Design Guide 26: Even in the presence of noise coupling, as long as the guard ring inductance is kept very small, the guard ring will sink the coupled noise, and isolation will not be degraded. This is clear by examining Figure 23 bottom plot with added noise, which gives nearly the same isolation as the case where no noise is added.

D=120 µm, f=1 GHz, L=0.01 nH, d=10 µm w/o Noise D=120 µm, f=10 GHz, L=4 nH, d=10 µm w/o Noise D=120 µm, f=10 GHz, L=4 nH, d=10 µm, w/Noise D=120 µm, f=1 GHz, L=0.01 nH, d=10 µm, w/Noise

−40 −50 −60 −70 −80

0

5

10 15 Ring Width w (µm)

20

25

23. Guard ring isolation versus w. 17 ■

Design Guide 30: Adding n ring to the p ring improves the isolation. Design Guide 31: The isolation improvement is higher at lower substrate resistivity and lower distance D. The isolation delta between the curves in one chart is reduced moving across the charts and also is reduced moving down the charts. The increase in substrate resistance in the case of small D and in the case of small ρ, introduced by the use of n-well ring, is significant compared to the original substrate resistance, and therefore the effect is significant. For the case of large D and large ρ the change is small compared to the original substrate impedance, hence a lower delta.

vdd

LNGR D

Rec

d N+ P+

LPGR

Trans

W P+ N+

P+ 25 µm

P+

P-well

P-sub

25 µm

N-well Lbp

DIFFERENTIAL NOISE Differential circuits are recommended over single-ended circuits in noisy

24. Dual guard rings.

Isolation Versus Enclosure Distance d, f=10GHz, D=120 µm, ρ=10 Ω-cm

−60

−65

−65

−70

−70

S12 (dB)

S12 (dB)

−60

−75 −80

P GR Only P + N GRs

−85 −90 0

10

20

30

40


−75 −80

P GR Only P + N GRs

−85 −90 0

50

10

Enclosure Distance d (µm) (a)

−70

−70

S12(dB)

S12(dB)

−65

−75 −80

P GR Only P + N GRs


−60

−65

−85

50

(b)


−60

30 40 20 Enclosure Distance d (µm)

−75 −80

P GR Only P + N GRs

−85 −90

−90 0

20

40

0

10

Enclosure Distance d (µm)

20

30

40

50

Enclosure Distance d (µm) (d)

(c)

25. Comparison between single and dual guard rings. ■ 18


■


environments [11]. Substrate noise is not an exception. The noise, due to its random nature, appears as a common-mode signal on the differential outputs. The differential noise signal is typically several orders of magnitude smaller than what would be observed in a single-ended implementation of the circuit. Figure 26 shows a simple asymmetric differential layout, with both p+ and n-well rings used. The two noise receivers of the structure a and b are placed asymmetrically with respect to the noise source Tx. If the noise source is placed symmetrical to the receivers, the differential noise will be very close to zero. The simulation results of the baseline isolation, isolation using a p+ ring only, and the isolation when dual p+ and n-well guard rings are used to surround the noise receivers are shown in Figure 27. The delta in the isolation numbers at noise receivers a and b in the case of the baseline isolation is shown in Figure 27(a) to be 3.1 dB. In Figure 27(b), the delta is 1.78 dB in the case of a p guard ring only surrounding the noise receivers and 0.43 dB in the case of a dual guard ring. Design Guide 32: A dual guard ring, when used for differential configurations, equalize noise coupling on the two sides of the differential structure and decrease the differential noise if compared to the p guard ring alone.

P-sub

P+

a

d N+

D

N well

Tx 26. Noise source placed asymmetrically with respect to receivers.

FLOOR PLANNING AND POWER DOMAINS The next step in the design guide is to design the floor plan and the power domains of the chip to minimize substrate noise coupling. Figure 28 shows the recommended methodology in the floor planning. The guideline is to spatially separate the building blocks based on their analog and digital nature as well as the voltage amplitude and frequency of switching. Each block should be surrounded by a guard ring, or a dual guard ring connected to a lowimpedance ground bond wire. In some cases, two bond wires in parallel are used to minimize inductance to ground. In some situations, the floor planning may contradict with the signal routing.


−25

−65

S12 (dB)

−29 −31


−60

a Baseline b Baseline

−27

S12 (dB)

160 µm

b

Thus, the following floor plan is recommended as long as it is practical to implement versus other constrains. The power domains of each block should be kept separate to avoid noise coupling through the switching power supplies. Figure 29 summarizes the recommended placement and biasing of the guard rings and ground lines. The BP of the die is glued with metal epoxy to the package ground metal plane. This ground metal plane is connected to the external bottom plane of the package and connected to the PCB to establish the external system ground. The on die pads that are connected to the different ground domains (internal grounds) are tied down to the package ground plane using bond wires. These on die ground pads are connected to the different guard rings. The guard rings and the ground domains are designed to reduce substrate coupling by limiting the injected noise and sinking the transmitted noise. To do so, the digital and analog transistors are treated differently. The switching digital transistor sources are separated from the transistor bulks. The sources and bulks are connected to two separate guard rings, as shown in Figure 29 top left section. Doing so will prevent the switching noise from being injected to the bulk, which is connected directly to the substrate. To reduce the effect of the cur-

−70 −75

(a) P GR Only (a) P + N GRs (b) P GR Only (b) P + N GRs

−80

−33

−85

−35 0

20 40 Enclosure Distance d (µm) (a)

0

40 20 Enclosure Distance d (µm) (b)

27. Comparing differential noise isolation of single and dual guard rings.


■


19 ■

vdd1

vdd2

Low Amplitude Analog Circuits

vdd3

Medium Amplitude Analog Circuits

High Amplitude Analog Circuits

vdd4

Guard Rings vdd5

Low Speed Digital Circuits

vddn

High Speed Digital Circuits 10 Buffers

28. Floor plan to minimize substrate noise coupling.

rent, which reaches the bulk, a lowimpedance return path is of uttermost importance. For heavily doped substrates, the best result is obtained by mounting the die with conductive epoxy to the lead frame using several bond wires to connect it to the external ground. Eventually, large substrate contacts with a dedicated pin filling spare places on the chip can be an alternative. In lightly doped substrates where most currents flow just underneath the chip surface, a guard ring with dedicated pin surrounding the digital block is an effective current sink. In these substrates, physical separation of noise source and sensitive circuit is also very effective as the resistance in the noise path continuously increases with the distance. Substrate noise disturbs the analog circuits through their bulk to source voltage.

Package Pins

On Die Pads

2 Ls in //

Dig. Guard Digital

Die with Metal Backplane

Dig. Ground

Digital

Analog

An. Ground and Bulk

Analog

Different gnds

An. Guard

Package gnd Plane

29. Guard ring placement to minimize substrate noise coupling. ■ 20


■


To reduce this bulk effect, bulk source voltage variations of analog MOS transistors should be minimized. The bulk must thus be tied locally to the analog reference on die rather than to the (slightly different) external one on package. This is achieved with bulk contacts close to the analog transistors and biased with the local analog ground, which results in an optimal output voltage relative to the local onchip analog reference. A guard ring with dedicated pin around the analog circuits eventually enhances the noise immunity even further [12] but does not eliminate the need of the good bulk contacts to the local analog ground. For a SiGe process where bipolar transistors are more frequently used than MOS transistors, the bulk terminal of the bipolar transistors that represent their contact to the substrate is connected to a ground pin that is separate from the emitters of the bipolars. The same applies to the bulk of all passive devices in the process. Such separation will prevent noise due to the switching transistors to be injected in the bulk and cause substrate injected noise.

CONCLUSION A design guide to maximize substrate noise isolation is presented based on silicon measurements and a simulation environment calibrated to measurements. The focus is put on the substrate resistivity used in RF and mixed signal ICs as well as the frequency of operation of such applications. The different techniques of the isolation structures are studied together with the electrical and geometrical parameters that affect their performance and guidelines are provided to minimize substrate noise coupling. Recommendations for floor planning and design of power and ground domains are highlighted with emphasis on the ground connections of digital and analog transistors ground connections in CMOS and bipolar technologies.


■


REFERENCES [1] A. Aktas and M. Ismail, CMOS PLLs and VCOs for 4G Wireless. Norwell, MA: Kluwer, May 2004. [2] D.M. Pozar, Microwave Engineering. Reading, MA: Addison-Wesley, 1990. [3] J.A. Buck, W.H. Hayt, and W. Hayt, Engineering Electromagnetics. New York: McGraw-Hill, 1989. [4] M. Pfost, H.-M. Rein, and T. Holzwarth, “Modeling substrate effects in the design of high-speed si-bipolar IC’s,” IEEE J. SolidState Circuits, vol. 31, no. 10, pp. 1493–1501, Oct. 1996. [5] B.R. Stanisic, N.K. Verghese, R.A. Rutenbar, L.R. Carley, and D.J. Allstot, “Addressing substrate coupling in mixed-mode ICs: Simulation and power distribution synthesis,” IEEE J. Solid-State Circuits, vol. 29, no. 3, pp. 226–238, Mar. 1994. [6] F.J.R Clement, E. Zysman, M. Kayal, and M. Declercq, “LAYIN: Toward a global solution for parasitic coupling modeling and visualization,” in Proc. Custom Integrated Circuits Conf., 1994, pp. 537–540. [7] S. Mitra, R.A. Rutenbar, L.R. Carley, and D.J. Allstot, “A methodology for rapid estimation of substrate-coupled switching noise,” in Proc. Custom Integrated Circuits Conf., 1995, pp. 129–132. [8] N. Verghese, D.J. Allstot, and S. Masui, “Rapid simulation of substrate coupling effects in mixed-mode ICs,” in Proc. Custom Integrated Circuits Conf., 1993, pp. 18.3.1–18.3.4. [9] QRC Extraction Datasheet [Online]. Available: http://www.cadence.com/datasheets/qrc_ extraction_ds.pdf [10] D.K. Su, M.J. Loinaz, S. Masui, and B.A. Wooley, “Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits,” IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 420–430, Apr. 1993. [11] M. Ismail and T. Fiez, Analog VLSI: Signal and Information Processing. New York: McGraw-Hill, 1994. [12] R. Gharpurey and R.G. Meyer, “Modeling and analysis of substrate coupling in integrated circuits,” IEEE J. Solid-State Circuits, vol. 31, pp. 344–353, Mar. 1996.

Ahmed Helmy is with the Analog VLSI Lab, Department of Electrical Engineering. The Ohio State University. E-mail: [email protected]. Mohammed Ismail is the founder and director of the Analog VLSI Lab at The Ohio State University. E-mail: [email protected]

21 ■

A Design Guide for Reducing Substrate Noise Coupling ... - IEEE Xplore

A Design Guide for Reducing Substrate Noise Coupling ... - IEEE Xplore

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