Linearity of Word-Level Representations of Multiple

Linearity of Word-Level Representations of Multiple-Valued Networks S. N. Yanushkevich†∗

V. P. Shmerko†

V. D. Malyugin‡

Department of Electrical & Computer

Department of Electrical & Computer

Institute of Control Problems,

Engineering, University of Calgary,

Engineering, University of Calgary,

Russian Academy of Sciences,

CANADA, [email protected]

CANADA, [email protected]

RUSSIA, [email protected]

P. Dziurzanski†§

A. M. Tomaszewska†§

Faculty of Computer Science, Technical University

Faculty of Computer Science, Technical University

of Szczecin, POLAND, [email protected]

of Szczecin, POLAND, [email protected]

We study a boundary case of combinational Multiple-Valued Logic (MVL) network representations, namely, the linear word-level expressions and Linear word-level Decision Diagrams (LDDs). The latter models have a number of useful properties: linearity and planarity, while they need less memory compared to other circuit formats; besides, they are compatible with the traditional word-level Decision Diagrams (DDs). The essential point of our approach is to represent every level of MVL network by a linear word-level expression that is mapped to an LDD. Hence, an arbitrary MVL network is represented by a set of LDDs. We prove that the word-level DD model upon the condition of linearity, lost the ability to optimize the initial form. Two types of linear word-level expressions are studied. The first type of word-level description is based on an arithmetic (spectral) transform of the integer-valued equivalent of the initial multi-output function. In the second type we obtain the word-level description with digit-wise operations by mapping of the initial functions to integer-valued equivalent. For both approaches, we successfully simulate MVL networks with about 250 levels and 8000 ternary gates. We test both models and show that the LDD representation of an MVL circuit consumes ten times less memory compared to standard formats. Keywords - Multiple-valued logic, spectral technique, linear decision diagrams

1

Introduction

The concept of linearization of network models, as a boundary case, has laid the foundation of designing linear systolic arrays [7], linear array multiplier and parallel linear circuits [13]. In some ∗

Supported Supported ‡ Supported § Supported †

by by by by

NSERC (Natural Sciences and Engineering Research Council of Canada), grant 239025-02 NATO Collaborative Linkage Grant PST-CLG.979071 the grant of Scientific Fund of the Russian Federation PhD grant of the State Committee for Scientific Research (KBN), Poland

1

cases, the spectral approach has been used [1, 4, 12]. The problem of linearization and closely related concept of planarization [2, 5, 8, 14] are important factors in VLSI technology, because of their influence on the connection complexity, the so-called ”pin problem”, delay analysis and power dissipation [5]. One can achieve special benefits from linearization in the word-level DD technique [3, 6, 14, 15]. For example, adders and multipliers have been shown as samples of circuits described by linear word-level DD. This paper is a continuation of our previous study of both problems, linearization and planarization [1, 9, 10, 16]. We motivate our interest by the fact that the well-known methods do not guarantee that an arbitrary network can be represented by linear and planar models. The algorithms reported so far deal with particular logic functions, not the arbitrary networks, even though there have been made some attempts to develop heuristics for grouping the outputs in word-level DDs to achieve a linearity of word-level representation. In contradiction, our approach guarantees that an arbitrary combinational MVL circuit is described by linear and planar (by their nature) models. Obviously, the very small class of logic functions can be represented by linear expressions. Moreover, even elementary logic gates cannot be represented by the linear AR spectrum1 . LARs have been considered as good candidates to extend the classes of functions having linear word-level representation2 . In our approach to the linearization of network models we accumulate the best ever reported results. 1. We utilize the statement, originated from [1], that an arbitrary MVL function can be represented by a LAR that is a spectrum of multi-output functions obtained by partitioning of the initial function3 . In our study we apply this result to the MVL gates. 2. It has been proved in [9] that an arbitrary binary circuit can be represented by a set of LARs. The contribution of the present paper can be recognized as the development of previous results [9] towards LDDs and generalization towards MVL circuits. 3. We utilize the statement that an arbitrary Boolean function can be represented by so-called Weighted Logic expression (WL) [10]. Although WLs demonstrated the same advantages as LARs while they have smaller coefficients in the expression, using mixed operations (logic and arithmetical) restricts their application to the levels of the same gate types. We generalize this result towards MVL gates and utilize the unique properties of WLs in linearization procedure. 4. Finally, we apply state-of-the-art of word-level DD, in particular, [3, 6, 11, 14, 15] to form LDDs. The LAR-based spectral diagrams (LDDs) have been first reported in [16]. Based on the understanding of the previously obtained results, the problem of linearization for 1

We do not consider Karuhnen-Loeve conditions of optimality and corresponding transforms. Our discussion is restricted to the transforms used in logic circuit design 2 Many papers have been published in Russian between 1980-1995, that focused on LAR representation of threshold and symmetric Boolean functions 3 The coefficients of such a LAR form a so-called pseudo arithmetic spectrum. In this case a truncated spectral transform is applied. The size of the truncated transform matrix is (n + 1) × (n + 1), in contrast to 2n × 2n for regular matrix, where n is the number of variables in a logic function

2

a multi-level combinational MVL circuit is formulated as the boundary case of its word-level (spectral) model. Hence, we study the exclusive case of Linear word-level DDs. Note that recent results show that a number of basic circuits (adders, multipliers and some control circuits) are representable by Linear DD. We extend the current understanding of linearization (theoretical result) and show that an arbitrary combinational circuit can be represented by a set of LDDs (practical result). The crucial point of our approach is the classical principle of linear system: when all components of the system are linear, the system is linear too. This principle is realized in designing a linear model by using a three-step strategy. (i) an arbitrary MVL gate, an elementary component of an MVL network, is represented by a LAR (pseudo-spectrum) and, thus, an LDD: Gate⇐⇒LAR model ⇐⇒LDD model (ii) We consider an r−level network as a set of r separate levels (multi input/output sub-circuits). The formal description of each level is a LAR that is the weighted sum of LARs corresponding to the gates in this level, and so an LDD can be generated for each level, i.e. Circuit level ⇐⇒ LAR model⇐⇒LDD model (iii) The MVL network description is a set of r linear models, LARs and LDDs: Circuit ⇐⇒ The set of LARs ⇐⇒The set of LDDs Hence, in contrast to the well-known methods that are aiming at building and then linearizing a multi-input, multi-output logic function, the proposed strategy is based on manipulating the LARs of primitive logic functions (gates). We design a word-level linear model in the form of LARs (formal representation) and LDD (graphical representation) scanning the initial circuit level by level. We prove that the resulting model, a set of LDD with links, is unique, as LAR of a gate is unique and the order of the gates is fixed. It means that a given MVL circuit can be described by a set of LDDs and, then, restored in a unique way. Our solution has a size benefit: our algorithm allows representation of large MVL networks (with hundreds inputs/outputs and hundred of thousands of gates) for some seconds. In particular, it requires 1.5-6 times less memory compared to the standard circuit format ISCAS. In this paper we discuss another word-level model, LWL, that is the alternative to linearization of circuit models. We introduce a generalization of the results [10] on WLs, towards MVL circuits. An LWL is generated directly (unlike LAR) from the integer-valued notation of initial multi-output Boolean functions. We show that an LWL-based model leads to the reduction of the memory need by two-three times compared to the lAR-based one. We proved, by the extensive experimental study, that the boundary case of word-level DDs, LAR- and LWL-based LDDs, enhances traditional understanding of the linearity of circuit models and their spectral interpretation. 3

The remainder of the paper is organized as follows. After the short basic definitions (Section 2), we formulate the Task (Section 3) and then introduce our contribution in developing LAR based model of the MVL circuit (Section 4). The results of the experimental study are given in Section 5. We show in Section 6 that there exists another linear word level model of the MVL network, the LWL model. Then, we compare LAR- and LWL-based models of the ternary combinational networks via advanced experimental study (Section 7).

2

Basic definitions

We consider two word-level models of a MVL network, namely, the LAR (Figure 1(a)) and LWL models (Figure 1(b), particular case). An LAR is obtained by AR spectral transform and it is the analytic description of a network in the form of a linear arithmetical equations set. An LWL is a word-level notation (weighted arithmetic sum) of a set of ”linear” logic expressions (linear ReedMuller, disjunctive sum of single literals, truncated sum of single literals and other forms linear in the sense of absence of products of literals). As we show below, the weighted sum of such ”linear” expressions results in an integer-coefficient expression and the corresponding bit-wise operation between its components keeps the linearity4 . We generate LDDs for both models. Definition 1. The linear spectrum (AR or RM) is the coefficient vector of a linear (AR or RM) expression. For example, linear RM expression x1 ⊕ x2 corresponds to the linear RM spectrum F = [01010000] and the LAR expression 2 − x1 + x2 is characterized by the linear AR spectrum P = [21010000]. Boolean functions

Boolean functions Weighted sum

AR transform

mj

Bit-wise operations

RM transform

Word-level expression

(a)

Word-level expression

(b)

Figure 1. Two word-level models to represent a Boolean function

Definition 2. The masking operator is an operator to extract the ξ-th digit, ξ ∈ {0, . . . , k}, of an m-valued representation of the number A = mk ak + mk−1 ak−1 + . . . + mξ aξ + . . . + m0 a0 , jAk Ξ {A} = mod m = aξ . mξ ξ

For instance, given A = 7, ξ = 2 and m = 2, we obtain a2 = 4

(1) ¥7¦ 22

mod 2 = 1.

We assume that the reader is familiar with the basics of spectral technique, namely, AR transform and RM transform

4

Definition 3. An LDD-based model of a multi-level combinational MVL network with no feedback is a set of LDDs, each representing a level of the MVL network. It follows from Definition 3 that the number of LDDs in this model is equal to the number of levels in the corresponding circuit. We consider two types of LDDs: LWL-based and LAR-based. Definition 4. An LAR-based model of a multi-level combinational MVL network is an n-input r-output function d0 + d1 x1 + . . . + dn xn , (2) where d0 , . . . , dn are integer numbers (weights). The LAR (2) carries information about an r-output function, or a system of r MVL functions. Notice, an arbitrary multi-output Boolean function given in a RM or sum-of-products form can be represented in a unique way by an WL expression [10]. The uniqueness follows from the uniqueness of an AR of one function and the unambiguity of encoding the outputs of the multioutput function. The inverse statement is also true: given a LAR, it is possible to restore the initial functions (see Section 4). An alternative word-level representation of Boolean functions is WLs, a generalization of sumof-products and RM form [10]. Example 1. Let us consider a two-output Boolean function f with outputs f1 = x1 ⊕ x2 , f2 = x1 ⊕x2 . In contrast to the traditional word-level LAR f = 21 f2 +20 f1 , the LWL of a given function

a

is defined via the bit-wise operation denoted by ⊕, that is f = 21 f2 + 20 f1 = 21 (x1 ⊕ x2 ) + 20 (x1 ⊕ x2 )

a

a

= 20 x1 ⊕ 21 x1 ⊕ (20 + 21 )x2 . The bit-wise modulo 2 sum of the weighted variables produces the integer values of the function.

a

a

For example, given x1 = 1, x2 = 1, we get f (1, 1) = 2 · 0 ⊕ 3 · 1 ⊕ 1 = 2 = (10)2 that corresponds to f1 (1, 1) = 0 and f2 (1, 1) = 1. The truth table of the multi-output function is f = [2 1 2 1]. Note that the LWL representation exist for ”linear” sum-of-products and RM expressions such as functions implemented by elementary two-input AND or EXOR gates. As for a circuit level, LWL exists only for the level consisting of the same type of gates (otherwise, they are not linear). In such particular cases, the LWL exhibits an advantage. Example 2. Let us compare the LWL and AR given the two-output Boolean function f1 = x1 ∨ x2 , f2 = x1 ∨ x2 . Both are ”linear” sum-of-products (only the single literals are included), so

a

a

their WL is ”linear” as well: LW L = x1 ∨ 2x1 ∨ 3x2 . On the other hand, the weighted sum of their arithmetical forms yields AR = 2f2 + f1 = 2(x1 + x2 − x1 x2 ) + (x1 + x2 − x1 x2 ) = x1 + 2x1 + 3x2 − x1 x2 − 2x1 x2 5

We observe, that the AR is not linear; it requires a special technique for linearization. In contrast to LAR, an LWL always exists in the above mentioned particular cases such as a multi-output function implementing by a circuit level of the same logic gates. In this paper we generalize LWL-based method for the particular case of MVL functions (elementary gates) implemented ”linear” WL expressions. Thus, an LWL-based approach can produce an alternative solution for some particular cases of the MVL networks.

3

Task formulation

We formulate the task as follows. Given: an arbitrary combinational MVL circuit, Find: a word-level linear model of the circuit. The strategies to solve the problem. Strategy 1: find the linear pseudo-spectrum (LAR) for each circuit gate and apply the system linearity paradigm to describe the initial network of gates level by level. Strategy 2: simplify the LAR-based model by combining it with LWL-based representation of particular MVL network levels. In both cases, an l-th level of the network is described by a LAR or LWL. It is important to notice that we do not consider the problem of optimization of the DD model of a given circuit like the traditional DD based technique. In the above task formulation we are interested in the boundary case of the circuit models, that is the LDDs, and their unique ability to linearize a description of an arbitrary combinational MVL circuit.

4

LAR based model of an MVL network

We utilize the beneficial idea of [1] and its further development by [16] to build an LAR based model of the MVL gates. We consider a ternary-valued case for simplification but without losses of generality. 4.1 LARs of the elementary gates

A method reformulated from [1] is illustrated by Figure 2 and described in detail below. The method includes three steps: (i) partitioning of the truth vector X of the gate to a set of subvectors X◦ , (ii) description of each part by a LAR with two binary pseudo-variables; applying the AR transform to obtain a pseudo-spectrum, and (iii) representation of the gate by the LAR of two binary pseudo-variables (weighted sum of LARs corresponding to X◦ s). LAR of an elementary gate is the pseudo AR spectrum that is the LAR of pseudo variables. Let us partition the truth column vector X of an n-variable m-valued function f into τ = dmn /(n + 1)e parts, where d·e denotes the nearest greater integer. The order of the partition is fixed (with respect to assignments of variables). Let us call µ-th part of X the sub vector (function) Xµ , µ = 0, 1, . . . , τ − 1. The index µ of Xµ given the i-th element of the initial truth table is equal to µ = bi/(n + 1)c, where b·c is the nearest smaller integer. In particular, 6

       ! " # $ % ! &  #  '( &  !  ) * ! 


       

    
              

     

+ ,-.$ %     #  '( &  !  ) * !  /

Figure 2. A pseudo-arithmetic spectrum of an MVL gate

given an arbitrary 3-input gate, its X includes 33 = 27 elements and can be partitioned into τ = d33 /(3 + 1)e = d27/4e = d6.7e = 7 sub-vectors X0 , X1 , . . . , X6 . The 20-th element of the truth vector X is located in the sub-vector X5 , since µ = b20/(3 + 1)c = 5. The Xµ , µ = 0, 1, . . . , τ − 1, is a function of n new variables x◦1 , x◦2 , . . . , x◦n , called pseudovariables. The pseudo-variables are the binary variables valid for assignments with at most one 1. For instance, for a set of four pseudo-variables x◦1 , . . . , x◦4 , the only valid variable assignments are {0000, 0001, 0010, 0100, 1000}. Table 1. LAR model to implement the ternary M AX(x1 , x2 ) gate Function MAX x1 x2 X Xµ 00 01 02 10 11 12 20 21 22

203 617 6 7 627 6 7 6 7 6 7 617 6 7 617 6 7 627 6 7 6 7 6 7 627 6 7 425 2

LAR model Pµ and LAR

x◦1 x◦2

2 3 0 X0 = 415 2

00 01 10

2 3 0 P0 = K · X0 = 415 = x◦2 + 2x◦1 2

2 3 1 X1 = 415 2

00 01 10

2 3 1 P1 = K · X1 = 405 = 1 + x◦1 1

2 3 2 X2 = 425 2

00 01 10

2 3 2 P2 = K · X2 = 405 = 2 0

£ ¤T Definition 5. Let W = mτ −1 mτ −2 · · · m1 m0 be the weight vector. A truth vector X◦ of a function f of n pseudo-variables x◦1 , . . . , x◦n includes n + 1 elements and is calculated by X◦ = [Xτ −1 | . . . |X1 |X0 ]W,

(3)

Example 3. Let us calculate the truth vector X◦ of a two-input M AX(x1 , x2 ) gate (Table 1). After partitioning of column-truth vector into three sub-vectors Xµ , µ = 0, 1, 2 where τ = d32 /(2 + 1)e = 3. A truth vector X◦ is derived from Xµ as follows · ¸· 2 ¸ · ¸ 3 2 1 0 21 ◦ 1 3 X = [X2 |X1 |X0 ]W = 2 1 1 = 22 . 0 2

7

2

2

3

26

4.2 Pseudo-spectrum of a logic gate

Theorem 1. An arbitrary m-valued n-variable function of n variables can be described by a Linear Arithmetic Expression (LAR), a function of corresponding n pseudo-variables of the form LAR = p0 + p1 x◦n p2 x◦n−1 · · · pn x◦1 ]T The vector of spectral coefficients P = [p0 p1 ...pn ] and the truth-vector X◦ of n-variable function meets the pair of spectral transforms P = K · X◦ , X◦ = K−1 · P

(4) (5)

where the direct AR transform matrix K and inverse AR transform matrix K−1 are truncated to the dimension (n + 1) × (n + 1). The proof of Theorem 1 is given in [1]. Note, for a 2-variable function the 3 × 3 forward and inverse truncated matrices are equal · ¸ · ¸ 1 0 0 1 0 0 −1 K = −1 1 0 , K = 1 1 0 . −1

0

1

1

0

1

Example 4. Let us find an LAR expression to describe the two-input MAX gate (Example 3). In Table 1, we give the partitioned column truth vector as a set of sub-vectors X0 , X1 , X2 , and the corresponding set of LARs represented by their pseudo-spectra P0 , P1 , P2 for the pseudo-variable assignments {x◦1 , x◦2 } = {00, 01, 10}. Accordingly (3), the pseudo-spectrum for M AX(x1 , x2 ) is P = 21 + 5x◦1 + x◦2 , and vector of spectral coefficients can be calculated as · ◦

P=K·X

=

1 −1 −1

0 1 0

0 0 1

¸·

21 22 26

¸

· =

21 1 5

¸ ,

4.3 Restoration procedure

The next example illustrates the restoration procedure, i.e. calculation of the output of the LAR model given the input assignments. Example 5. Given the word-level model, P = 21 + 5x◦1 + x◦2 , of the M AX(x1 , x2 ) gate, calculate its output value given (x1 , x2 ) = (2, 1). Based on the encoding rule given in Table 1, x1 x2 = 21 is equivalent to x◦1 x◦2 = 01. In order to find the sub-vector Xµ , let us calculate µ: x1 x2 = 21. It corresponds to the 7-th element of the truth vector X, µ = b7/3c = 2. The LAR P satisfies the model (2), i.e. P = d1 x1◦ + d2 x◦2 + d0 . So, taken ξ = µ in (2) and the masking operator (1), we are able to define the LAR for an arbitrary 3-valued 2-input logic gate. Definition 6. A function f implemented by an arbitrary 3-valued (m = 3) two-input (n = 2) logic gate can be extracted from the LAR P by the masking operator f = Ξµ {P } = 8

jP k 3µ

mod 3.

(6)

The example below illustrates how to calculate any value of the MVL function via the LAR model (6) of the MVL circuit. Example 6. Calculation of M AX(2, 1) is equivalent to the computation of f = Ξµ {P }. Since ¥ ¦ x◦1 x◦2 = 01, then Ξ2 {21 + 5x◦1 + x◦2 } = Ξ2 {22} = 22 mod 3 = 2. 32 4.4 Pseudo spectrum of a level

Let us treat a level of an MVL network as an n-input r-output function. Lemma 2. An LAR-based formal model of an n-input r-output level of a ternary circuit is the LAR r X L= (33(j−1) Pj ). (7) j=1

that is the weighed sum of pseudo-spectra (LARs) of each output fj , j ∈ (1, . . . , r). Proof: Ordering the functions Pj by weights and summation yields a polynomial that satisfies (2) and, thus, a LAR too. The uniqueness of such a LAR follows from the unambiguity of encoding the LARs (pseudo-spectra Pj ) by weights. Thus, a particular case, a LAR for ternary gate, is described as follows. Definition 7. A 3-valued (m = 3) n-input r-output function which j-th output, j ∈ {1, . . . , r}, is derived from (1) taken ξ = 3(j − 1) + µ fj = Ξ3(j−1)+µ {L} =

j

L 33(j−1)+µ

k mod 3.

(8)

Hence, the proposed strategy on LAR based linearization of MVL circuit model can be represented as follows Gate model P ⇐⇒ f = Ξµ {P } Circuit level model L ⇐⇒ fj = Ξ3(j−1)+µ {L} Circuit model (set of L) ⇐⇒ The set of level outputs Example 7. Find a word-level expression to represent a circuit level consisting of three two-input MAX gates (with separate inputs). Based on the word-level description of MAX gate (Example 3): P = 30 (21 + 5x◦1 + x◦2 ) + 33 (21 + 5x◦3 + x◦4 ) + 36 (21 + 5x◦5 + x◦6 ) = 15897 + 5x◦1 + x◦2 + 135x◦3 + 27x◦4 + 3645x◦5 + 729x◦6 . The correspondence of the assignments of variables and pseudo-variables is given below: x1 x2 x3 x4 x5 x6 = 201112 =⇒ x◦1 x◦2 x◦3 x◦4 x◦5 x◦6 = 000110 and µ1 = 2, µ2 = 1, µ3 = 1. For this assignment, P = 15897 + 5 · 0 + 1 · 0 + 135 · 0 + 27 · 1 + 3645 · 1 + 729 · 0 = 19569. Then, the outputs fj , j ∈ {1, 2, 3}, of the level are calculated by (8) as follows

9

3·0+2

f1 = Ξ

{19569} =

f2 = Ξ3·1+1 {19569} = f3 = Ξ3·2+1 {19569} =

j 19569 k 32 j 19569 k 34 j 19569 k 37

mod 3 = 2, mod 3 = 1, mod 3 = 2.

Table 2. LARs and pseudo-spectrum of elementary gates x x1 · x2 mod 3 M IN (x1 , x2 ) T SU M (x1 , x2 ) M AX(x1 , x2 ) T P ROD(x1 , x2 ) (x1 + x2 ) mod 3 x1 |x2

= = = = = = = =

2−x 15x◦1 + 21x◦2 21x◦1 + 12x◦2 21 + 5x◦1 + 4x◦2 21 + 5x◦1 + x◦2 21x◦1 + 9x◦2 21 − 10x◦1 − 14x◦2 1 − x◦1 + 5x◦2

£ P= 2 £ P= 0 £ P= 0 £ P = 21 £ P = 21 £ P= 0 £ P = 21 £ P= 1

¤T −1 ¤T 21 15 ¤T 12 21 ¤T 4 5 ¤T 1 5 ¤T 9 21 ¤T −14 −10 ¤T 5 −1

Table 2 contains the LAR-based models of ternary gates from a library of gates. The new models can be formed using these basic ones. For example, x1 + x2 (mod 3) = Ξµ {30 (2 − (x◦2 + 2x◦1 )) + 31 (2 − (1 + x◦2 − x1◦ )) + 32 (2 − (2 − 2x◦2 − x◦1 ))} = Ξµ {5 + 14x◦2 + 10x◦1 }. 4.5 LDD design

We utilize the state-of-the-art DD technique, word-level LDDs with arithmetic analog of the Positive Davio pDA expansion in the nodes, to represent, manipulate, and calculate the LARs introduced above, . An equivalent word-level model of a gate is an LDD, the graph-based representation of LAR expression [16]. We will use the LDD models of a circuit level involving elementary 2-input ternary gates. The LDD corresponds the LARs accordingly the scheme Gate Circuit level Circuit

⇐⇒ ⇐⇒ ⇐⇒

LAR gate model LAR level model A set of LAR level models

⇐⇒ ⇐⇒ ⇐⇒

LDD gate model LDD level model A set of LDD level models

Lemma 3. An arbitrary MVL network can be modelled by a set of l LDDs. The proof follows from Lemma 2 and also from Definition 3. Example 8. The LDDs for the ternary MIN and MAX gates are given in Figure 3. Figure 4 shows the set of two LDDs derived from the LAR for a two-level ternary network. 10

MIN

MAX

21x◦1 + 12x◦2

21 + 5x◦1 + x◦2

pDA

0 pDA

0

0

x

o 2

pDA

x1o

0

31+2⋅⋅32

pDA

0

Karnaugh maps of MAX gate

x1o

0 1 x 2⋅⋅3 +3 o 2

31+2⋅⋅32 30

31+32

x2

x1

0 1 2

0

1

2

0 1 2

1 1 2

2 2 2

x2o

x1o

0 1

0

1

21 22

26 -

x1ox2o

0

1

2

00 01 10

0 1 2

1 1 2

2 2 2

Figure 3. LAR and LDD models of 3-valued gates

y1 y2

x1 x2 MIN

pD A

MIN

pD A

MIN

y3 y4

x3 x4

0

z1 0 pDA

z2

0

MAX

x3o

pDA

0

27.21+21

x4o

27.1

pD A

o

0

x1 x2o

pDA

5

0

1

27.5

pDA

0 pDA

0

21

y4o

y3o

o

y1 y2o

5

1

27.21

27.12

Figure 4. A 2-level ternary circuit (left) and its LDD model (right)

4.6 Algorithm

The algorithm to derive a LAR-based LDD model given a circuit description is shown in Figure 5. One of the difficult problems of word-level representation, including linear forms, are the exponential values of terminal nodes. To calculate these, we utilize Zero-Suppressed BDD-like trees [11]. We developed a special encoding scheme in order to obtain reasonable memory requirements. In case of LDD derived from the ternary gates, each terminal node is a sum of three integer exponential numbers, where mantissa takes a value from a set {-2,-1, . . . , 2} and the exponents are three subsequent integers. Moreover, as we use circuits with 2 inputs only, two adjoining terminal nodes at the 2i-th and 2i + 1-th LDD levels have the same components: 33i , 33i+1 and 33i+2 . Consequently, there is no need to keep the huge exponential numbers, as they can be calculated simply from the given tree level and, thus, each terminal node is described fully by a set of three mantissas. In this way, we replace the calculation by manipulating the encoded bits of numbers (for more details, see [16]). Communication between LDDs will be considered in the Appendix.

11

procedure buildLDD(circuit): for (∀ level i in the circuit) { Design LDD for level i; for (∀ gate g in level i) for (∀ input in of gate g) if (no input in in LDD for level i) then add a new node with pseudo-variable corresponding to the given input; else add new terminal value to the existing node with pseudo-variable corresponding to the given input; return set of LDDs; }

Figure 5. The algorithm to build word-level LDD of an MVL circuit

5

Experiments with LAR based LDD model

We simulated the LAR based LDDs of the benchmark circuits (with about 5000 gates) from LGSynth 93 base)5 . Every binary gate from the circuit is interpreted as a ternary gate, i.e. AND gate is replaced with MIN gate, and OR gate is replaced with MAX gate. Then we represented each MVL gate by its LAR model. Finally, we mapped this model to the LDDs. 6 A. Experiment on comparison of the number of gates in the circuit and the number of nodes in LAR based LDD. The first three columns in Table 3 contain the name of the tested circuit, the number of inputs/outputs (IN/OUT), and the number of gates (#G). In the fourth and fifth columns we indicate the number of circuit levels (#L) and the total number of nodes (#N) in LDDs. In the brackets (Nmax ) we give the maximal number of nodes in an LDD from the set of LDDs. We indicate, in the sixth column, the parameter Wmax that is the maximal number of digits in a terminal node value. In the last column we give run time (CPU) in seconds to simulate a circuit via the set of LDDs. Observation: (i) The number of nodes (#N) in LDD is comparable with the number of gates (#G) in the circuit. For example, 207-input 109-output circuit C7552 that includes 4094 gates is represented by 66 LDDs (#L=66) with #N=5935 nodes. This is because of the complexity O(#G) of our algorithm. (ii) Run time (CPU) to transform circuit from EDIF format to a system of LDDs is acceptable for practice. This proves the efficiency of the algorithm, which manipulates, for instance, a model of the 32-bit multiplier (C6288) that operates with 800-ternary-digit numbers. B. Experiment on comparison of memory requirements with standard circuits formats. In Table 4 we give the memory requirements for the EDIF and ISCAS formats, and the proposed LAR based LDD representation (column LDD(LAR)). 5

http://zodiac.cbl.ncsu.edu/CBL Docs/lgs93.html The package is available from the authors. Our program LDDDesign is written in C. In the experiments, a PC Pentium III 450 MHz processor with 128 MB RAM was used. 6

12

Observation: LAR-based LDDs require about 5-20 times less memory than EDIF and 1.5-7 times less memory compared to ISCAS format. Table 3. Characteristics of LDDs Name C17 C432 C499 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552

T E S T IN/OUT 5/2 36/54 41/32 60/32 41/32 33/25 233/108 50/24 178/163 32/32 207/109

#G 12 319 524 619 908 765 1234 1670 2910 4768 4094

#L 6 28 25 39 43 54 45 65 78 245 66

LDD-based #N(Nmax ) 23(5) 503(46) 880(105) 860(59) 1354(129) 1140(71) 1715(228) 2397(202) 3977(356) 6917(256) 5935(407)

network Wmax 6 63 200 148 192 101 372 311 646 768 561

CPU 0.00 0.04 0.15 0.10 0.25 0.12 0.91 1.14 2.06 1.43 3.69

Table 4. Comparison of memory requirements for LDDs TEST C17 C432 C499 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552

6

#G 12 433 516 619 1204 2134 2603 3901 6018 4847 8067

Memory [bytes] EDIF LDD(LAR) 5478 258 102257 6314 167343 15301 190729 8869 273018 16133 230507 13098 400707 32395 503457 34744 903899 88965 1387230 71476 1236066 146057

#G 6 160 202 383 546 880 1193 1669 2307 2416 3512

Memory [bytes] ISCAS LDD(LAR) 1303 201 18991 4601 21989 5427 37844 8306 59573 16850 78574 22491 110025 36305 145359 54857 220596 107392 255406 168572 311939 271970

LWL model of MVL network

In this Section we discuss an alternative model of an arbitrary MVL combinational circuit. It was shown in [10] that an arbitrary Boolean multi-output function given in SOP or RM form can be represented in a unique way by a weighted logical expression, LWL. These expressions have a number of useful properties: (i) LWL is generated by bit-wise operations, no arithmetical ones (excepting calculation of the integer coefficients). In MVL cases, we need digit-wise operation. Note, that in opposite to the LARs with the huge coefficients (more than k 100 in our experiments) that require the special technique to manipulate the codes of these weights, the LWL-based model do not need this technique. (ii) An LWL of an elementary 2-input MVL gate is a 2-variable linear logic expression (linear Reed-Muller, and also other forms ”linear” with respect to logic summation operations: disjunctive

13

sum of single literals, truncated sum of single literals and other forms linear in sense of due to no products presented). (iii) One can design an LWL-based model of a given logic network deriving LWL for each level. The latter is a word-level notation (weighted arithmetic sum) of the LWLs of gates, and, thus, is linear (with respect to their sum (modulo, disjunction, truncated sum, etc.) as well. However, this model has a number of restrictions, such as the same type of gates in the level. An LWL model of an MVL network is derived by the two-step strategy: Circuit level Circuit

⇐⇒ ⇐⇒

LWL model The set of LWLs

⇐⇒ ⇐⇒

LDD model The set of LDDs

6.1 Generalized LWL

The central statement of the LWL based model design is the Theorem below. Theorem 4. An LWL of an MVL function of n ≤ N variables is defined by n

LW L =

_ K

wi,q xi,q ,

(9)

i=1

where xi,0 denotes bi , wi,q ≥ 0 is an integer value J xi , xi,1 denotes xi , xi,2 means cyclic inversion x (weight), and is for digit-wise M AX, M ODSU M or T SU M operation.

a

Proof-sketch. The above statement follows from the fact that the digit-wise operation ¯ of the digits ”weighted” (multiplied) by mj−1 , j = 1, 2, . . . , k, and summarized, produces the same result

a

a

as the arithmetical sum, i.e. mk ak + mk−1 ak−1 + . . . + mξ aξ + . . . + m0 a0 = mk ak ¯ mk−1 ak−1 ¯

a

a

a

. . . ¯ mξ aξ ¯ . . . ¯ m0 a0 . Applying the distributive law, we can have some variables with weights

a

like (m0 + m1 + ...). The digit-wise operation (in particular ¯) results in the integer values; their binary interpretation produces the initial function. We explain this Theorem by the following example. Example 9. Let ¯ denotes any of logic operations M AX, M ODSU M or T SU M . For instance, x1 ¯ x2 means x1 ∨ x2 if ¯ = max(x1 , x2 ). The corresponding digit-wise operation is specified by

a

¯. In case of MIN and TPROD gates we apply DeMorgan’s law to obtain MAX and TSUM. For example, f1 = x1 x2 ⇒ f 1 = x1 ∨ x2 = Ξ1 {LW LM IN } f2 = x2 x3 ⇒ f 2 = x2 ∨ x3 = Ξ2 {LW LM IN } where LW LM IN = 31 f 2 + 30 f 1 = 30 (x1 ∨ x2 ) + 31 (x2 ∨ x3 )

a

a

= 30 x1 ∨ (30 + 31 )x2 ∨ 31 x3 . 14

By analogy7n ’ f1 = x1 u x2 ⇒ f 1 = x1 t x2 = Ξ1 {LW LT P ROD }, f2 = x2 u x3 ⇒ f 2 = x2 t x3 = Ξ2 {LW LT P ROD } where LW LT P ROD = 31 f 2 + 30 f 1 = 30 (x1 t x2 ) + 31 (x2 t x3 )

a

a

= x1 t (30 + 31 )x2 t 31 x3 . To restore the initial data from the LWL expression, we apply a masking operator. Lemma 5. A value fj of a j-th MVL function, j ∈ {1, . . . , r}, can be extracted from an LWL (9) by a masking operator (1) taken ξ = j fj = Ξj−1 {LW L} =

j LW L k mj−1

mod m.

(10)

a

Proof-sketch. The above statement follows from the fact that the digit-wise operation ¯ of the weights mj−1 , j = 1, 2, . . . , k, produces the same result as the arithmetical sum, i.e. A =

a

a

a

a

mk ak + mk−1 ak−1 + . . . + mξ aξ + . . . + m0 a0 = mk ak mk−1 ak−1 ¯ . . . ¯ mξ aξ ¯ . . . ¯ m0 a0 . Note that fj is considered any of mn m-valued values of the function fj , and LWL as any integer (word-level) value of the LWL. If ¯ denotes a M ODSU M operation, the LWL can be described as a result of spectral transform, as presented in Fig. 1b. 6.2 Network representation by generalized ¯−description

In a general case, i.e. a circuit level with n inputs and r outputs f1 , ...fr , the LWL is equal to

a

a

a

a

a

a

f = a1 · x1 ∨ b1 · x1 ∨ a2 · x2 ∨ b2 · x2 ∨ . . . ∨ an · xn ∨ bn · xn , ai , bi ∈ {0, 1, . . . , 2r−1 }. The Boolean functions f1 , ...fr can be restored from the LWL as follows (1)

(r)

i=1

{z

a

(1)

(r)

a

(1)

a

(r)

(1)

(r)

a

a

a

(r) (1) (r) f = a1 . . . a1 x1 ∨ b1 . . . b1 x1 ∨ a2 . . . a2 x2 ∨ b2 . . . b2 x2 ∨ . . . ∨ a(1) n . . . an xn ∨ bn . . . bn xn n n n _ _ _ (1) (1) (2) (2) (r) (r) = [ (ai xi ∨ bi xi ); (ai xi ∨ bi xi ); . . . ; (ai xi ∨ bi xi )]

|

Output f1

} i=1 |

{z

}

i=1

|

Output f2

{z

}

Output fr

The generalized ¯−description can be useful in some cases. 15

Let us build, for exam-

ple, an LWL-based model of a 2-input, 3-output level of an MVL circuit consisting of the gates f1 = x1 ¯x2 , f2 = x1 ¯x2 , f3 = x1 ¯x2 . Recall, that ¯ operation denotes M AX, M IN, M ODSU M , T SU M or T P ROD. The LWL model of the level is 32 f3 + 31 f2 + 30 f1 = 32 (x1 ¯x2 ) + 31 (x1 ¯x2 ) + 30 (x1 ¯x2 )

a

a

a

a

a

a

= (32 + 30 )x1 ¯ (31 + 30 )x2 ¯ 31 x1 ¯ 32 x2 = 10x1 ¯ 4x2 ¯ 3x1 ¯ 9x2 . So, we can calculate the outputs f1 , 2 a a 10 · 0 ¯ 4 · 0 ¯ 3 · 2 6 a a 6 6 10 · 0 ¯ 4 · 1 ¯ 3 · 2 6 a a 6 6 10 · 0 ¯ 4 · 2 ¯ 3 · 2 6 a a 6 6 10 · 1 ¯ 4 · 0 ¯ 3 · 1 6 6 a a [f3 f2 f1 ] = 66 10 · 1 ¯ 4 · 1 ¯ 3·1 6 a a 6 10 · 1 ¯ 4 · 2 ¯ 3 · 1 6 6 a a 6 10 · 2 ¯ 4·0 ¯ 3·0 6 6 a a 6 10 · 2 ¯ 4·1 ¯ 3·0 4 a a 10 · 2

¯

4·2

¯

3·0

f2 and f3 as follows 2 3 a a a a ¯ 9·2 000 ¯ 000 ¯ 020 ¯ 200 6 7 a a a a 6 7 6 000 ¯ 011 ¯ 020 ¯ 100 ¯ 9·1 7 6 7 a a a a 6 7 6 000 ¯ 022 ¯ 020 ¯ 000 7 ¯ 9·0 7 6 a a a a 6 7 6 101 ¯ 000 ¯ 010 ¯ 200 ¯ 9·2 7 7 6 = 7 6 a a a a 6 101 ¯ 011 ¯ 010 ¯ 100 ¯ 9·1 7 7 6 7 6 a a a a 6 101 ¯ 022 ¯ 010 ¯ 000 ¯ 9·0 7 6 7 6 7 a a a a 6 202 ¯ ¯ 9·2 7 000 ¯ 000 ¯ 200 7 6 7 6 a a a a 6 202 ¯ ¯ 9·1 7 011 ¯ 000 ¯ 100 5 4 a a a a ¯

9·0

3

2

7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 5

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 4

=

202 ¯ 022 ¯ 000 ¯ 000

c0 b0 a0

3

7 7 c1 b1 a1 7 7 7 c2 b2 a2 7 7 7 c3 b3 a3 7 7 7 c4 b4 a4 7 7 7 c5 b5 a5 7 7 7 7 c6 b6 a6 7 7 7 c7 b7 a7 7 5 c8 b8 a8

a a

In particular, given the assignments x1 x2 x1 x2 = {0022} and ¯=∨, the values of functions are equal to a0 = 0¯0¯0¯0 = 0∨0∨0∨0 = 0(x1 ∨ x2 = 0 ∨ 0 = 0), b0 = 0¯0¯2¯0 = 0∨0∨2∨0 = 2(x1 ∨ x2 = 2 ∨ 0 = 2), c0 = 0¯0¯0¯2 = 0∨0∨0∨2 = 2(x1 ∨ x2 = 0 ∨ 2 = 2). Hence, ¯−expression represents different sub-circuits (levels) that depend on the type of operation. In our case, f1 = x1 ¯x2 , f2 = x1 ¯x2 , f3 = x1 ¯x2 we have LW LM IN f3 f2 f1 0 0 2 6 1 0 1 6 6 2 0 0 6 6 0 1 1 6 6 1 1 1 6 6 1 0 0 6 6 0 2 0 4 0 1 0 0 0 0 2

3 7 7 7 7 7 7 7 7 7 7 7 5

LW LM AX f3 f2 f1 2 2 0 6 1 2 1 6 6 0 2 2 6 6 2 1 1 6 6 1 1 1 6 6 1 2 2 6 6 2 0 2 4 2 1 2 2 2 2 2

3 7 7 7 7 7 7 7 7 7 7 7 5

LW LM ODSU M LW LT SU M LW LT P ROD f3 f2 f1 2 2 0 6 1 0 1 6 6 0 1 2 6 6 0 1 1 6 6 2 2 2 6 6 1 0 0 6 6 1 0 2 4 0 1 0 2 2 1 2

3 7 7 7 7 7 7 7 7 7 7 7 5

f3 f2 f1 2 2 0 6 1 2 1 6 6 0 2 2 6 6 2 1 1 6 6 2 2 2 6 6 1 2 2 6 6 2 0 2 4 2 1 2 2 2 2 2

3 7 7 7 7 7 7 7 7 7 7 7 5

f3 f2 f1 0 0 2 6 1 0 1 6 6 2 0 0 6 6 0 1 1 6 6 0 0 0 6 6 1 0 0 6 6 0 2 0 4 0 1 0 0 0 0 2

3 7 7 7 7 7 7 7 7 7 7 7 5

6.3 Particular case: linear RM spectrum

In a case where a sub-circuit includes M ODSU M gates only (Figure 6), the spectral interpretation is very simple. We calculate RM spectrum F1 for the first M ODSU M function (gate) f1 with the truth vector X1 = [012120201]:

16

  f1 = x1 ⊕ x2 : X1 = [012120201] f2 = x1 ⊕ x2 : X2 = [201120012]  f3 = x1 ⊕ x2 : X3 = [210021102]

x1 x2 x1 x2


 

3 f1


 

3 f2


 

3 f3

0

1

2

Figure 6. The i-th level of a circuit with M ODSU M gates 2

F1 = K ·

6 6 6 6 6 X1 = 666 6 6 6 4

1 0 2 0 0 0 2 0 1

0 2 2 0 0 0 0 1 1

0 1 2 0 0 0 0 2 1

0 0 0 2 0 1 2 0 1

0 0 0 0 1 1 0 1 1

0 0 0 0 2 1 0 2 1

0 0 0 1 0 2 2 0 1

0 0 0 0 2 2 0 1 1

0 0 0 0 1 2 0 2 1

32 76 76 76 76 76 76 76 76 76 76 76 54

0 1 2 1 2 0 2 0 1

2 3 0 7 6 1 7 7 6 7 7 6 0 7 7 6 7 7 6 1 7 7 6 7 0 = 7 6 7 7 6 7 7 6 0 7 7 6 7 7 6 0 7 5 4 0 5 0 3

By analogy, the RM spectra for the second and third gates are F2 = [210200000] and F3 = [220100000] accordingly. The LWL model of the circuit level is 32 f3 + 31 f2 + 30 f1 = 32 (x1 ⊕x2 ) + 31 (x1 ⊕x2 ) + 30 (x1 ⊕x2 )

a

a

a

a

a

a

= (32 + 30 )x1 ⊕ (31 + 30 )x2 ⊕ 31 x1 ⊕ 32 x2 = 10x1 ⊕ 4x2 ⊕ 3x1 ⊕ 9x2 . The outputs f1 , f2 and f3 are as follows 2 a a a 10 · 0 ⊕ 4 · 0 ⊕ 3 · 2 ⊕ 9 · 2 6 a a a 6 6 10 · 0 ⊕ 4 · 1 ⊕ 3 · 2 ⊕ 9 · 1 6 a a a 6 6 10 · 0 ⊕ 4 · 2 ⊕ 3 · 2 ⊕ 9 · 0 6 a a a 6 6 10 · 1 ⊕ 4 · 0 ⊕ 3 · 1 ⊕ 9 · 2 6 a a a [f3 f2 f1 ] = 666 10 · 1 ⊕ 4·1 ⊕ 3·1 ⊕ 9·1 6 a a a 6 10 · 1 ⊕ 4 · 2 ⊕ 3 · 1 ⊕ 9 · 0 6 6 a a a 6 10 · 2 ⊕ 4·0 ⊕ 3·0 ⊕ 9·2 6 6 a a a 6 10 · 2 ⊕ 4·1 ⊕ 3·0 ⊕ 9·1 4 a a a 10 · 2

⊕

4·2

⊕

3·0

⊕

3 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 5

2

=

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 4

9·0

a a a a a a 000 ⊕ 011 ⊕ 020 ⊕ 100 a a a 000 ⊕ 022 ⊕ 020 ⊕ 000 a a a 101 ⊕ 000 ⊕ 010 ⊕ 200 a a a 101 ⊕ 011 ⊕ 010 ⊕ 100 a a a 101 ⊕ 022 ⊕ 010 ⊕ 000 a a a 202 ⊕ 000 ⊕ 000 ⊕ 200 a a a 202 ⊕ 011 ⊕ 000 ⊕ 100 a a a

000 ⊕ 000 ⊕ 020 ⊕ 200

202 ⊕ 022 ⊕ 000 ⊕ 000

3

2

7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 5

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 4

=

2 2 0

3

7 7 1 2 1 7 7 7 0 2 2 7 7 7 0 1 1 7 7 7 2 1 2 7 7 7 1 2 2 7 7 7 7 1 0 2 7 7 7 0 1 2 7 5 2 2 1

6.4 LDD design

An LWL can be described by an LDD. To explain the type of decomposition used in nodes of

a

a

LDD, let us analyze the LW L = x1 ∨ 2x1 ∨ 3x2 . Due to the associative law that holds for each

a

a

a

operator ¯, the LWL can be rewritten as LW L = x1 ∨ (2x1 ∨ 3x2 ), where the integer coefficient

a

of x1 is equal to 1 and (2x1 ∨ 3x2 ) is a value of the LWL if x1 is substituted with 0. Hence,

a

the node of the LDD corresponds to the expression: LW L = d0 x ¯ LW L|x=0 . The algorithm to generate a set of LDDs from an MVL network is similar to the LAR-based LDD model. 17

LDD model

f Level of initial MVL circuit

x1 x2 x1 x2 x1 x2

MAX

∧

3 f1

∧

0

MAX

1

3 f2

∧

0

MAX

∨

0

0

2

3 f3

∨

∧

0

0

∨

∨

30+32 31

30+31 32

Figure 7. An MVL circuit level with three MAX gates and the corresponding LDD

7

Comparison of linear models

A. Experiment on comparison of memory. In Table 5 we compare memory requirements LAR based model and LWL based model (columns LDD(LAR) and LDD(LWL) correspondingly). Observation. The LDD(LWL) model requires significant less memory compared to the LDD(LAR) model (over two times). B. Experiment on comparison of the number of nodes. In this experiment (Table 6) we compare two characteristics of the LAR-based model and LWL-based model: (i) the number of nodes (column #N(Nmax )), along with the maximal number of nodes in brackets, and (ii) the number of digits in terminal nodes #W(Wmax ), along with the maximal number of ternary digits assigned to a node (in brackets). For example, circuit C6228 is represented by a set of LAR based LDDs, LDD(LAR), with total number of nodes #N=6917. In the set of 245 LDDs, there exists an LDD with maximal number of nodes #Nmax =256. The total number of ternary digits #W in terminal nodes is equal to 21456, i.e #W=21456. One of the terminal nodes corresponds to the weight #Wmax =1536 ternary digits. One can compare these characteristics with LWL based LDDs (columns LDD(LWL)). Observation. The total number of nodes #N in both model is approximately the same (line Total). But we observe significant difference (up to 20%) for some circuits. The total number of digits in terminal nodes #W is significantly less in the LDD(LWL) model (about three times). C. Experiments on comparison of CPU time calculation by LDDs. In Table 7 we give two characteristics, namely CPU time to design the LDD-based NLN and runtime to calculate MVL functions on the NLN models. The columns LDD(LAR) and LDD(LWL) contain CPU time to transform a circuit given in ISCAS format to the LDD format, for LDDs derived from LAR and LWL, respectively. In the column Mailbox we place CPU time required to design links between LDDs. In the next three columns we present results of a simulation of functions calculated for 10,000 randomly generated input assignments. The columns Circuit, LDD(LAR) and LDD(LWL) contain the average CPU time for ISCAS format, LDD format derived from LAR, and LDD format accordingly. 18

Observation: CPU time of all models is almost the same. Table 5. Comparison of the size of memory for LDDs in EDIF format Test C17 C432 C499 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552 Total

IN/OUT 5/2 36/7 41/32 60/26 41/32 33/25 233/64 50/22 178/123 32/32 207/107

Memory [bytes] LDD(LAR) LDD(LWL) 201 48 4601 2688 5427 3672 8306 5832 16850 9576 22491 14980 36305 20760 54757 32329 107392 48246 68572 52778 271970 73632 596872 264541

Table 6. Comparison of the number of nodes and digits in LDDs for EDIF format T E S T Name IN/OUT c17 5/2 C432 36/7 C499 41/32 C880 60/26 C1355 41/32 C1908 33/25 C2670 233/64 C3540 50/22 C5315 178/123 C6288 32/32 C7552 207/107 Total

LDD(LAR) #N(Nmax ) #W(Wmax ) 23(5) 54(12) 503(46) 1425(135) 880(105) 2682(408) 860(59) 2718(321) 1354(129) 4146(384) 1140(71) 3291(213) 1715(228) 5334(789) 2397(202) 7389(711) 3977(356) 12669(1395) 6917(256) 21456(1536) 5935(407) 17796(1218) 25701(1415) 78960(2627)

LDD(LWL) #N(Nmax ) #W(Wmax ) 15(3) 18(4) 421(36) 531(45) 717(72) 938(136) 728(58) 957(127) 1149(96) 1426(128) 944(53) 1213(113) 1550(172) 1963(319) 1997(151) 2746(244) 3432(223) 4866(559) 5952(255) 7150(510) 4937(296) 6372(442) 21842(1864) 28180(7122)

Table 7. Comparison of the RUN time Test C17 C432 C499 C880 C1908 C1355 C2670 C3540 C5315 C6288 C7552 Total

CPU time to design [s] LDD(LAR) LDD(LWL) Mailbox 0.00 0.00 0.00000 0.04 0.01 0.0014 0.15 0.02 0.0017 0.10 0.05 0.0083 0.12 0.39 0.0760 0.25 0.07 0.0200 0.91 0.24 0.1900 1.14 0.29 0.2400 2.06 0.51 0.5150 1.43 0.42 0.4950 3.69 0.69 0.9600 9.70 2.66 2.696

19

CPU time to calculate [ms] Circuit LDD(LAR) LDD(LWL) 0.00 0.00 0.00 0.10 0.15 0.12 0.14 0.16 0.14 0.18 0.33 0.30 0.24 0.25 0.74 0.24 0.28 0.45 0.37 0.49 1.02 0.44 0.59 1.49 1.24 1.58 2.29 1.10 2.19 2.60 2.01 2.34 3.83 6.06 8.36 12.98

Concluding remarks We have shown that the boundary cases of the word-level expressions, LARs and LWLs, allow an arbitrary MVL circuit to be represented by a set of LDDs planar by their nature. We show also the behavior of the word-level DDs under the condition of linearity, namely, an LDD-based model has no ability to optimize the initial circuit. Hence, we do not manipulate the LDD nodes in order to optimize their characteristics. In contrast, optimization is the main ability of the traditional DDs. Thus, the LDD models might be considered as a form of circuit representation, not the manipulation tool. One can consider this effect as the drawback of the LDDs. Our current study is focused on combining state-of-the-art DD technique with understanding of the boundary case, LDD. For example, we conduct the experiments on the mapping of the LDDs to FPGA, combining word-level DDs and LDDs, compared power dissipation using DD and LDD techniques. We considered a number of useful characteristics of the LDD based models. The expected high ”cost” of achieving the linearity and planarity of the proposed circuit models has not been observed. Instead, the LDD representation exhibits drastically less memory needs compared to some traditional circuit formats (1.5-6 times compared to ISCAS format). The results of comparison with EDIF format are even more impressive. We continue our experimental study with complex interconnected networks. If successful for industrial networks, the proposed approach can tackle the problems of realization of complex interconnected systems like neural networks. In spite of the limitations of LDD models, we believe that they might be used to alternate word-level DDs for MVL network design. Acknowledgment. The authors thank to Prof. C. Moraga (Germany) and Prof. R. Stankovic (Yugoslavia) for long-term interest in the area of study and useful remarks. The authors are grateful to Prof. G. W. Dueck (Canada) for his help and critical remarks.

References [1] V. Antonenko, A. Ivanov, V. Shmerko, Linear Arithmetical Forms of k-valued Logic Functions and their Realization on Systolic Arrays, Automation and Remote Control (USA), vol. 56, no. 3, Pt. 2, 1995, pp. 419-432 [2] M. Beynon, J. Buckle, On Planar monotone computation of Boolean functions, Theoretical Computer Science. Elsevier Science Publishers B.V. (North-Holland), vol. 53, 1987, pp. 267 - 279 [3] R. Bryant, Y. Chen, Verification of Arithmetic Functions Using Binary Moment Diagrams, Proc. Design Automation Conf., 1995, pp. 535-541 [4] E. Eris, J. C. Muzio, Spectral Testing of Circuit Realisations Based on Linearizations, IEE Proc., Pt. E, 1986, no. 2, vol. 133, pp. 73 -78 [5] V. Feinberg, A. Levin, E. Rabinovich, VLSI Planarization Methods, Models, Implementation, Kluwer Academic Publishers, 1997 [6] M. Keim, M. Martin, B. Becker, R. Drechsler, P. Molitor, Polynomial Formal Verification of Multiplies, Proc. VLSI Test Symp., 1997, pp. 150-155

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[7] V. K. P. Kumar, Y-C. Tsai, Designing Linear Systolic Arrays, Journal of Parallel and Distributed Computing, no. 7, 1989, pp. 441-463 [8] R. J. Lipton, R. E. Tarjan, Applications of Planar Separator Theorem, SIAM Journal Comput. vol. 9, no. 3. 1980, pp. 615 - 627 [9] V. Malyugin, Realization of Boolean Function’s Corteges by Means of Linear Arithmetical Polynomial, Automation and Remote Control (USA), vol.45, no. 2, Pt. 1, 1984, pp. 239-245 [10] V. Malyugin, Parallel Calculation by Means of Arithmetical Polynomials, Physical and Mathematical Publishing Company, Russian Academy of Sciences Moscow, Russia, 1997 (In Russian) [11] S. Minato, Binary Decision Diagrams and Applications for VLSI CAD. Kluwer Academic Publishers, 1996 [12] S. Muroga, T. Ibaraki, Design of Optimal Switching Networks by Integer Programming, IEEE Trans. on Computers, 1972, no. 6, vol. C-21, pp. 573-582 [13] M. Nakajima, M. Kameyama, Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy, Proc. IEEE 26-th Int. Symp. on Multiple-Valued Logic, 1996, pp. 104 - 109 [14] T. Sasao, J. T. Butler, Planar Decision Diagrams for Multiple-valued Functions, Int. Journal on MultipleValued Logic, vol. 1, 1996, pp. 39 - 64 [15] R. S. Stankovic, T. Sasao, C. Moraga, Spectral Transform Decision Diagrams, In T. Sasao, M. Fujita (Eds) Representations of Discrete Functions, Kluwer Academic Publishers, 1996, pp.55-92 [16] S. Yanushkevich, V. Maluygin, P. Dziurzanski, V. Shmerko, Linear Models of Multiple-Valued Networks, Automation and Remote Control (USA), 2002, invited paper, to appear

Appendix. Data transmission between the LDDs In the Appendix we give the details of the data transmission between LDDs. The communication between LDDs is organized using the technique similar to one used in linear systolic arrays [7]. This result is also useful in procedure for data transmission between word-level DD and LDDs (mixed circuit models). We compare data transmission between the two types of the word-level LDDs, LAR based LDDs and LWL based LDDs. Let us consider a 3-valued 3-level circuit (Figure 8) that includes three LDDs in each case. Corresponding schemes of the data transmission are given in Figure 9. Link INPUTS carries information about the input assignment and their routes of transmission. Next link, MAILBOX: 1 LDD, receives information from the link INPUTS, processing the data in terminal nodes and sends results to the next link MAILBOX: 2 LDD, etc. Denote the variable assignment as XIN = [x1 x2 x3 ]. Suppose x1 = 2, x2 = 0 and x3 = 1, i.e. XIN = [201]. A. LAR based LDD model, Figure 9(a). The values of pseudo-variables have to be calculated as follows Gate 1"(j = 1): Gate 2"(j = 2):

Inputs x1 = 2, x3 = 1 Inputs x1 = 2, x2 = 2

⇐⇒ ⇐⇒

Pseudo-variables: Pseudo-variables:

x◦1 = 0, x◦3 = 1, (µ1 = 2) x◦4 = 1, x◦2 = 0, (µ2 = 2)

Although variable x1 = 2 is an input of two ternary gates at the first circuit level, when converted into pseudovariables, both of the instances have to be substituted with different pseudo-variables. It is due to the fact that a pseudo-variable value depends not only on a value of the given variable, but also on a value of the other input of the gate. In the example, for the first MODSUM gate, x1 x3 = 21 ⇒ x◦1 x◦3 = 01, and for the second MODSUM gate x1 x2 = 22, so the corresponding variables take values 10. Thus, in the first gate the pseudo-variable corresponding to x1 is equal to 0, whereas in the second MODSUM gate it equals 1. This is why we have to treat the second instance of pseudo-variable of x1 as independent of the x◦1 and thus name it as x◦4 .

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pDA

0 pDA

0 x4o

pDA

0 . 5

4

. 2

1

5

. 0

0

-3 -3

pDA

0 4

. 3

-3 -3 +2 3

x2o 5

2 3 +3 +2 3 +3

1

-3 -3 +2 3

x3o 2

pDA

0

x1o 2

pDA

3

-3 -3

. 2

0

x1o

0

3 +3

2

pDA

y1o

z1o

0 1

pDA

2 3 +3

0 . 2

1

1

1

. 0

3 +2 3

z2o 0

2 3 +3

3



x1

x1

x3

x3

y1






y1 x1







z1

z1



x1 



z2

f





x4

x1 x2

z2







x2


  







   



 















 



Figure 8. 3-level ternary circuit and its LAR based LDD model and LWL based LDD model

The (binary) values of pseudo-variables are multiplied by values from terminal nodes, and then results are added accordingly (7) L

= 30 (21 − 10x◦1 − 14x◦3 ) + 33 (21 − 10x◦4 − 14x◦2 ) = 588 − 10x◦1 − 14x◦3 − 270x◦4 − 378x◦2 = 588 − 14 − 270 = 304.

Using the masking operator (8), the values of outputs f1 = 0 and f2 = 1 are extracted f1

=

Ξ3·0+2 {304} =

j 304 k 32

mod 3 = 0,

f2 = Ξ3·1+2 {304} =

j 304 k 35

mod 3 = 1.

After computing of the first level outputs, values f1 = 0 and f2 = 1 are transmitted into nodes corresponding to inputs y1 and z2 , which are a fan-out of outputs f1 and f2 . However, in order to not deal with huge integers, our implementation utilizes the following simplification. Notice, that under valid input assignments, for each pair of LDD nodes corresponding to both inputs of one gate, one addition of maximum two integers is carried out. These integers and a result of addition are from a scope < −27, 27 >. In our example, for the first MODSUM gate, Wx◦1 · x◦1 = 0 (as a result of multiplication by xc1 irc = 0), Wx◦3 · x◦3 = −14, and the free terminal node W0 = 21. Addition of these integers gives 7. Similar calculations are performed for nodes corresponding with the second MODSUM gate, where Wx◦4 · x◦4 = −10 is added to W0 = 21 and a result of the sum equals 11. In our implementation of the algorithm, we extract output values f1 and f2 using the masking operator f1

= Ξ2 {7} =

j7k mod 3 = 0, 32

f2 = Ξ2 {11} =

j 11 k 32

mod 3 = 1.

Similarly, a value of the second gate output is transmitted into the first node of the third LDD, as the input z1 is a fan-out of the output. Then, after computation, the primary output value f = 1 is obtained.

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B. LWL based LDD model, Figure 9(b). The MODSUM operation for the two bits is performed, so f1 = 2 ⊕ 0 ⊕ 1 = 0 and f2 = 2 ⊕ 2 ⊕ 0 = 1. The values from terminal nodes are added accordingly: L = 30 y 1 + 3 1 z 2

=

30 · 0 + 31 · 1 = 3.

After computing the first level outputs, extracted values y1 = Ξ02 =

j3k mod 3 = 0 30

z2 = Ξ12 =

j3k mod 3 = 1 31

and

are transmitted into nodes corresponding to inputs y1 and z2 . Then, the extracted value of the output y1 is transmitted to the second node of the second LDD (2LDD) and the value of the second output z2 is transmitted to the second node of the third LDD (3LDD). Next, the value of the second level’s output z1 composed of the single gate MIN and calculated as z1 = 0 ∨ 1 = 0 is transmitted to the first node of the second LDD (2LDD). Finally the value calculated on the second level (composed of single MAX gate) f1 = 0 ∨ 1 = 1 is transmitted to the output of the circuit.

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INPUTS

V V V V V V V V V V V V V V x1 V

2 To : 1 LDD 1 node 6 6 value x 2 6 1 6 −−−−−−−−− 6 6 To : 1 LDD 6 6 ???node 6 6 value x3 1 6 6 −−−−−−−−− 6 6 To : 1 LDD 6 6 3 node 6 6 value x1 2 6 6 −−−−−−−−− 6 6 To : 1 LDD 6 6 4 node 6 6 value x2 2 6 6 −−−−−−−−− 6 2 LDD 6 To : 4 2 node value

3 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 5

2 6 6 6 6 6 6 6 4

0

MAIL BOX: 1 LDD 3 To : 2 LDD 1 node 7 7 value 0 7 7 −−−−−−−−− 7 To : 3 LDD 7 7 2 node 5 value 1

V V V V V V

XIN = [2 0 1]

2 4

X1LDD = [1 0]

MAIL BOX: 2 LDD 3 To : 3 LDD 1 node 5 value 0

V V V



X2LDD = [0]

W x1

0⋅0 0⋅0 0⋅0 -1⋅0 -1⋅0 2⋅0

W x3

0⋅1 0⋅1 0⋅1 -2⋅1 1⋅1 1⋅1

W x4

-1⋅1 -1⋅1 2⋅1

MAIL BOX: 3 LDD  To : Output f1 value 1

V

V

X3LDD = [1]

+ +

W y1

0⋅1 0⋅1 0⋅1

W x2

-2⋅0 1⋅0 1⋅0

2⋅0 1⋅0 0⋅0

W z1

0⋅0 1⋅0 2⋅0

W z2

0⋅1 0⋅1 1⋅1

+

+

W x1

0⋅0 0⋅0 0⋅0

+

1⋅0 1⋅0 0⋅0

+

+

+

W0

2

1

0

2

1

0

W0

0

0

0

W0

2

1

0

X1 LDD

1

0

2

0

2

1

X2 LDD

0

0

0

X3 LDD

2

1

1

(a) Data transmission between LAR based LDDs INPUTS

V V V V V V V V V V V V V V V V

2 To : 1 LDD 1 node 6 6 µ 0 6 6 value 2 6 6 −−−−−−−−− 6 6 To : 1 LDD 6 6 2 node 6 6 µ 1 6 6 value 0 6 6 −−−−−−−−− 6 6 To : 1 LDD 6 6 3 node 6 6 µ 2 6 6 value 1 6 6 −−−−−−−−− 6 6 To : 2 LDD 6 6 1 node 4 µ 0 value

2

XIN = [2 0 1]

3 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 5

2 6 6 6 6 6 6 6 6 6 6 6 4

MAIL BOX: 1 LDD 3 To : 2 LDD 2 node 7 7 µ 0 7 7 value 0 7 7 −−−−−−−−− 7 To : 3 LDD 7 7 2 node 7 7 5 µ 1 value 1

V V V V V V V V

X1LDD = [1 0]

MAIL BOX: 2 LDD 3 To : 2 LDD 6 7 1 node 6 7 4 µ 5 0 value 0

2

V V V V

X2LDD = [0]

MAIL BOX: 3 LDD 3 To : Output f1 4 µ 5 0 value 1

2

V

V V

X3LDD = [1]

TW x1

2 2

TW x1

2

TW x2

2 0

TW y1

2

TW z1

0

TW x3

0 1

X LDD2

2

TW z2

1

X LDD1 1 0

X LDD2

0

X LDD3

1

(b) Data transmission between LWL based LDDs

Figure 9. Realization of links (mailbox) for data transmission between LDDs for the circuit given in Figure 8

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